MOTOROLA MC33121FN

Order this document
by MC33121/D
SEMICONDUCTOR TECHNICAL DATA
Thin Film Silicon Monolithic Integrated Circuit
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P SUFFIX
PLASTIC PACKAGE
CASE 738
20
The MC33121 is designed to provide the interface between the 4–wire side of
a central office, or PBX, and the 2–wire subscriber line. Interface functions
include battery feed, proper loop termination AC impedance, hookswitch
detection, adjustable transmit, receive, and transhybrid gains, and single/
double fault indication. Additionally, the MC33121 provides a minimum of 58 dB
of longitudinal balance (4–wire and 2–wire).
The transmit and receive signals are referenced to analog ground, while
digital signals are referenced to digital ground, easing the interface to codecs,
filters, etc. The 2 status outputs (hookswitch and faults) and the Power Down
Input are TTL/CMOS compatible. The Power Down Input permits local
shutdown of the circuit.
Internal drivers allow the external loop current pass transistors to be standard
bipolar transistors (non–Darlington).
The MC33121 is available in a 20 pin DIP and a 28 pin PLCC surface mount
package.
1
28
FN SUFFIX
PLCC
CASE 776
1
ORDERING INFORMATION
Temperature
Range
Device
MC33121P
58 dB Longitudinal Balance Guaranteed; 4–wire and 2–wire
Transmit, Receive, and Transhybrid Gains Externally Adjustable
Return Loss Externally Adjustable
Proper Hookswitch Detection With 30 kΩ Leakage
Single/Double Fault Indication With Shutdown for Thermal Protection
Critical Sense Resistors Included Internally
Standard Power Supplies: – 21.6 V to – 42 V, and + 5.0 V, ± 10%
On–Hook Transmission
Power Down Input (TTL and CMOS Compatible)
Operating Ambient Temperature: – 40°C to + 85°C
Available in a 20 Pin DIP and 28 Pin PLCC Package
– 40° to + 85°C
Package
Plastic DIP
MC33121FN
PLCC
CURRENT
MIRROR
VDD (+5.0 V)
VDG
(DIG. GND)
SIMPLIFIED BLOCK DIAGRAM
VCC
EP
CURRENT
MIRROR
*
CURRENT
MIRROR
BP
TIP
PDI/ST2
–
+
CP
VEE
ST1
*
TSI
RSI
HOOK STATUS AND
FAULT DETECTION
AND BIAS CONTROL
VCC
RING
CN
EN
VEE
(BATTERY)
*
*
CURRENT
MIRROR
CURRENT
MIRROR
VAG
(ANA. GND)
RXI
BIAS
–
+
BN
+
–
+
–
CURRENT
MIRROR
TXO
RFO
CF
VQB
MC33121
* Indicates trimmed resistor
REV 1.0
4/96

Motorola, Inc. 1996
MOTOROLA
MC33121
1
MAXIMUM RATINGS
Characteristic
Supply Voltage
(with respect to VCC)
(with respect to VDG)
Symbol
Value
VEE
VDD
– 60, + 0.5
– 0.5, + 7.0
Unit
Vdc
Voltage
@ PDI, (with respect to VDG)
@ CP, CN
EP, TSI
BP
RSI, EN
BN
Vin
Vdc
Junction Temperature
TJ
150
°C
Storage Temperature
Tstg
– 65 to + 150
°C
– 0.5, + 7.0
VEE – 0.5, VCC + 0.5
VCC – 7.0, VCC + 0.5
VCC – 14, VCC + 0.5
VEE – 0.5, VCC + 14
VEE – 1.0, VEE + 21
* Devices should not be operated at these limits. The “Recommended Operating Conditions” table
provides for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Min
Typ
Max
VEE
VDD
– 42
+ 4.5
– 24
+ 5.0
– 21.6
+ 5.5
(with respect to VCC)
(with respect to VCC)
(with respect to VAG)
VAG
VDG
– 3.0
– 3.0
– 3.0
0
0
0
+ 10
+ 7.0
+ 10
(with respect to VEE)
(with respect to VCC and VAG)
VDD
—
3.5
—
—
47.5
—
IL
15
—
50
mA
PDI Input Voltage
VPDI
0
—
VDD
Vdc
Sink Current
ST1
ST2
IST1L
IST2L
0
0
—
—
1.0
1.0
STX
SRX
– 48
– 48
—
—
+ 3.0
+ 3.0
dBm
RL
0
0
—
—
2.0 k
800
Ω
External Transistor Beta
Hfe
40
—
500
A/A
Operating Ambient Temperature (See text for derating)
TA
– 40
—
+ 85
°C
Unit
Vdc
Supply Voltage
(with respect to VCC)
(with respect to VDG)
Loop Current
mA
Transmit Signal Level at Tip & Ring
Receive Signal Level at VRX
Loop Resistance
Unit
VEE = – 42 V
VEE = – 24 V
All limits are not necessarily functional concurrently.
ELECTRICAL CHARACTERISTICS
(VEE = – 24 V, VDD = + 5.0 V, unless otherwise noted. VCC = VAG = VDG = 0 V, TA = 25°C, see Figure 1.)
Characteristic
Symbol
Min
Typ
Max
IEEN
IEEF
– 2.7
– 72
– 1.0
– 55
—
– 41
IDDN
IDDF
—
4.0
1.4
7.0
2.7
14
40
40
62
52
—
—
37
37
52
48
—
—
POWER SUPPLIES
VEE Current
On Hook (RL > 10 MΩ, VEE = – 42 V)
Off Hook (RL = 0 Ω, VEE = – 42 V)*
VDD Current
On Hook (RL > 10 MΩ, VDD = + 5.5 V)
Off Hook (RL = 0 Ω, VDD = + 5.5 V)
VEE Ripple Rejection
f = 1.0 kHz, @ VTX (4–wire)
f = 1.0 kHz, @ Tip/Ring (2–wire)
VDD Ripple Rejection
f = 1.0 kHz, @ VTX (4–wire)
f = 1.0 kHz, @ Tip/Ring (2–wire)
mA
PSRR
dB
* Includes loop current.
MC33121
2
MOTOROLA
ELECTRICAL CHARACTERISTICS
(VEE = – 24 V, VDD = + 5.0 V, unless otherwise noted. VCC = VAG = VDG = 0 V, TA = 25°C, see Figure 1.)
Characteristic
Symbol
Min
Typ
Max
IL(max)
IL
IL(min)
37
21
16
41
27
17.5
51
34
—
Battery Feed Resistance (RRF = 4.7 k, RL = 796 Ω)*
RBF
475
575
675
Hookswitch Threshold
On–to–Off Hook
Off–to–On Hook
RNF
RFN
2.0
—
4.1
7.7
—
10
Fault Detection Threshold
Ring–to–Ground (RL = 367 Ω)
Tip–to–Battery (RL = 367 Ω)
RRG
RTB
600
600
1100
1100
—
—
GTX1
—
0.328
—
GTX2
– 0.3
– 0.1
– 0.15
—
0
0
0
± 0.1
0.3
0.1
0.15
—
—
0.05
—
Unit
LOOP FUNCTIONS
Loop Current
Maximum (RRF = 4.7 k, RL = 10 Ω)
Nominal (RRF = 4.7 k, RL = 367 Ω)
Minimum (RRF = 4.7 k, RL = 796 Ω)
mA
Ω
kΩ
Ω
* Calculated from [(24/IL(min)) – 796]
GAIN LEVELS
Transmit Voltage Gain (CP, CN to TXO)
Transmit Voltage Gain (VTX/VL)
VL = 0 dBm, f = 1.0 kHz
VL = 0 dBm, f = 3.4 kHz, with respect to GTX2
VL = + 3.0 dBm, f = 1.0 kHz, with respect to GTX2
VL = – 48 dBm, f = 1.0 kHz, with respect to GTX2
V/V
dB
Transmit Distortion (at Pin 11)
(f = 300 Hz to 4.0 kHz, – 40 dBm ≤ VT–R ≤ + 5.0 dBm)
THDT
Receive Current Gain (IEP/IRXI)
GRX1
94
102
110
GRX2
– 0.3
– 0.1
– 0.15
—
0
0
0
± 0.1
0.3
0.1
0.15
—
THDR
—
0.05
—
%
RL
30
> 40
—
dB
THR
—
44
—
dB
LB
58
58
64
64
—
—
dB
2–Wire Balance, f = 330 Hz, Zac = 600 Ω (@ Tip/Ring)
4–Wire Balance, f = 330 Hz, Zac = 600 Ω (@ VTX)
58
58
64
64
—
—
2–Wire Balance, f = 3.3 kHz, Zac = 600 Ω (@ Tip/Ring)
4–Wire Balance, f = 3.3 kHz, Zac = 600 Ω (@ VTX)
53
53
60
60
—
—
2–Wire Balance, f = 1.0 kHz, Zac = 900 Ω (@ Tip/Ring)
4–Wire Balance, f = 1.0 kHz, Zac = 900 Ω (@ VTX)
—
—
62
62
—
—
Signal Balance, f = 1.0 kHz (Figure 3)
40
55
—
150
180
210
8.5
16
—
Receive Voltage Gain (VL/VRXI) (RL = 600 Ω)
VRXI = 0 dBm, f = 1.0 kHz
VRXI = 0 dBm, f = 3.4 kHz, with respect to GRX2
VRXI = + 3.0 dBm, f = 1.0 kHz, with respect to GRX2
VRXI = – 48 dBm, f = 1.0 kHz, with respect to GRX2
Receive Distortion
(f = 300 Hz to 4.0 kHz, – 40 dBm ≤ VRXI ≤ + 5.0 dBm)
Return Loss (Reference = 600 Ω resistive, f = 1.0 kHz)
Transhybrid Rejection (RL = 600 Ω resistive, f = 1.0 kHz, Figure 4)
%
mA/mA
dB
LONGITUDINAL SIGNALS (VCM = 1.0 Vrms, see Figures 1 and 2)
2–Wire Balance, f = 1.0 kHz, Zac = 600 Ω (@ Tip/Ring)
4–Wire Balance, f = 1.0 kHz, Zac = 600 Ω (@ VTX)
Longitudinal Impedance, RS = 9100 Ω
Maximum Longitudinal Current, per side
f = 1.0 kHz, ILoop = IL(min), CT = 0.1 µF
VEE = – 42, VCM = 5.12 Vrms
MOTOROLA
ZLong
ILong(max)
Ω
mA
MC33121
3
ELECTRICAL CHARACTERISTICS
(VEE = – 24 V, VDD = + 5.0 V, unless otherwise noted. VCC = VAG = VDG = 0 V, TA = 25°C, see Figure 1.)
Characteristic
Symbol
Min
Typ
Max
Unit
ST1 Output Voltage
Low (IST1 = 1.0 mA, VDD = 5.5 V)
High (IST1 = – 100 µA, VDD = 4.5 V)
VOL
VOH
VDG
2.4
0.17
3.2
0.4
—
ST2 Output Voltage
Low (IST2 = 1.0 mA, VDD = 5.5 V)
High (IST2 = – 100 µA, VDD = 4.5 V)
VOL
VOH
VDG
2.4
0.17
4.3
0.4
—
Time Delay
Hookswitch Closure to ST1 Change
Hookswitch Opening to ST1 Change
tST11
tST12
—
—
10
200
—
—
tHS
—
19
—
ms
tST21
tST22
—
—
18
10
—
—
ms
µs
– 1250
—
– 800
– 800
– 300
—
VDG
2.0
—
—
0.8
VDD
—
—
0.82
0.95
—
—
VTXO
– 400
+ 30
+ 400
mVdc
LOGIC INTERFACE
Vdc
µs
Hookswitch Closure to 90% of Loop Current (CT = 0.1 µF)
PDI Taken High–to–Low to 10% of Loop Current
PDI Taken Low–to–High to 90% of Loop Current
PDI Input Current
VPDI = 3.0 V, RL = 367 Ω, VDD = 5.0 V
VPDI = 0 V, RL = 367 Ω, VDD = 5.5 V
µA
IIH
PDI Input Voltage
Low
High
Vdc
VIL
VIH
MISCELLANEOUS
VQB Voltage (VQB – VEE)
@ IL = 20 mA
@ IL = 40 mA
VQB
TXO Offset Voltage (VTXO – VAG) @ RL = 600 Ω
Vdc
ITXO
± 275
± 800
—
µA pk
VRXOS
—
0.8
—
mVdc
VAG Input Current @ RL = 600 Ω
IVAG
—
0.2
—
µA
Idle Channel Noise (with C–message filter, RL = 600 Ω)
@ TXO (Pin 11)
@ Tip/Ring
NIC4
NIC2
—
—
– 10
– 5.0
—
—
—
—
62
36
—
—
TXO Output Current
RXI Offset Voltage (VRXI – VAG) @ RL = 600 Ω
Thermal Resistance — Junction to Ambient
(Either package, in still air, soldered to a PC board)
MC33121
4
dBrnc
θJA
(@ TA = + 25°C)
(@ TA = + 85°C)
°C/W
MOTOROLA
20
19
IEP
VDD 15
VCC
12
ST2/PDI
EP
+ 5.0 V
PDI/ST2
0.01
18
RP
100
IL
RC
17
1.0 k
TIP
RS
16
9.1 k
RS
VL RL
RC
RP
ST1
CP
VDG
TSI
VAG
13
ST1
14
9
IRXI
MC33121
5
9.1 k
RING
BP
CT
0.1
4
1.0 k
3
0.01 100
2
1
RXI
RSI
CN
RFO
BN
TXO
EN
CF
8
RRF
4.7 k
RRO
20.3 k
30.9 k
CRO
1.0 µF
11
VQB
VEE
RRX
10
1.0 µF
7
2.0 k
6
301 CCF
1.0 µF
20
RECEIVE
IN (VRXI)
TRANSMIT
OUT (VTX)
+10.13 dB
CQB (10 µF)
– 24 V
Components shown for a 600 Ω system.
Three grounds are connected directly together.
Figure 1. Test Circuit
VCM
368
0.01%
TIP
MC33121 TEST CIRCUIT
(FIGURE 1)
2.0 µF
368
0.01%
VTX
V4
4–Wire Balance = 20 (log V4/VCM)
2–Wire Balance = 20 (log V2/VCM)
RING
1.0 Vrms
0 dB DIFF.
AMPLIFIER
V2
Figure 2. Longitudinal Balance Test
(Per IEEE–455)
368
0.01%
TIP
MC33121 TEST CIRCUIT
(FIGURE 1)
VB
368
0.01%
RING
VRXI
Vin
0 dBm
1.0 kHz
Signal Balance = 20 (log VB/Vin)
Figure 3. Signal Balance Test
MOTOROLA
MC33121
5
Figure 4. Application Circuit
MC33121
6
MOTOROLA
RL
TIP
RING
CC
0.01
VEE
RP
100
RP
100
Component values shown
for a 600 Ω system.
VEE
IL
CC
0.01
–24 V
MJD243
1.0 k, 2%
RC
9.1 k
RS
9.1 k
RS
1.0 k, 2%
RC
MJD253
0.1
1
2
3
4
5
16
17
18
19
20
VEE
EN
BN
CN
RSI
TSI
CP
BP
EP
VCC
MC33121
13
12
15
VQB
CF
TXO
RFO
RXI
6
7
11
8
10
VAG 9
VDG 14
ST1
ST2/PDI
VDD
20
300
CRO
1.0 µ F
RRF
4.7 k
5.0 µF
30.6 k
CQB (10 µF)
600
0.005
1.0 µF
15.8 k
600
ST1
ST2/PDI
CCF (1.0 µF)
10 k
RTX1
RRO RRX
20.3 k
CT
+5.0 V
–
+
31.6 k
RTX2
TRANSMIT
OUT (VTX )
RECEIVE IN (VRXI )
PIN FUNCTION DESCRIPTION
Pin
S b l
Symbol
DIP
PLCC
D
Description
i i
VCC
20
28
Connect to noise–free battery ground. Carries loop current and some bias currents.
EP
19
27
Connect to the emitter of the PNP pass transistor.
BP
18
26
Connect to the base of the PNP pass transistor.
CP
17
24
Connect to TIP through a current limiting protection resistor (RC). CP is the noninverting
input to the internal transmit amplifier (Figure 28). Input impedance is 31 kΩ.
TSI
16
23
Sense input. Connect to TIP through a current limiting protection resistor (RS) which also
sets the longitudinal impedance. Input impedance is 100 Ω to VCC.
VDD
15
22
Connect to a + 5.0 V, ± 10% supply, referenced to digital ground. Powers logic section and
provides some bias currents for the loop current drivers.
VDG
14
20
Digital Ground. Reference for ST1, ST2 and VDD. Connect to system digital ground.
ST1
13
18
Status Output (TTL/CMOS). Indicates hook switch status — high when on–hook, low when
off–hook, and pulse dialing information. Used with ST2 to indicate fault conditions.
ST2/PDI
12
17
Status output and an input (TTL/CMOS). As an output, ST2 can indicate hook status — Low
when on–hook, high when off–hook. Used with ST1 to indicate fault conditions. As an input,
it can be taken low (when off–hook) to deny subscriber loop current.
TXO
11
16
Transmit voltage output. Amplitude is 1/3 that across CP and CN. Nominally capable of
800 µA output current. DC referenced to VAG.
RXI
10
14
Receive current input. Current at this pin is multiplied by 102 at EP and EN to generate loop
current. RXI is a virtual ground at VAG level. Current flow is out of this pin.
VAG
9
13
Analog ground, reference for TXO and RXI. Connect to system analog ground. Current flow
is into this pin.
RFO
8
12
A resistor from this pin and RXI sets the maximum loop current and DC feed resistance.
Minimum resistor value is 3.3 k (see Figures 5 to 7).
CF
7
10
A low leakage capacitor between this pin and VAG provides DC and AC signal separation. A
series resistor is required for battery supply turn–on/off transient protection (Figure 4).
VQB
6
8
Quiet Battery. A capacitor between VQB and VCC filters noise and ripple from VEE, providing
a quiet battery source for the speech amplifiers. A series resistor is required for battery
supply turn–on/off transient protection (Figure 4).
RSI
5
7
Sense input. Connect to RING through a current limiting protection resistor which also sets
the longitudinal impedance. Input impedance is 100 Ω to VQB.
CN
4
6
Connect to RING through a current limiting protection resistor. CN is the inverting input to
the internal transmit amplifier (Figure 28). Input impedance is 31 kΩ.
BN
3
4
Connect to the base of the NPN pass transistor.
EN
2
3
Connect to the emitter of the NPN pass transistor.
VEE
1
2
Connect to battery voltage (– 21.6 V to – 42 V).
[
[
[
(Pins 1, 5, 9, 11, 15, 19, 21, and 25 are not internally connected on the PLCC package.)
MOTOROLA
MC33121
7
50
50
RS = 9.1 k
VEE = – 42 V
TA = 25°C
RRF = 3900 Ω
40
5100
6200
30
7500
8200
20
40
5100
6200
30
7500
8200
20
10 k
10 k
10
10
0
400
800
1200
1600
0
2000
400
600
800
1000
RL, LOOP RESISTANCE (Ω)
Figure 5. Loop Current versus Loop
Resistance and RRF
Figure 6. Loop Current versus Loop
Resistance and RRF
LOOP RESISTANCE THRESHOLD (kΩ )
15
RS = 9.1 k
VEE = – 24 V
TA = 25°C
RRF = 3900 Ω
4700
IL, LOOP CURRENT (mA)
200
RL, LOOP RESISTANCE (Ω)
50
40
5100
6200
30
7500
8200
20
10 k
10
0
200
400
600
800
13
11
9.0
7.0
5.0
6.0
7.0
8.0
9.0
RRF (kΩ)
Figure 7. Loop Current versus Loop
Resistance and RRF
Figure 8. Off–Hook to On–Hook
Threshold versus RRF
15
3.9 k ≤ RRF ≤ 10 k
4.5 V ≤ VDD ≤ 5.5 V
TA = 25°C
VEE = – 24 V
3.0
VEE = – 42 V
2.0
1.0
5.0
4.0
RL, LOOP RESISTANCE (Ω)
IDD, INTERNAL BIAS CURRENT (mA)
4.0
– 42 V ≤ VEE ≤ – 24 V
5.1 k ≤ RS ≤ 11 k
4.5 V ≤ VDD ≤ 5.5 V
TA = 25°C
5.0
3.0
1000
5.0
LOOP RESISTANCE THRESHOLD (kΩ )
RS = 9.1 k
VEE = – 28 V
TA = 25°C
RRF = 3900 Ω
4700
IL, LOOP CURRENT (mA)
IL, LOOP CURRENT (mA)
4700
– 42 V ≤ VEE ≤ – 24 V
TA = 25°C
VDD = + 5.0 V
RRF = 4700 Ω
10
5.0
6.0
7.0
8.0
9.0
10
11
12
20
30
40
RS, SENSE RESISTANCE (kΩ)
IL, LOOP CURRENT (mA)
Figure 9. On–Hook to Off–Hook Threshold versus RS
Figure 10. IDD versus Loop Current
MC33121
8
10
45
MOTOROLA
3.0
TA = 25°C
RL = OPEN
3.5
TIP–TO–VEE
VEE = – 24 V
3.0
TIP–TO–VEE
VEE = – 42 V
2.5
2.0
1.5
RING–TO–GROUND
VEE = – 42 V
1.0
5.0
7.0
RING–TO–GROUND
VEE = – 24 V
RLK , FAULT THRESHOLD (kΩ)
RLK , FAULT THRESHOLD (kΩ)
4.0
VEE = – 42 V
TA = 25°C
RING–TO–GROUND
AND/OR TIP–TO–VEE
2.4
1.2
RS = 11 k
5.1 k
0.6
0
9.0
0
11
500
1000
1500
2000
RL, LOOP RESISTANCE (Ω)
Figure 11. Fault Threshold (On–Hook) versus RS
Figure 12. Fault Threshold (Off–Hook)
versus Loop Resistance
3.0
3.0
VEE = – 28 V
TA = 25°C
RING–TO–GROUND
AND/OR TIP–TO–VEE
2.4
1.8
RLK , FAULT THRESHOLD (kΩ)
RLK , FAULT THRESHOLD (kΩ)
7.5 k
1.8
RS, SENSE RESISTANCE (kΩ)
9.1 k
RS = 11 k
1.2
7.5 k
0.6
5.1 k
VEE = – 24 V
TA = 25°C
RING–TO–GROUND
AND/OR TIP–TO–VEE
2.4
1.8
9.1 k
RS = 11 k
1.2
7.5 k
0.6
5.1 k
0
0
0
200
400
600
800
0
200
RL, LOOP RESISTANCE (Ω)
400
600
800
RL, LOOP RESISTANCE (Ω)
Figure 13. Fault Threshold (Off–Hook)
versus Loop Resistance
Figure 14. Fault Threshold (Off–Hook)
versus Loop Resistance
1.0
80
TA = 25°C
200 Ω < RL < 800 Ω
(SEE TEXT)
0.8
RIPPLE REJECTION (dB)
RLK , FAULT THRESHOLD (kΩ)
9.1 k
RING–TO–VEE
VEE = – 42 V
0.6
RING–TO–VEE
VEE = – 24 V
0.4
TIP–TO–GROUND
– 24 V ≤ VEE ≤ – 42 V
0.2
0
5.0
7.0
9.0
11
RS, SENSE RESISTANCE (kΩ)
Figure 15. Fault Threshold (Off–Hook) versus RS
MOTOROLA
VEE = – 24 V
TA = 25°C
20 mA ≤ IL ≤ 40 mA
4–WIRE
60
2–WIRE
40
20
0.02
0.1
1.0
10
20
f, FREQUENCY (kHz)
Figure 16. VDD Ripple Rejection versus Frequency
MC33121
9
80
60
RIPPLE REJECTION (dB)
RIPPLE REJECTION (dB)
80
4–WIRE
2–WIRE
40
20
0.02
VEE = – 24 V
TA = 25°C
20 mA ≤ IL ≤ 40 mA
CQB = 10 µF
0.1
10
1.0
VEE = – 24 V
TA = 25°C
20 mA ≤ ILOOP ≤ 40 mA
40
20
1.0
20
10
Figure 17. VEE Ripple Rejection versus Frequency
Figure 18. VEE Ripple Rejection
versus Frequency and CQB
6.0
0.6
VOH, OUTPUT VOLTAGE (V)
4.5 V ≤ VDD ≤ 5.5 V
TA = 25°C
0.5
VOL , OUTPUT VOLTAGE (V)
20
CQB, CAPACITOR (µF)
f, FREQUENCY (kHz)
0.4
0.3
0.2
5.0
VDD = + 5.5 V
4.0
VDD = + 4.5 V
3.0
TA = 25°C
0.1
0
2.0
0
0.5
1.0
1.5
2.0
0
–50
IOL, OUTPUT CURRENT (mA)
–100
–150
–200
IOH, OUTPUT CURRENT (µA)
Figure 19. ST1, VOL versus IOL
Figure 20. ST1, VOH versus IOH
0.6
6.0
4.5 V ≤ VDD ≤ 5.5 V
TA = 25°C
0.5
VOH, OUTPUT VOLTAGE (V)
VOL , OUTPUT VOLTAGE (V)
1.0 kHz
300 Hz 4–WIRE
4.0 kfHz
1.0 kHz
300 Hz 2–WIRE
4.0 kHz
60
0.4
0.3
0.2
VDD = 5.5 V
5.0
VDD = 4.5 V
4.0
3.0
TA = 25°C
0.1
2.0
0
0
0.25
0.50
0.75
IOL, OUTPUT CURRENT (mA)
Figure 21. ST2, VOL versus IOL
MC33121
10
1.0
0
–100
–200
–300
–400
–500
IOH, OUTPUT CURRENT (µA)
Figure 22. ST2, VOH versus IOH
MOTOROLA
VEE = – 28 V
TA = 25°C
VDD = + 5.0 V
0.6
RRF = 3900
0.5
0.4
RRF = 6200
0.3
RRF = 10 k
0.2
0
200
400
600
800
POWER DISSIPATION IN EACH TRANSISTOR (W)
IC POWER DISSIPATION (W)
0.7
0.4
VEE = – 28 V
TA = 25°C
RP = 100 Ω
0.3
6.2 k
0.2
10 k
0.1
RRF = 3.9 k
0
0
200
50
40
30
RS = 5.1 k
20
– 42 V ≤ VEE ≤ – 24 V
f = 60 Hz AND 1.0 kHz
CT > 0.1 µF FOR 1.0 kHz
CT > 1.0 µF FOR 60 Hz
10
0
20
30
IL, LOOP CURRENT (mA)
Figure 25. Maximum Longitudinal Current
versus Loop Current
MOTOROLA
600
800
Figure 24. Transistor Power Dissipation
versus Loop Resistance and RRF
40
MAX. LONGITUDINAL CURRENT, PER LEG (mArms)
MAX. LONGITUDINAL CURRENT, PER LEG (mArms)
Figure 23. IC Power Dissipation versus
Loop Resistance and RRF
RS = 11 k
400
RL, LOOP RESISTANCE (Ω)
RL, LOOP RESISTANCE (Ω)
20
ST2
RT
16
RT = 200 k
f = 1.0 kHz
VEE = – 28 V
TA = 25°C
CT IL = 20 mA
RS = 9.1 k
12
RT = 200 k
f = 60 Hz
8.0
RT = 20 k
f = 1.0 kHz
4.0
RT = 20 k
f = 60 Hz
0
0.1
1.0
10
CT (µF)
Figure 26. Maximum Longitudinal Current
versus CT, RT and Frequency
MC33121
11
FUNCTIONAL DESCRIPTION
Introduction
The MC33121 is a solid state SLIC (Subscriber Line Interface Circuit) which provides the interface between the two
wire telephone line and the four wire side of a Central Office
or PBX. Most of the BORSCHT functions are provided, specifically:
— Battery feed of the loop current to the line, with programmable maximum current for short lines and battery
feed resistance for long lines.
— Overvoltage protection through internal clamp diodes
and external resistors and diodes.
— Supervision, in that hook status is indicated in the presence of ≥ 30 kΩ leakage, and regardless of whether or
not the circuit is powered down intentionally by the Central Office or PBX. Fault conditions are detected and indicated to the system. Dialing (pulse and DTMF)
information is passed through the MC33121 to the 4–wire
side.
— Hybrid function, in that the MC33121 is a 2–to–4–wire
converter. Transmit, receive, return loss, and transhybrid
gains are independently adjustable.
Thy MC33121 does not provide ring insertion, ring trip, digital coding/decoding of the speech signals, nor test functions.
These must be provided external to this device.
The MC33121 controls two external transistors (one NPN
and one PNP) through which the loop current flows. By appropriate circuit design, the power dissipation (which can
exceed 3.0 W under certain worst case conditions) is approximately equally distributed among the two transistors and the
IC, thereby lowering junction temperatures and increasing
long term reliability. In most situations, heatsinks will not be
required.
The MC33121 incorporates critical sense resistors internally, which are trimmed for optimum performance. With this
technique, the external resistors on the two wire side, which
generally must be high wattage for transient protection reasons, can be non–precision.
Longitudinal balance is tested to a minimum of 58 dB @
1.0 kHz (refer to Electrical Characteristics and Figure 2) for
both the two–wire and four–wire side, and typically measures
in the mid–60s. The longitudinal current capability is tested to
a minimum of 8.5 mArms per side (refer to Electrical Characteristics and Figure 2) at a loop current of 20 mA.
Following is a description of the individual sections. Figure 4 is the reference schematic.
DC Loop Current
The DC loop current is determined by the battery voltage
(VEE), the load resistance across Tip and Ring, and the resistor at RFO. Varying the 4 resistors RS and RC will influence
the loop current a small amount (< 5%). The curves of Figures 5 to 7 indicate the loop current versus loop resistance,
different values of RRF, and for various values of VEE. The
graphs represent performance at TA = 25°C and after the IC
had reached a steady state temperature (> 5 minutes).
VCC
MC33121
30
3060
EP
BP
ILOOP
RP
100
TIP
1.0 k
CP
9.1 k
TSI
9.1 k
RL
1.0 k
RING
100
–
+
31 k
100 I
A
VDD
CURRENT
MIRROR
ICP
VDD
+
–
IA
VAG
RXI
IRXI
RSI
CN
ANALOG
GROUND
VQB
ICN
RRF
12.4 k
RP
ILOOP
+
–
BN
31 k
100
+
–
RFO
EN
30
3060
ICP
) ICN
3
VQB
5.0 Ω
IA = IRXI
– 24 V
VEE
10 µF
0.8 V
Figure 27. DC Loop Current Path
MC33121
12
MOTOROLA
Figure 27 is representative of the DC loop current path
(bold lines). On a long line (RL > 400 Ω), the loop current can
be determined from the following equation:
ǒŤ Ť
Ǔ
– 3.6 V • 13
+ RRFEE) {(R ) 5) • 13}
L
L
V
I
protection needed, described in another section, with 1.0 kΩ
resistors being suitable for most applications. The resulting
signal at TXO needs to be gained up to obtain 0 dB from Tip/
Ring to V TX (the 4–wire output). The common method
involves an external op amp, as shown in Figure 28, with a
gain of RTX2/RTX1. The gain from VL to VTX is:
(1)
V
TX
V
L
On short lines (RL < 400 Ω), the three diodes across the
12.4 k resistor clamp the voltage at RFO, thereby preventing
the RXI current from increasing as the load resistance is
decreased. The maximum loop current is:
I
L(max)
V • 102
+ 1.85RRF
(T
A
+ 25°C)
(2)
Receive Path
The receive path, shown in Figure 29, consists of the input
at RXI, the transistor driver amplifiers, the external transistors, and the load at Tip/Ring.
RXI is a virtual ground (DC level = VAG) and is a current
input. Current flow is out of the pin. The RXI current is mirrored to the two transistor drivers which provide a gain of
102. the two external transistors are then two current
sources, in series, operating at the same value. An additional
internal circuit (not shown) balances the two current sources
to maintain operation in their linear region.
The load current (through RL) is slightly different from the
transistor current due to the sense resistors RC and RS. The
sense resistors add to the DC loop current, but subtract from
the AC load current.
In normal operation, the current at RXI is composed of a
DC current (from RFO), an AC current (from VRX) which is
the receive signal, and an AC current from TXO, which is the
feedback signal to set the return loss (setting the return loss
is discussed in the section on AC Terminating Impedance).
The resulting AC signal at Tip is inverted from that at VRX,
while the signal at Ring is in phase with VRX.
The resistors RP are for transient protection, and their
value (defined in another section) depends on the amount of
protection required. A nominal value of 100 Ω is suitable for
most applications.
The system receive gain, from VRX to Tip/Ring, is not
described in this section since in normal applications, it
involves the feedback which sets the AC terminating impedance. The Applications Section discusses these in detail.
[
Transmit Path
The transmit path, shown in Figure 28, consists of an internal amplifier which has inputs at CP and CN, and its output at
TXO. The gain is internally fixed at 0.328 V/V (– 9.7 dB). The
output is in phase with the signal at CP (normally the same
as TIP), and is out of phase with the signal at CN. The signal
at TXO is also out of phase with that at VRX, the receive signal input, described in another section.
The TXO output can swing
3.0 Vp–p, with a nominal
current capability of ± 800 µA peak (± 275 µA minimum). The
load on TXO is the parallel combination of RTX1 and the
RRO network (described later). TXO is nominally internally
biased at the VAG DC level, but has an offset which varies
with loop current.
In normal applications, the signal at CP/CN is reduced
slightly from that at Tip/Ring by the voltage divider composed
of the external RC resistors, and the internal 31 k resistors.
The value of the RC resistors depends on the transient
[
TIP
1.0 k
CP 17
9
31 k
AC
RC
1.0 k
RING
RC
CN 4
31 k
AC
VAG
VDD
+
–
VL
(3)
If a codec/filter is used, many of which include an internal
op amp, a separate op amp is not needed. CTX is primarily
for DC blocking (of the TXO offset), and is usually large
(1.0 µF) so as to not affect the gain.
Due to the temperature dependence of a diode’s forward
voltage, the maximum loop current will change with temperature by – 0.3%/°C.
The battery feed resistance (∆VTIP/∆IL) is 400 Ω, but
depends on the loop current, VEE, RRF, and is a valid parameter only on long lines where the current limit is not in effect.
On short lines, the feed resistance is high since the loop current is clamped at a near constant level. The AC impedance
(Return Loss) however, is not determined nor affected by the
DC parameters. See the Applications Section for Return
Loss information.
[
• 31 k • 0.328
+ RTX2
RTX1 • (RC ) 31 k)
+
–
11 TXO
AV = 0.328
VQB
MC33121
RTX1
VTX
CTX
RTX2
NOTE: Op amp may be part
of a codec/filter.
Figure 28. Transmit Path
MOTOROLA
MC33121
13
Logic Interface (Hook status, pulse dialing, faults)
current source pullup, and a 1.0 mA current source for a pulldown. Current limiting this output controls the discharge from
the external capacitor when ST2 switches low.
The condition where both ST1 and ST2 are high is not
valid, but may occur momentarily during an off–hook to on–
hook transition. The condition where both ST1 and ST2 are
low may occur momentarily during an on–hook to off–hook
transition — this should not be interpreted as a fault condition. ST1 and ST2 are TTL/CMOS compatible and are
powered by the + 5.0 V supply (VDD). Refer to the Applications Section for more details.
The logic interface section provides hookswitch status,
fault information, and pulse dialing information to the 4–wire
side of the system at the ST1 and ST2 outputs. Figure 30 is
a representative diagram.
The logic outputs operate according to the truth table in
Table 1:
Table 1. Status Output Truth Table
Hook
Status
Fault
Detection
On–Hook
Off–Hook
On–Hook
Off–Hook
Outputs
ST1
ST2
Ci
Circuit
i Condition
C di i
Hi
Lo
Lo
Lo
Lo
Hi
Lo
Lo
Internally powered down
Powered up
Internally powered down
Internally powered down
No Fault
No Fault
Fault
Fault
Power Supplies, Grounds
The MC33121 requires 2 power supplies: battery voltage
between – 21.6 V and – 42 V (VEE), and an auxiliary voltage
between + 4.5 V and + 5.5 V (VDD).
VEE is nominally – 24 V, with a typical range of – 21.6 V to
– 42 V, and must be referenced to VCC (battery ground). A
0.1 µF bypass capacitor should be provided between VCC
Referring to Figure 30, ST1 is configured as an active NPN
pulldown with a 15 kΩ pullup resistor. ST2 has a 800 µA
VCC 20
30
IT
3060
EP 19
IA
MIRROR
+
–
BP 18
TIP
VDD
IA
VL
RL
9 VAG
+
–
RP
RP
10 RXI
RING
+
–
BN 3
VRX
RRX
IRXI
VQB
EN 2
IT
VQB 6
IA = IRXI
30
3060
MC33121
TO VEE
Figure 29. Receive Path
VDD
+ 5.0 V
15
800 µA
TO LOOP
CURRENT
DRIVERS
HOOK
SWITCH
12 ST2/PDI
BIAS
CIRCUIT
1.0 mA CT
TIP
RL
RING
RC
CP
RC
CN
RS
TSI
RS
RSI
HOOK STATUS
DETECTION
FAULT
DETECTION
OFF–HOOK
ON–HOOK
STATUS 2
50 k
50 k
FAULT
5.0 µF
EXTERNAL
POWER DOWN
CONTROL INPUT
VDD
15 k
13 ST1
STATUS 1
14 VDG
MC33121
Figure 30. Logic Interface
MC33121
14
MOTOROLA
and VEE. The VEE current (IEE) is nominally 1.0 mA when
on–hook, 8.0 to 12 mA more than the loop current when off–
hook, and
5.0 mA when off–hook but powered down by
using the PDI pin. Ripple and noise rejection from VEE is a
minimum of 40 dB (with a 10 µF capacitor at VQB), and is
dependent on the size and quality of the V QB capacitor
(CQB) since VQB is the actual internal supply voltage for the
speech amplifiers. The absolute maximum for VEE is – 60 V,
and should not be exceeded by the combination of the battery voltage, its tolerance, and its ripple.
VDD is normally supplied from the line card’s digital + 5.0 V
supply, and is referenced to VDG (digital ground). A 0.1 µF
capacitor should be provided between VDD and VDG. The
VDD current (IDD) is nominally 1.7 mA when on–hook and
between 6.0 and 8.0 mA when off–hook (see Figure 10).
When the MC33121 is intentionally powered down using the
PDI pin, IDD changes by < 1.0 mA from the normal off–hook
value.
[
VAG is the analog ground for the MC33121, and is the reference for the speech signals (RXI and TXO). Current flow is
into the pin, and is typically < 0.5 µA.
Normally, VCC, VDG and VAG are to be at the same DC
level. However, if strong transients are expected at Tip and
Ring, as in a Central Office application, or any application
where the phone line is outdoors, VCC should not be connected directly to VDG and VAG in order to prevent possible
damage to the + 5.0 V system. The MC33121 is designed to
tolerate as much as ± 30 V between VCC and the other two
grounds on a transient basis only. This feature permits VCC
and the other grounds to be kept separate (on an AC basis)
on the line card by transient suppressors, or to be connected
together farther into the system (at the power supplies). See
the Applications Section on ground arrangements and transient protection for further information on connecting the
MC33121 to the system supplies.
APPLICATIONS INFORMATION
This section contains information on the following topics:
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation Calculations
and Considerations . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting the Transistors . . . . . . . . . . . . . . . . . . . . . .
Longitudinal Current Capability . . . . . . . . . . . . . . . .
PC Board Layout Considerations . . . . . . . . . . . . . . .
Alternate Circuit Configurations . . . . . . . . . . . . . . . .
pg. 15
pg. 22
pg. 23
pg. 23
pg. 23
pg. 26
Design Procedure
This section describes the step–by–step sequence for designing in the MC33121 SLIC into a typical line card application for either a PBX or Central Office. The sequence is
important so that each new component value which is calculated does not affect components previously determined.
Figure 4 (Typical Application Circuit) is the reference circuit
for most of this discussion. The recommended sequence
(detailed below), consists of establishing the DC aspects
first, and then the AC aspects:
1) Determine the maximum loop current for the shortest line,
select RRF. Power dissipation must be considered here.
2) Select the main protection resistors (RP), and diodes,
based on the expected transient voltages. Transient
protection configuration must also be considered here.
3) Select RC based on the expected transient voltages.
4) Select RS based on the desired longitudinal impedance at
Tip and Ring. Transient voltages are also a factor here.
5) Calculate RRO based on the desired AC terminating impedance (return loss).
6) Calculate RRX based on the desired receive gain.
7) Calculate RTX2 and RTX1 based on the desired transmit
gain.
8) Calculate the balance resistor (RB), or network, as appropriate for desired transhybrid rejection.
9) Logic Interface
Preliminary
There is a primary AC feedback loop which has its main
sense points at CP and CN (see Figure 34). The loop extends from there to TXO, through RRO to RXI, through the
internal amplifiers to the transistor drivers, through RP to Tip
MOTOROLA
and Ring, and through the RCs to CP and CN. Components
within this loop, such as RP, RC, the transistors, and the
compensation capacitors need not be tightly matched to
each other in order to maintain good longitudinal balance.
The tolerance requirements on these components, and
others, are described in subsequent sections. Any components, however, which are placed outside the loop for additional line card functions, such as test relay contacts, fuses,
resistors in series with Tip and Ring, etc. will affect longitudinal balance, signal balance, and gains if their values and
mismatch is not carefully considered. The MC33121 cannot
compensate for mismatch among components outside the
loop.
The compensation capacitors (0.01 µF) shown at the transistor collectors (Figure 4) compensate the transistor driver
amplifiers, providing the required loop stability. The required
tolerance on these capacitors can be determined from the
following guidelines:
• A 10% mismatch (± 5% tolerance) will degrade the longitudinal balance by 1.0 dB on a 60 dB device, and by
3.0 dB on a 70 dB device.
• A 20% mismatch (± 10% tolerance) will degrade the longitudinal balance by 3.0 dB on a 60 dB device, and by
6.0 dB on a 70 dB device.
[
[
[
[
High quality ceramic capacitors are recommended since
they serve the secondary function of providing a bleedoff
path for RF signals picked up on the phone line. These
capacitors should be connected to a good quality RF ground.
The capacitors used at CQB and CF must be low leakage
to obtain proper performance. Leakage at the CQB capacitor
will affect the DC loop current characteristics, while leakage
at the CF capacitor will affect the AC gain parameters, and
possibly render the IC inoperative.
1) Maximum Loop Current and Battery Feed Resistance
The maximum loop current (at RL = 0) is determined by the
RRF resistor between RFO and RXI. The current limit is accomplished by three internal series diodes (see Figure 27)
which clamp the voltage across RRF as the loop resistance
decreases, thereby limiting the current at RXI. Since the loop
current is 102 x IRXI, the loop current is therefore clamped.
The graphs of Figures 5 to 7 indicate the maximum loop
MC33121
15
current at an ambient temperature of + 25°C, and after the IC
has reached thermal equilibrium (approx. 10 minutes).
Although the maximum loop current is primarily a function
of the RRF resistor, it is also affected by ambient temperature, and slightly by VEE. The ambient temperature effects
are due to the temperature dependence of the diodes’ forward voltage drop, causing the maximum loop current to
change by – 0.3%/°C. Changing VEE affects the maximum
current in that the power dissipation is changed, thereby
changing the die temperature, which affects the diodes’ voltage.
The maximum loop current is affected slightly (< 5%) by
the choice of the RS and RC resistors, since the sense currents through those resistors add to the current supplied by
the transistors.
The battery feed resistance is determined by RRF, and is
not adjustable independently of the current limit. Defined as
∆VTIP/∆IL, it is 400 Ω, and is a valid parameter only on long
lines where the current limit is not in effect. On short lines, the
feed resistance is high since the loop current is clamped at a
near constant level. The AC impedance (Return Loss) however, is not determined nor affected by these DC parameters.
Return loss is discussed in another section.
If the application requires that the current limit value have
a low temperature dependence, refer to the section following
this design sequence which describes an alternate configuration.
[
[
2) Main Protection Resistors (RP) and Transient
Currents
The purpose of the protection resistors (RP), along with
the 4 clamp diodes shown in Figure 4, is to absorb the bulk of
the transient energy when transient voltages come in from
the phone line. The resistor value must be selected to limit
the transient current to a value which can be tolerated by the
diodes, while dissipating the energy. The recommended
value shown (100 Ω) will limit the current from a 1500 V transient to 15 A, which can be carried by 1N4002 diodes under
surge conditions. The resistors must be of a type which can
tolerate the high instantaneous energy associated with transients. Resistor manufacturers should be consulted for this
information.
Referring to Figure 4, a positive transient on either Tip or
Ring, or both, will cause the transient current to be delivered
to Ground. A negative transient will cause the transient current to come from the VEE supply line. Therefore, the PC
board track supplying VCC and VEE to the MC33121 must
be designed to carry the transient currents as well as the normal operating currents. Additionally, since a negative transient will cause a current flow out of the power supply’s
negative output, which is opposite to the normal flow of current, provisions must be made for this reverse current flow.
One suggested method is to place a zener transient suppressor (1N6287 for – 42 V, 1N6282 for – 28 V and – 24 V) across
the battery supply pins (VCC to VEE) physically adjacent to
the MC33121. The inductance associated with PC board
tracks and wiring will result in insufficient protection for the
MC33121 if the suppressor is located at the opposite end of
the line card, or at the power supplies.
Transient currents can be reduced by increasing the value
of RP, with an upper limit determined by the DC conditions on
the longest line (highest loop resistance) and minimum VEE
supply voltage. These conditions determine the minimum DC
MC33121
16
voltage across the transistors, which must be sufficient to
handle the largest AC (transmit and receive) signals. If too
large a value is selected for RP, the AC signals will be
clipped. It is recommended that each transistor have no less
than one volt (DC) across their collector to emitter. System
AC specifications may require more than this.
Since the RP resistors are within the loop, their tolerance
can be ± 5% with no substantial degradation of longitudinal
balance. A ± 10% tolerance (20% mismatch) will degrade
balance by 4.0 dB on a 65 dB device.
[
Figure 31.
TIP
1.0 k
CP
VCC
31 k
AC
VEE
RC
VDD
+
–
RING
1.0 k
RC
CN
VQB
31 k
VCC
VEE
TXO
AV =
0.328
AC
MC33121
Figure 32. RC Protection Resistors
3) Selecting the RC Resistors
The primary purpose of the RC resistors is to protect the
CP and CN pins from transient voltages and destructive currents. Internally, these pins have clamp diodes to VCC and
VEE rated for a maximum of 1.0 A under surge conditions
only (Figure 32). The 1.0 kΩ resistors shown in the figures,
for example, will provide protection against surges up to
1.0 kV. Resistor manufacturers must be consulted for the
proper type of resistor for this environment.
The RC resistors are in series with internal 31 kΩ resistors,
and therefore form a voltage divider to the inputs of the transmit amplifier, as shown in Figure 32. This will affect the transmit gain, receive gain, return loss, and transhybrid rejection
(described in subsequent sections). The tolerance of the RC
resistors depends on the value selected for them, since any
mismatch between them will create a differential voltage at
CP and CN when longitudinal voltages are present on Tip
and Ring. To ensure a minimum of 58 dB of longitudinal balance, the resistors’ absolute value must not differ by more
than 39 Ω . With a nominal value of 1.0 kΩ, their tolerance
must be ± 2%, or less. If their nominal value is 390 Ω or less,
their tolerance can be ± 5%.
4) Longitudinal Impedance (ZLong) — Selecting the
RS Resistors
The longitudinal impedance is determined by the RS resistors at the TSI and RSI pins according to the following
equation:
R
100
S
(4)
Z
Long
51
ZLong is defined as VLong/ILong as shown in Figure 33;
for R S = 9.1 kΩ , Z Long = 180 Ω . The calculated value
of ZLong includes the fact that the RS resistors are in parallel
with the synthesized impedance. The tolerance of the RS
resistors therefore depends on how much mismatch can be
tolerated between the longitudinal impedances at Tip and at
Ring. Calculations indicate the two RS resistors can have a
± 5% tolerance, and still comfortably provide a minimum of
58 dB longitudinal balance.
+ )
MOTOROLA
The resistors must be able to withstand transient voltages
expected at Tip and Ring. The TSI and RSI pins have internal
clamp diodes rated for a maximum of 1.0 A under surge
conditions only (Figure 33). Resistor manufacturers must be
consulted for the proper type of resistor for this environment.
ance. The reference impedance can be, in some cases, a
pure resistance (commonly 600 Ω or 900 Ω), a series resistor
and capacitor (900 Ω + 2.16 µF), or a more complex network.
To achieve proper return loss with the MC33121, the RRO
impedance shown in Figure 34 is to have the same configuration as the reference impedance, but with values scaled
according to the equations mentioned below.
CRO, used primarily for DC blocking, is generally a large
value (1.0 µF) so as to not affect the impedance of RRO.
However, it can be included in the RRO network if a complex
network is required.
5) AC Terminating Impedance and Source Impedance
(Zac) — Return Loss
The return loss measurement is a measure of how closely
the AC impedance of the SLIC circuit matches the characteristic impedance of the phone line, or a reference imped-
VCC
EP
BP
ZLONG
TIP
RING
ILONG
TSI
RS
AC
VQB
VEE
14 V
EN
VEE
– 24 V
COMMON MODE
DETECTOR
& AMPLIFIER
100
BN
ZLONG
VLONG
100
RSI
RS
ILONG
BUFFER
VCC
7.0 V
BUFFER
MC33121
Figure 33. Longitudinal Impedance
VCC
30
IT
ZT
2
TIP
RS 9.1 k
IL
VL
RC 1.0 k
RS 9.1 k RC 1.0 k
AC
RSI
+
–
AC
31 k
+
–
VAG
IRXI
RXI
AV =
0.328
RRO
AC
TXO
+
–
BN
ZT
2
IA
31 k
CP
CN
RP
100
MIRROR
TSI
ZAC
RING
IA
–
+
BP
RP
100
3060
EP
CRO
EN
IT
VQB
30
3060
TO VEE
MC33121
IA = IRXI
Figure 34. AC Terminating Impedance
MOTOROLA
MC33121
17
Zac is the impedance looking into the circuit from Tip and
Ring (set by RRO), and is defined as VL/IL. Half of Zac is
from Tip to VCC, and the other half is from Ring to VQB (an
AC ground). Each half is made up of a synthesized impedance (ZT/2) in parallel with RS and (RC + 31 k). Therefore,
Zac is equal to:
Zac = [ZT/2//RS//(RC + 31 k)] • 2
(5)
and
Z
T
2
{R ńń(RC ) 31 k)} • (Z acń2)
S
+ {R
ńń(RC ) 31 k)} – (Zacń2)
S
(9)
S
Zac is computed at a nominal frequency of interest. A first
order approximation of Equation 9 is:
SF = 1.037 • 106/(RC + 31 k)
(9a)
For example:
IF THE AC LOAD IS:
• 31 k • 0.328
+ VL (RC
TXO
) 31 k)
THEN RRO SHOULD BE:
TO
RXI
2.16 µF
TO TIP
AND RING
900
• 1.037 • 10 6
+ ZT(31 k ) RC)
IF THE AC LOAD IS:
a) Resistive Loads (with RC = 1.0 k, RS = 9.1 k):
For a 600 Ω resistive system, ZT calculates to 626 Ω , and
RRO calculates to 20.3 kΩ .
For a 900 Ω resistive system, ZT calculates to 961 Ω , and
RRO calculates to 31.14 kΩ .
b) Complex Loads
For complex (nonresistive) loads, the MC33121 must be
made to look like a termination impedance equal to that complex load. This is accomplished by configuring RRO the
same as the complex load, but with all impedance values
increased according to the scaling factor of Equation 9.
62 nF (CRO)
820
THEN RRO SHOULD BE:
TO
RXI
0.115 µF
220
TO TIP
AND RING
FROM
TXO
(8)
While equation 8 gives the exact value for RRO, a first order
approximation is Zac • 33.5.
31.15 k (RRO)
FROM
TXO
(7)
The signal at TXO creates an AC current IRXI through
RRO. RXI is a virtual ground, and CRO is insignificant for first
order calculations.
IRXI is gained up by a factor of 102 to produce the current
IT through the transistors.
ZT is therefore VL/IT. The relationship between ZT and
RRO is:
RRO
) 31 k)ńńRS] • 1.037 • 106
+ (RC )[(RC
31 k) • [(RC ) 31 k)ńńR – (Z acń2)]
(6)
The synthesized impedance ZT is created as follows:
An incoming signal VL produces a differential voltage at
CP and CN, and therefore at TXO equal to:
V
SF
3.3 nF
CRO
28.4 k
7.61 k
CRO must remain in series with the network to provide DC
blocking. If the load network does not include a series capacitor (as in the second example above), CRO should be large
(1.0 µF) so its impedance does not affect the RRO network.
The above procedure will yield a return loss measurement
which is constant with respect to frequency. The RRO resistor, or network, must have a tolerance equal to or better than
the required system tolerance for return loss and receive
gain.
6) Receive Gain (GRX)
The receive gain involves the same circuit as Figure 34,
but with the addition of the RRX resistor (or network) which
sets the receive gain. See Figure 35.
EP
VAG
BP
RP
100
TIP
IL
VL
RC 1.0 k
CP
RS 9.1 k
TSI
RAC
RING
MC33121
RP
100
RS 9.1 k
RSI
RC 1.0 k
CN
RRX
IRXI
VRX
RXI
IR
RRO
BN
TXO
CRO
ITXO
EN
Figure 35. Receive Gain
MC33121
18
MOTOROLA
The receive gain (GRX), defined as the voltage gain from
VRX to VL, is calculated as follows:
RXI is a virtual ground, and Rac is the AC impedance of
the load (phone line).
The AC current generated in the transistors is 102 • IRXI,
which is equal to 102 • (IR – ITXO).
IR = VRX/RRX, and
I
TXO
TXO + V L • 31 k • 0.328
+ VRRO
RRO • (31 k ) RC)
(10)
The preceding procedure will yield a receive gain which is
constant with respect to frequency. The RRX resistor, or network, must have a tolerance equal to or better than the required system tolerance for receive gain.
7) Transmit Gain (GTX)
Setting the transmit gain involves selecting RTX1 and RTX2
in Figure 28. The voltage gain from VL to VTX is calculated
from the following:
G
Using equations 5 and 8, involving Zac, RS and RC, and
the above equations yields:
acńńZ ac)
+ GRX + 102 • (R
RRX
RX
102 • (R acńńZ ac)
RRX +
V
V
Therefore,
L
G
(11)
(12)
RX
Equation 12 applies only for the case where Rac and Zac
have the same configuration. If they also have the same
magnitude, then set RRX = 51 • Rac to set a receive gain of
0 dB. The AC source impedance of the above circuit to Tip
and Ring is Zac. For the case where Rac ≠ Zac, use the following equation:
V
V
L
RX
+
where Z
ƪ
RRX •
L
+
ƪ
R ac
2
102
1
Z
L
)
1.037 • 10 6
(31 k RC) • RRO
)
ńń RS ńń (RC ) 31 k)
ƫ
ƫ
• 2
(13)
(14)
a) Resistive Loads
For a 600 Ω resistive system, set RRX = 30.6 kΩ , and for
a 900 Ω resistive system, set RRX = 45.9 kΩ .
b) Complex Loads
For complex (nonresistive) loads, the RRX resistor needs
to be replaced with a network having the same configuration
as the complex load, but with all impedance values scaled up
by a factor of 51 (for 0 dB gain). If a gain other than 0 dB is
desired, the scaling factor is determined from Equation 12.
This method applies only if the RRO network has been
made complex comparable to the load according to the procedure in the previous section (Equations 5 – 9a), such that
Rac = Zac. Using a scaling factor of 51, and the previous examples, yields:
IF THE AC LOAD IS:
2.16 µF
900
TO TIP
AND RING
THEN RRX SHOULD BE:
TO
RXI
VRX
45.9 k
V
TX + RTX2 • 31 k • 0.328
+
TX
V
RTX1 • (RC ) 31 k)
(15)
L
For 0 dB gain, set RTX2 = 3.15 x RTX1 (for RC = 1.0 k). The
actual values of RTX2 and RTX1 are not critical — only their
ratio so as to provide the proper gain at the op amp. Once the
ratio is established, the two resistors can be selected from a
set of standard resistor values. The minimum value for RTX1
is limited by the drive capability of TXO, which is a nominal
± 800 µA peak (± 275 µA minimum). As a general rule, RTX1
should be between 5.0 kΩ and 20 kΩ . The load on TXO is
the parallel combination of RTX1 and RRO.
CTX is for DC blocking, and is typically a large value
(1.0 µF) so as to not be a significant impedance. In general,
it should not be used for low frequency rolloff as that will affect the transhybrid rejection (discussed in the next section).
Low frequency rolloff should be done after the op amp. High
frequency roll–off can be set by placing a capacitor across
RTX2.
For complex loads (at Tip and Ring), if RRO and RRX have
been made complex comparable to the load as described in
the previous sections, neither RTX1 nor RTX2 needs to be
complex since both the transmit and receive signals which
appear at TXO will be flat with respect to frequency.
RTX1 and RTX2 must have a tolerance equal to or better
than the required system tolerance for the transmit gain.
8) Balance Network (RB) — Transhybrid Rejection
When a receive signal is applied to VRX to produce a signal at Tip and Ring, the two–to–four wire arrangement of a
hybrid (the MC33121) results in a reflected signal at TXO.
Transhybrid rejection involves canceling that reflected signal
before it appears at VTX. The method used is to insert the RB
resistor (or network) as shown in Figure 36. The current IB,
supplied from VRX, cancels the current ITX1 supplied from
TXO (Node A is a virtual ground). Good transhybrid cancellation requires that the currents be equal in magnitude and
180° out of phase at Node A.
Using the equations for transmit and receive gains, the
current ITX1 is equal to:
42 nF
I
33.5 • V
• Z ac • Z • 31 k
RX
L
+
TX1
RRX • [Z ac ) Z ] • RTX1 • (RC ) 31 k)
(16)
L
IF THE AC LOAD IS:
2.25 nF
820
220
a) For the case where RRO and RRX are comparable in
configuration to Z:
Since IB = VRX/RB, then RB can be determined from:
THEN RRX SHOULD BE:
0.115
µF
TO TIP
TO
AND RING RXI
11.2 k 41.8 k
VRX
RB
• RTX1 • (RC ) 31 k)
+ RRX
33.5 • [Z acńńZ ] • 31 k
(17)
L
MOTOROLA
MC33121
19
TIP
IRX
RXI
VL
ZL
VRX
RRX
–102 IRX
IB
Zac
+
–
RING
TXO
ITX1
VL x 0.328
MC33121
RTX2
RB
RTX1
–
+
A
VTX
Figure 36. Balance Resistor
Equation 17 provides a value for an RB resistor which will
provide the correct magnitude for IB. The correct phase relationship is provided by the fact that the signal at TXO is out of
phase with that at VRX. The phase relationship will be 180°
only if RRO and RRX are of a configuration identical to that
of the load. This applies regardless of whether the load, ZL,
(and RRO and RRX) are purely resistive or of a complex
nature. Equation 17 reduces to a non–complex resistance if
RRX, Zac, and ZL are all comparably complex.
For the case where Zac = ZL, RRX = 51 • Zac, and RC =
1.0 k, Equation 17 reduces to:
RB = 3.15 • RTX1
explanation, the current source and Zac of Figure 36 are
replaced with the Thevenin voltage source and series Zac.
Since ZL and Zac are not matched, there will be a phase shift
from VRX to the signal across Tip and Ring. This phase shift
is also present at TXO. The same phase shift is generated at
node B in the RB network by making RB1 equal to Zac, and
ZL equal to the load. RB2 is then calculated from:
RRX • RTX1 • (RC 31 k)
(19)
RB2
33.5 • Z ac • 31 k
For example, for a system where the load is considered a
600 Ω resistor (RRO = 20.3 kΩ , RRX = 30.6 kΩ , RTX1 =
10 kΩ , and RC = 1.0 kΩ), RB1 would be a 600 Ω resistor, ZL
(in the RB network) would be a 600 Ω resistor in parallel with
a 0.005 µF capacitor, and RB2 calculates to 15.715 kΩ .
The RB resistor, or network, must have a tolerance equal
to or better than the required system tolerance for transhybrid rejection.
(18)
b) For the case where Zac and ZL do not have the same
frequency characteristics:
For the case where, for reasons of cost and/or simplicity,
the load (RL) is considered resistive (whereas in reality it is
not a pure resistance) and therefore resistors, rather than
networks, were selected for RRO and RRX, using a simple
resistor for RB may not provide sufficient transhybrid rejection due to a phase angle difference between VRX and TXO.
The terminating impedance may therefore not necessarily be
matched exactly to the line impedance, but the resulting circuit still provides sufficiently correct performance for receive
gain, transmit gain, and return loss. The rejection can be improved in this case by replacing RB with the configuration
shown in Figure 37. Even on a very short phone line there is
a reactive component to the load due to the two compensation capacitors (CC, Figure 4) at the transistor collectors. The
two capacitors can be considered in series with each other,
and across the load as shown in Figure 37. To simplify the
TIP
0.005 µF
Rac
9) Logic Interface
The logic circuit (output ST1, and the I/O labeled ST2/PDI)
is depicted in Figure 30, and functions according to the
Status Output Truth Table (Table 1).
a) Output Characteristics
ST1 is a traditional NPN pull–down with a 15 kΩ pull–up
resistor. Figures 19 and 20 indicate its output characteristics.
ST2 is configured with the following items: a) a 1.0 mA current source for a pull–down which is active only when ST2 is
internally set low; b) an 800 µA current source pull–up which
is active only when ST2 is internally set high; c) a positive
RXI
Zac
VL
VRX
RRX
VS
+
–
TXO
RTX1
ITX1
ZL
RING
)
+
RB1
B
ZL
IB
RB
RB2
MC33121
RTX2
A
–
+
VTX
Figure 37. Balance Network
MC33121
20
MOTOROLA
feedback aspect within this output circuit which provides considerable hysteresis for stability reasons. Its output characteristics are shown in Figures 21 and 22. Due to this
configuration, any external pull–up resistance which is applied to this pin must be greater than 15 kΩ , or the output
may not reliably switch from high to low. Any external pull–
down resistance does not affect this output’s ability to switch
from low–to–high, but does affect the maximum longitudinal
currents which can be accepted by the circuit (see the section on Longitudinal Current Capability). The capacitor (CT)
is required to provide a time delay, for stability reasons, during transitions between off–hook and on–hook. This capacitor additionally affects maximum longitudinal currents, as
well as stability during pulse dialing (explained below).
b) Hook Status
The MC33121 uses the sense currents at CP and CN to
activate the hook status circuit. The sensing is configured
such that the circuit monitors the impedance across Tip/Ring,
which results in the hookswitch thresholds are minimally
affected by the battery voltage. The off–hook to on–hook
threshold is affected by the choice of RRF according to the
graph of Figure 8, but is not affected by the value of RS. The
on–hook to off–hook threshold is affected by the value of RS
according to the graph of Figure 9, but is not affected by RRF.
Varying the RC resistors does not affect the thresholds significantly.
When the telephone is on–hook (ST1 = High, ST2 = Low),
the MC33121 is internally powered down, the external transistors are shut off, and power consumption is at a minimum.
Upon closure of the phone’s hookswitch, ST1 will switch low
within 10 µs. ST2 will then change state slowly due to the external capacitor (CT = 5.0 µF). There is a 8.0 ms delay for
ST2 to reach the threshold necessary to activate the internal
bias circuit, which in turn activates the external drive transistors to supply loop current. This delay is necessary to prevent instabilities during the transition to off–hook.
Upon opening the telephone’s hookswitch, ST1 will switch
high within 200 µs. ST2 then requires 60 ms to reach
the threshold to switch off the internal bias circuit, which in
turn shuts down the external drive transistors.
[
[
[
ON–HOOK
d) Fault Detection
Faults are defined as excessive leakage from Tip to VEE
and/or ground, and from Ring to VEE and/or ground. A single
fault is any one of the above conditions, while a double fault
is defined as excessive leakage from Tip to VEE and from
Ring to VCC, as depicted in Figure 38. Refer to Figures 11 –
15 for the resistance, RLK, which will cause the MC33121 to
switch to a power–down condition. If the leakage resistance
is less than that indicated in the graphs, the MC33121 will
power–down itself and the two external transistors, thereby
protecting them from overheating. Both status outputs (ST1
and ST2) will be at a logic low, indicating a fault condition. A
fault condition is detected by monitoring an imbalance in the
magnitudes of the currents at TSI and RSI, and/or a polarity
reversal at Tip and Ring.
The MC33121 will detect the following conditions:
1) When on–hook (see Figure 11):
a) < 2.6 kΩ between Ring and VCC (depending on RS
and VEE), with no hysteresis at this threshold, or
b) < 3.7 kΩ between Tip and VEE (depending on RS
and VEE), with no hysteresis at this threshold, or
c) Both a and b simultaneously.
Leakage from Tip to VCC and/or Ring to VEE are not
detected as faults while the MC33121 is on–hook.
2) When off–hook (367 Ω between Tip and Ring):
a) < 400 Ω between Tip and VCC (RS = 6.2 kΩ), or
b) < 1800 Ω between Tip and VEE, or
c) < 400 Ω between Ring and VEE (RS = 6.2 kΩ), or
d) < 1800 Ω between Ring and VCC, or
e) Both b and d simultaneously
OFF–HOOK
OFF–HOOK
VCC
VCC
MC33121
VCC
MC33121
RLK
MC33121
RLK
ST2
VEE
TIP
ST1
ST2
RLK
RING
VEE
VEE
ST1
=0
RL
OR
AND/OR
=0
RING
RLK
TIP
ST1
AND/OR
TIP
RLK
c) Pulse Dialing
During pulse dialing, ST1 will change state concurrent with
the hookswitch. ST2 is kept from switching during pulse dialing by the external capacitor (CT), which keeps the MC33121
in a powered up condition and stable. If the CT capacitor is
too small, the voltage at ST2 could drop to the PDI threshold
(see section e below) during each pulse. This could cause
the MC33121 to create additional noise on the line as it
would cycle between a power–up and power–down condition
with each dialing pulse.
=0
RL
ST2
RLK
RING
VEE
VEE
VEE
Figure 38. Fault Detection
MOTOROLA
MC33121
21
A simultaneous occurrence of conditions a) and c) is not
detected as a fault. See Figures 12 to 15 for the threshold
variation with RL and VEE. Resetting of the fault detection circuit requires that the leakage resistance be increased to a
value between 10 kΩ and 20 kΩ , depending on VEE, RL, and
RS. Both ST1 and ST2 should be monitored for hookswitch
status to preclude not detecting a fault condition.
Figure 15 indicates the variation in fault thresholds for Tip–
to–VCC and Ring–to–Battery faults, and is valid only for loop
resistances of 200 Ω to 800 Ω . On loops larger than 800 Ω ,
the MC33121 does not reliably indicate the fault condition at
ST1 and ST2, but may indicate on–hook status instead. This
does not apply to Tip–to–Battery and Ring–to–VCC faults
which are correctly detected for lines beyond 800 Ω .
e) PDI Input
The ST2 output can also be used as an input (PDI Input) to
power down the circuit, denying loop current to the subscriber (by shutting off the external pass transistors), regardless
of the hookswitch position. Powering down is accomplished
by pulling PDI to a logic low with an open collector output, or
an NPN transistor as shown in Figure 30. The switching
threshold is 1.5 V. The current out of PDI, when pulled low,
is 800 µA. Releasing PDI allows the MC33121 to resume
normal operation.
If the external telephone is off–hook while the MC33121 is
powered down, sense currents at CP and TSI will result in
some loop current flowing through the loop and back into CN
and RSI. This current is generally on the order of 1.0 to
3.0 mA, determined primarily by the RS resistors, loop resistance, and VEE. ST1 will continue to indicate the telephone’s
actual hook status while PDI is held low. The on–to–off hook
threshold is the same as that during normal operation, but
the off–to–on hook threshold is > 250 kΩ .
When powered down with the PDI pin, the receive gain
(VRXI to Tip/Ring) is muted by > 90 dB, and the transmit gain
(Tip/Ring to TXO) is muted by > 30 dB.
[
[
Power Dissipation, Calculation and Considerations
a) Reliability
The maximum power dissipated by the MC33121 must be
considered, and managed, so as to not exceed the junction
temperature listed in the Maximum Ratings Table. Exceeding
this temperature on a recurring basis will reduce long term
reliability, and possibly degrade performance. The junction
temperature also affects the statistical lifetime of the device,
due to long term thermal effects within the package. Today’s
plastic integrated circuit packages are as reliable as ceramic
packages under most environmental conditions. However,
when the ultimate in system reliability is required, thermal
managements must be considered as a prime system design
goal.
Modern plastic package assembly technology utilizes gold
wire bonded to aluminum bonding pads throughout the electronics industry. When exposed to high temperatures for protracted periods of time an intermetallic compound can form in
the bond area resulting in high impedance contacts and
degradation of device performance. Since the formation of
intermetallic compounds is directly related to device junction
temperature, it is incumbent on the designer to determine
that the device junction temperature is consistent with system reliability goals.
MC33121
22
Based on the results of almost ten years of + 125°C operating life testing, Table 2 has been derived indicating the relationship between junction temperature and time to 0.1% wire
bond failure.
Table 2. Statistical Lifetime
Junction
Temperature (°C)
Time
(Hours)
Time
(Years)
80
90
100
110
120
130
140
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
4.2
2.0
1.0
Motorola MECL Device Data, DL122
The “Time” in Table 2 refers to the time the device is operating at that junction temperature. Since the MC33121 is at a
low power condition (nominally 40 mW) when on–hook, the
duty cycle must be considered. For example, if a statistical
duty cycle of 20% off–hook time is used, operation at 130°C
junction temperature (when off–hook) would result in a statistical lifetime of 10 years.
[
b) Power and Junction Temperature Calculation
The power within the IC is calculated by subtracting the
power dissipated in the two–wire side (the transistors and the
load) from the power delivered to the IC by the power supplies. Refer to Figure 4 and 27.
PD = |VDD • IDD| + |VEE • IEE| – (IL • |VEP – VEN|)
(20)
The terms VEP and VEN are the DC voltages, with respect
to ground, at the EP and EN pins. These voltages can be
measured, or can be approximated by:
VEN
VEP [ – (30 Ω • IL)
[ |VEE| + 2.1 V + (IL • 35 Ω)
Refer to Figure 23. The junction temperature is then calculated from:
TJ = TA + (PD • θJA)
(21)
where TA is the ambient air temperature at the IC package,
and θ JA is the junction–to–ambient thermal resistance
shown in Figure 39. The highest junction temperature will
occur at maximum VEE and VDD, maximum loop current,
and maximum ambient temperature.
If the above calculations indicate the junction temperature
will exceed the maximum specified, then it is necessary to
reduce the maximum loop current, ambient temperature,
and/or VEE supply voltage. Air flow should not be restricted
near the IC by tall components or other objects since even a
small amount of air flow can substantially reduce junction
temperature. For example, typically an air flow of 300 LFPM
(3.5 mph) can reduce the effective θJA by 14 to 20% from
that which occurs in still air. Additionally, providing as much
copper area as possible at the IC pins will assist in drawing
away heat from within the IC package. For additional information on this subject, refer to the “Thermal Considerations” section of Motorola MECL System Design Handbook,
and the “System Design Considerations” section of Motorola
MECL Device Data.
MOTOROLA
70
MC33121
STILL AIR, SOLDERED
TO A G–10 PC BOARD
θJA, °C/W
60
50
40
30
25
35
45
55
65
75
85
TA, °C
Figure 39. Thermal Resistance
(Junction–to–Ambient)
Selecting the Transistors
The specifications for the two loop current pass transistors
involve their current gain, voltage rating, and power dissipation capabilities at the highest ambient temperatures. Power
dissipation during both normal operation and faults must be
considered when determining worst case situations. Generally, more power is dissipated during a fault condition than
during normal operation.
The transistors’ minimum beta is recommended to be 40 at
the loop currents involved in the application. A lower beta
could degrade gain and balance performance. Maximum
beta should be less than 500 to prevent possible oscillations.
Darlington type transistors should not be used. The voltage
rating should be consistent with the maximum VEE, expected
transients, and the protection scheme used.
Referring to Figure 27, during normal operation the loop
current and the voltage across the transistors are both at a
maximum when the load impedance (RL) is at a minimum.
The loop current is determined by RRF and the graphs of
Figures 5 – 7. The voltage across each transistor is determined from the following:
Ť Ť
)
)
V
– 2.1 – [(65 2RP R ) • I ]
EE
L
L
(22)
T
2
The power in each transistor is then (VT • IL). The voltage
across the two transistors will always be nearly equal during
normal operation, resulting in equal power dissipation. The
graph of Figure 24 indicates the power dissipated in each
transistor where RP = 100 Ω .
During a fault condition, depicted in Figure 38, if the leakage resistance from Tip to VEE or from Ring to VCC is less
than that shown in Figures 12 – 14 (when off–hook), the
MC33121 will power down the transistors to protect them
from overheating. Should the leakage resistance be slightly
higher than that shown in the graphs, however, and the fault
detection has not been activated, the power in one transistor
(in a single fault, both transistors in a double fault) will be
higher than normal. The power will depend on VEE, RL, RP
and the leakage resistance. Table 3 is a guide of the power in
the transistor dissipating the higher power level.
The power (in watts) in the two right columns indicates the
power dissipated by that transistor if it is carrying the maximum fault current. The system designer should attempt to
predict possible fault conditions for the system, and then
V
+
MOTOROLA
measure the conditions on the transistors during the worse
case fault(s).
Table 3. Transistor Power During a Fault
VEE
RL
PPNP
PNPN
– 42
– 24
– 42
– 24
150
150
600
600
0.835
0.257
0.601
0.109
0.615
0.176
0.185
0.057
For most applications involving a maximum loop current of
30 – 40 mA, and a maximum TA of + 85°C, and where faults
may occur, the MJD243 and MJD253 DPAK transistors are
recommended. When mounted as described in their data
sheet, they will handle both the normal loop current as well
as most fault conditions. If faults are not expected to occur in
a particular application, then smaller package transistors,
such as MPS6717 and MPS6729, may be used. Each application must be evaluated individually when selecting the
transistors.
Other possible transistors which can be considered:
PNP
MJD253–1
MJE253
MJD32
MJD42
MJD350
TIP30A,B,C
NPN
MJD243–1
MJE243
MJD31
MJD41
MJD340
TIP29A,B,C
Longitudinal Current Capability
The maximum longitudinal current which can be handled
without distortion is a function of loop current, battery feed resistance, the longitudinal impedance, and the components
on ST2.
Since the pass transistors cannot pass current in the reverse direction, the DC loop current provides one upper
boundary for the peak longitudinal current plus peak speech
signal current. The battery feed resistance determines, in effect, the DC voltage across the transistors, which is a measure of the headroom available for the circuit to handle the
peak longitudinal voltage plus peak speech signal voltage.
The longitudinal impedance, determined by the RS resistors
(equation 4), determines the longitudinal current for a given
longitudinal voltage.
While analysis of the above items may yield one value of
maximum longitudinal current, a different limit (which may
be higher or lower) is imposed by the capacitor CT, and any
pulldown resistance RT, on Pin 12 (ST2). This is due to the
fact that the sense currents at TSI and RSI will be alternately
mismatched as Tip and Ring move up and down together in
the presence of longitudinal signals. When the longitudinals
are strong, the internal fault detect circuit is activated with
each 1/2 cycle, which attempts to switch ST2 low (see the
section on Fault Detection). The speed at which ST2 can
switch low is a function of both the external capacitor, CT and
any pulldown resistance, RT.
The graphs of Figures 25 and 26 indicate the maximum
longitudinal current which can be handled (in Tip and in Ring)
without distortion or causing ST2 to switch low.
PC Board Layout Considerations
PC board considerations include thermal, RFI/EMI, transient conditions, interconnection of the four wire side to the
MC33121
23
codec/filter, and others. Wirewrapped boards should be
avoided — breadboarding should be done on a (at least) reasonably neat PC board.
a) Thermal
Power dissipated by the MC33121 and the two transistors
must be removed to prevent excessively high junction temperatures. The equations for calculating junction temperatures are mentioned elsewhere in this data sheet. Heat is
removed by both air flow and copper foil on the PC board.
Since even a small amount of air flow substantially reduces
junction temperatures compared to still air, tall components
or other objects should not be placed such that they block air
flow across the heat generating devices. Increasing, wherever possible, the area of the copper foil at the IC pins will provide additional heat removal capability. A ground plane can
generally help here, while at the same time helping to reduces RFI problems.
b) RFI/EMI
While the MC33121 is intended for use at audio frequencies, the internal amplifiers have bandwidths in excess of
1.0 MHz, and can therefore respond to externally induced
RFI and EMI. Interference signals can come in on the phone
line, or be radiated on to the PC board from nearby radio stations or from high frequency circuitry (digital & microprocessor circuitry) in the vicinity of the line card.
Usually RFI entering from the phone line at Tip and Ring
can be removed by the compensation capacitors (CC) provided they are connected to a good quality RF ground (generally the same ground which connects to V CC on the
MC33121). The ground track should be as wide and as direct
as possible to minimize lead inductance. Generally better
results can be obtained if an RF bleedoff to earth (or chassis)
ground can be provided where the twisted pair phone line
comes into the system.
To minimize problems due to noise radiating directly onto
the PC board from nearby high frequency circuitry, all components associated with the MC33121 should be physically
as close as possible to the IC. The most sensitive pins in this
respect are the CP, CN, RSI, TSI, VAG and RXI pins. Keeping the tracks short minimizes their “antenna” effect.
c) Transient Conditions
When transient voltages come in to Tip and Ring, the transient currents, which can be several amperes, must be carried by the ground line (VCC) an/or the VEE line. These
tracks, along with the protection and clamping devices, must
be designed for these currents at the frequencies involved. If
the tracks are narrow, not only may they be destroyed by the
high currents, but their inductance can allow the voltage at
the IC, and other nearby components, to rise to damaging
levels.
The protection circuits shown in Figure 4, and in other figures in this data sheet, are such that the bulk of the transient
energy is dissipated by external components (the protection
resistors and the clamp diodes). The MC33121 has internal
diodes to limit voltage excursions on the pins, and to pass a
small amount of the transient current — typically less than
1.0 A peak. The arrangement of the diodes is shown in Figure 40.
d) Interconnection of the four–wire side
The connections on the four–wire side to the codec and
other digital circuitry involves keeping digital noise out of the
speech paths, and also ensuring that potentially destructive
transients on Tip and Ring do not get through to the + 5.0 V
system.
VDD
VCC
ST1
MC33121
EP
+ 5.0 V
BP
ST2
CP
VDG
TSI
TO DIGITAL
GROUND
VAG TO ANALOG
GROUND
RSI
RXI
14 V
TXO
CN
RFO
BN
CF
VQB
EN
All zener diodes are 7.0 V,
except where noted.
VEE
14 V
9.0 V
Figure 40. Protection Diodes
MC33121
24
MOTOROLA
Basically, digital connections to ST1 and ST2 should be
referenced to the VDD and VDG pins, while the transmit and
receive analog signals should be referenced to the analog
ground (VAG). VCC should be connected to a clean battery
ground, and generally should not be connected directly to
VDG and/or VAG (on the line card) when strong transients are
anticipated. Even with a good layout, VCC can move several
volts when a transient hits, possibly damaging components
on the + 5.0 V line if their grounds have a direct connection at
the line card. The MC33121 is designed to allow VCC to
move as much as ± 30 V with respect to VDG and VAG on a
transient basis only. VCC and the other grounds should preferably be connected together at the power supply rather
than at the IC. Internally, the MC33121 has clamp diodes on
the 4–wire side pins as indicated in Figure 40.
If the codec has a single ground pin, as in Figure 41, it will
be the reference for both the digital and analog signals, and
must be connected to both VAG and VDG on the MC33121. If
the codec has separate digital and analog grounds, as in Figure 42 (the MC145503 internally generates the analog
ground), then each ground should be connected to the
appropriate ground on the MC33121.
e) Other
A 0.1 µF capacitor should be provided across VCC to VEE
on the MC33121 to help keep idle channel noise to a minimum.
The CQB capacitor (on the VQB pin) forms a pole with an
internal 7.5 kΩ resistor to filter noise from the VEE pin, providing an internal quiet battery supply for the speech amplifiers. Power supply rejection will depend on the value and
quality of this capacitor at the frequencies of concern. Tantalum capacitors generally have better high frequency characteristics then electrolytics. See Figure 17 and 18 for ripple
rejection characteristics (the four–wire data was measured at
pin 11 (TXO)). Figure 16 indicates ripple rejection from the
+ 5.0 V supply (VDD).
In general, pc board tracks carrying analog signals (on the
four–wire side and Tip/Ring) should not be routed through
the digital section where they could pick up digital noise. Any
tracks longer than a few inches should be considered an antenna and should be checked for potential noise or RFI pickup which could affect the circuit operation.
BATTERY GROUND
VCC
VDD
VCC
0.1
5 µF
0.1
VDG
GNDA
VAG
RXI
VFRO
MC33121
VFXI+
VFXI–
GSX
TXO
10 µF
VQB
VBB
DIGITAL GROUND
+ 5.0 V
0.1
– 5.0 V
VEE
–
+
DIGITAL
INTERFACE
+
–
MC145554
BATTERY SUPPLY
0.1
Figure 41. Connection to a CODEC With a Single Ground
BATTERY GROUND
VCC
VDD
VCC
0.1
VDG
VAG
5 µF
VSS
DIGITAL GROUND
+ 5.0 V
0.1
– 5.0 V
0.1
VLS
VAG
MC33121
RXI
+TX
TXO
10 µF
VEE
VQB
–
+
RXO
–TX
+
–
TXI
MC145503
DIGITAL
INTERFACE
BATTERY SUPPLY
0.1
Figure 42. Connection to a CODEC With Separate Grounds
MOTOROLA
MC33121
25
[
Alternate Circuit Configurations
VAG
RXI
RRF1
50
IL, LOOP CURRENT (mA)
a) Loop Current Limit
Replacing the RRF resistor with the circuit in Figure 43 will
change the DC loop current characteristics in two ways from
the graphs of Figures 5 – 7; a) the maximum loop current on
a short line can be reduced while increasing the current on a
long line, and b) the temperature dependence of the maximum current is reduced to the TC of the external reference
diode.
a small amount ( 10%) flows through the sense resistors
and the CP, CN, RSI pins. On a positive transient, all the current is directed to ground. The diode in the NPN’s collector
prevents reverse current through the base–collector junction
of the transistor during a negative transient.
LM385–1.2
RRF2
40
30
20
RS = 9.1 k
VEE = – 24 V
TA = 25°C
RFO
10
Figure 43. Alternate Current Limit Circuit
0
RRF1 = 4.3 kΩ
RRF2 = 820 Ω
200
400
600
800
RL, LOOP RESISTANCE (Ω)
The LM385–1.2 is a precision temperature stable zener
diode. As the load impedance at Tip and Ring is reduced, the
voltage at RFO goes increasingly negative. When the zener
diode is turned on, the current into RXI is then clamped at a
value determined by RRF1 and the zener diode. To calculate
the two resistors, use the following procedure:
RRF1 must be > 0.7 • (RRF1 + RRF2);
Determine RRF1 to set the current limit on a short line by
using the following equation:
RRF1
+I
102 • 1.23 V
– 3.0 mA
L(max)
(23)
(24)
Figure 44 illustrates one example using the above circuit.
Comparing this graph to the 5100 Ω curve of Figure 7 shows
a substantial decrease in the current limit (at RL = 0), resulting in reduced power consumption and dissipation. Use of
this circuit does not affect the hookswitch or fault thresholds.
b) Protection Scheme
The protection circuit shown in Figure 45 has the advantage of drawing 90% of the transient current from ground
(VCC) on a negative transient, rather than from the VEE line
as the circuit of Figure 4 does. The majority of the transient
current flows through the RP resistors and the Mosorbs while
[
MC33121
26
VCC
MC33121
EP
BP
1.5KE15
1.0 kΩ
0.01
100 V
CP
RP
Then using Equation 1 calculate RRF for the long line current. RRF2 is then determined by;
RRF2 = RRF – RRF1
Figure 44. Loop Current versus Loop Resistance
Alternate Loop Current Limit Configuration
9100 Ω TSI
TIP
RSI
RING
9100 Ω
14 V
RP
1.5KE30
0.01
100 V
1.0 kΩ
CN
1N4002
BN
EN
– 24 V
VEE
14 V
All zener diodes are 7.0 V except as noted.
Figure 45. Alternate Protection Scheme
MOTOROLA
CIRCUIT PERFORMANCE
The following three circuits are presented as typical application examples, and the accompanying graphs indicate
their measured performance. The first circuit (Figure 46) has
a 600 Ω pure resistance as the AC load. The second circuit
(Figures 47) has as an AC load a 900 Ω resistor in series with
a 2.16 µF capacitor. The third circuit (Figure 48) has as an
20
19
18
MJD253
0.01
1.0 k, 2%
17
100
TIP
RAC
600 Ω
VEE
9.1 k
VL RING
16
VDD
EP
PDI
BP
ST1
CP
VDG
TSI
VAG
15
12
+ 5.0 V
0.1
ST2/PDI
5.0 µF
13
ST1
14
9
MC33121
9.1 k
5
1.0 k, 2%
0.01
VCC
AC load, a complex network composed of an 820 Ω resistor
in parallel with 0.115 µF, and those in series with a 220 Ω resistor. In the graphs of Figures 49 – 51, RL = Return Loss,
THR = Transhybrid Rejection, GTX = Transmit Gain, GRX =
Receive Gain.
4
100
RSI
RXI
CN
RFO
30.6 k
10
8
4.7 k
20.3 k 600
1.0 µF
3
MJD243
TXO
BN
1.0 µF
10 k
VEE
2
1
– 28 V
CF
EN
VQB
VEE
7
300
6
20
600
15.8 k
11
RECEIVE
IN (VRX)
0.005
31.6 k
–
+
TRANSMIT
OUT (VTX)
1.0 µF
10 µF
0.1
Figure 46. 600 Ω System
20
19
MJD253
18
0.01
1.0 k, 2%
17
100
TIP VEE
RAC
900 Ω
2.16 µF
9.1 k
VL RING
16
VDD
EP
PDI
BP
ST1
CP
VDG
TSI
VAG
15
12
+ 5.0 V
0.1
ST2/PDI
5.0 µF
13
ST1
14
9
MC33121
9.1 k
5
1.0 k, 2%
0.01
VCC
4
100
RSI
RXI
CN
RFO
45.9 k 42 nF
10
8
4.7 k
31.6 k
31.2 k
31.6 k
62 nF
MJD243
3
BN
TXO
11
1.0 µF
10 k
VEE
2
1
– 28 V
EN
VEE
CF
VQB
7
300
6
20
RECEIVE
IN (VRX)
–
+
TRANSMIT
OUT (VTX)
1.0 µF
0.1
10 µF
Figure 47. 900 Ω and 2.16 µF System
MOTOROLA
MC33121
27
20
19
MJD253 18
0.01
RAC
VEE
TIP
100
1.0 k, 2% 17
9.1 k
16
9.1 k
5
820
VL RING
VCC
VDD
EP
PDI
BP
ST1
CP
VDG
TSI
VAG
MC33121
220
RXI
RSI
15
12
+ 5.0 V
0.1
ST2/PDI
5.0 µF
13
ST1
14
2.25 nF
9
41.8 k
10
4.7 k
1.0 k, 2%
0.01
100
4
RFO
CN
1
– 28 V
31.6 k
7.61 k
28.4 k
31.6 k
MJD243 3 BN
2
RECEIVE
IN (VRX)
8
3.3 nF
VEE
11.2 k
TXO 11
CF
EN
VQB
VEE
1.0 µF
7
300
6
20
10 k
1.0 µF
–
+
TRANSMIT
OUT (VTX)
1.0 µF
0.1
10 µF
Figure 48. 220 Ω and 820 Ω //0.115 µF System
90
50
RL
RL
40
50
TEST RESULTS (dB)
TEST RESULTS (dB)
70
THR
30
+0.1
GTX
30
THR
20
+0.2
GTX
0
0
GRX
–0.1
100
1.0 k
GRX
10 k
–0.2
100
1.0 k
10 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 49. Circuit Performance, 600 Ω System
Figure 50. Circuit Performance
900 Ω and 2.16 µF System
MC33121
28
MOTOROLA
80
RL
TEST RESULTS (dB)
60
VA
40
VB
+0.2
GTX
0
GRX
–0.2
100
T
REFERENCE
NETWORK
THR
20
1.0 k
IL
MC33121
CIRCUIT
(FIGURES 46,
47 OR 48)
R
10 k
f, FREQUENCY (Hz)
Ť
Ť
Reference Network = RAC of Figures 46 to 48.
VB
Return Loss = 20 log VA
VA – VB
Figure 51. Circuit Performance
820 Ω//0.115 µF and 220 Ω System
)
Figure 52. Return Loss Test Circuit
for Figures 46 to 51
GLOSSARY
ATTENUATION — A decrease in magnitude of a communication signal, usually expressed in dB.
BALANCE NETWORK — That part of the SLIC circuit which
provides transhybrid rejection.
BANDWIDTH — The range of information carrying frequencies of a communication system.
BATTERY — The voltage which provides the loop current,
and in some cases powers the SLIC circuit. The name
derives from the fact that COs have always used batteries, in
conjunction with AC power, to provide this voltage.
BATTERY FEED RESISTANCE — The equivalent Thevenin
DC resistance of the SLIC circuit for supplying loop current.
Traditionally it is 400 Ω .
C–MESSAGE FILTER — A frequency weighting which evaluates the effects of noise on a typical subscriber’s system.
CENTRAL OFFICE — Abbreviated CO, it is a main telephone office, usually within a few miles of its subscribers,
that houses switching gear for interconnection within its
exchange area, and to the rest of the telephone system. A
typical CO can handle up to 10,000 subscriber numbers.
CODEC — Coder/Decoder — Interfacing between the SLIC
and the digital switch, it converts the SLIC’s transmit signal to
digital, and converts the digital receive signal to analog.
dB — A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:
10 • log (P1/P2) for power measurements, and
20 • log (V1/V2) for voltage measurements.
dBm — An indication of signal power. 1.0 mW across 600 Ω ,
or 0.775 Vrms, is defined as 0 dBm. Any other voltage level
MOTOROLA
is converted to dBm by:
dBm = 20 • log (Vrms/0.775), or
dBm = [20 • log (Vrms)] + 2.22.
dBmp — Indicates dBm measurement using a psophometric
weighting filter.
dBrn — Indicates a dBm measurement relative to 1.0 pW
power level into 600 Ω . Generally used for noise measurements, 0 dBrn = – 90 dBm.
dBrnC — Indicates a dBrn measurement using a C–
message weighting filter.
DTMF — Dual Tone Multifrequency. It is the “tone dialing”
system based on outputting two non–harmonic related frequencies simultaneously to identify the number dialed. Eight
frequencies have been assigned to the four rows and four
columns of a keypad.
FAULT — An incorrect condition where Tip is accidentally
connected to the battery voltage, or Ring is connected to
ground, or both. The most common fault is Ring to ground.
FOUR WIRE CIRCUIT — The portion of a telephone, or central office, which operates on two pairs of wires. One pair is
for the transmit path, and one pair is for the receive path.
FULL DUPLEX — A transmission system which permits
communication in both directions simultaneously. The standard handset telephone system is full duplex.
GAIN — The change in signal amplitude (increase or decrease) after passing through an amplifier, or other circuit
stage. Usually expressed in dB, an increase is a positive
number, and a decrease is a negative number.
MC33121
29
HALF DUPLEX — A transmission system which permits
communication in one direction at a time. CB radios, with
“push–to–talk” switches, and voice activated speakerphones, are half duplex.
HOOKSWITCH — A switch, within the telephone, which connects the telephone circuit to the subscriber loop. The name
derives from old telephones where the switch was activated
by lifting the receiver off and onto a hook on the side of the
phone.
HYBRID — Another name for a two–to–four wire converter.
IDLE CHANNEL NOISE — Residual background noise
when transmit and receive signals are absent.
LINE CARD — The PC board and circuitry in the CO or PBX
which connects to the subscriber’s phone line. A line card
may hold circuitry for one subscriber, or a number of subscribers.
LONGITUDINAL BALANCE — The ability of the SLIC to
reject longitudinal signals on Tip and Ring.
LONGITUDINAL SIGNALS — Common mode signals.
LOOP — The loop formed by the two subscriber wires (Tip
and Ring) connected to the telephone at one end, and the
central office (or PBX) at the other end. Generally, it is a floating system not referred to ground, or AC power.
LOOP CURRENT — The DC current which flows through
the subscriber loop. It is typically provided by the central
office or PBX, and ranges from 20 to 120 mA.
OFF–HOOK — The condition when the telephone is connected to the phone system, permitting the loop current to
flow. The central office detects the DC current as an indication that the phone is busy.
ON–HOOK — The condition when the telephone is disconnected from the phone system, and no DC loop current
flows. The central office regards an on–hook phone as available for ringing.
PABX — Private Automatic Branch Exchange. In effect, a
miniature central office, it is a customer owned switching system servicing the phones within a facility, such as an office
building. A portion of the PABX connects to the Bell (or other
local) telephone system.
PROTECTION, PRIMARY — Usually consisting of carbon
blocks or gas discharge tubes, it absorbs the bulk of a lightning induced transient by clamping the voltages to less than
± 1500 V.
PROTECTION, SECONDARY — Usually located on the line
card, it protects the SLIC and associated circuits from transient surges. Typically, it must be capable of clamping a
± 1.5 kV surge of 1.0 ms duration.
PULSE DIALING — A dialing system whereby the loop current is interrupted a number of times in quick succession.
The number of interruptions corresponds to the number
dialed, and the interruption rate is typically 10 per second.
The old rotary phones, and many new pushbutton phones,
use pulse dialing.
MC33121
30
RECEIVE PATH — Within the CO or PBX it is the speech
path from the internal switching system towards the phone
line (Tip & Ring).
REN — Ringer Equivalence Number. An indication of the impedance or loading factor of a telephone bell or ringer circuit.
An REN of 1.0 equals 8.0 kΩ . The Bell system typically
permits a maximum of 5.0 REN (1.6 kΩ) on an individual
subscriber line. A minimum REN of 0.2 (40 kΩ) is required by
the Bell system.
[
RETURN LOSS — Expressed in dB, it is a measure of how
well the SLIC’s AC impedance matches the line’s AC characteristic impedance. With a perfect match, there is no reflected signal, and therefore infinite return loss. It is
calculated from:
RL
+ 20 • log (Z(ZLine )– ZZCKT))
Line
CKT
RING — One of the two wires connecting the central office to
a telephone. The name derives from the ring portion of the
plugs used by operators (in older equipment) to make the
connection. Ring is traditionally negative with respect to Tip.
SLIC — Subscriber Line Interface Circuit. It is the circuitry
within the CO or PBX which connects to the user’s phone
line.
SUBSCRIBER — The customer at the telephone end of the
line.
SUBSCRIBER LINE — The system consisting of the user’s
telephone, the interconnecting wires, and the central office
equipment dedicated to that subscriber (also referred to as a
loop).
TIP — One of the two wires connecting the central office to a
telephone. The name derives from the tip of the plugs used
by operators (in older equipment) to make the connection.
Tip is traditionally positive with respect to Ring.
TRANSHYBRID REJECTION — The rejection (in dB) of the
reflected signal in the transmit path resulting from a receive
signal applied to the SLIC.
TRANSMIT PATH — Within the CO or PBX it is the speech
path from the phone line (Tip & Ring) towards the internal
switching system.
TWO WIRE CIRCUIT — Refers to the two wires connecting
the central office to the subscriber’s telephone. Commonly
referred to as Tip and Ring, the two wires carry both transmit
and receive signals in a differential manner.
TWO–TO–FOUR WIRE CONVERTER — A circuit which
has four wires (on one side) — two (signal & ground) for the
outgoing signal, and two for the incoming signal. The outgoing signal is sent out differentially on the two wire side (the
other side), and incoming differential signals received on the
two wire side are directed to the four wire side. Additional circuit within cancels the reflected outgoing signal to keep it
separate from the incoming signal.
VOICEBAND — That portion of the audio frequency range
used for transmission across the telephone system. Typically, it is 300 to 3400 Hz.
MOTOROLA
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 738–03
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
0.25 (0.010)
20 PL
0.25 (0.010)
20 PL
M
T A
M
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA
MC33121
31
FN SUFFIX
PLCC
CASE 776–02
0.007 (0.180)
B
M
T L–M
N
S
T L–M
S
S
Y BRK
–N–
0.007 (0.180)
U
M
N
S
D
Z
–M–
–L–
W
28
D
X
G1
0.010 (0.250)
T L–M
S
N
S
S
V
1
VIEW D–D
A
0.007 (0.180)
R
0.007 (0.180)
T L–M
M
S
N
S
C
M
T L–M
S
N
0.007 (0.180)
H
Z
M
T L–M
N
S
S
S
K1
E
0.004 (0.100)
G
J
S
SEATING
PLANE
K
F
VIEW S
G1
0.010 (0.250)
–T–
T L–M
S
N
S
0.007 (0.180)
M
T L–M
S
N
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER
EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING
PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD
FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP
TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION.
THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE
GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT
CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10_
0.410
0.430
0.040
–––
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10_
10.42
10.92
1.02
–––
How to reach us:
USA/EUROPE: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: [email protected] – TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC33121
32
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MOTOROLA