iPlay TM Media Player Controller MP620DUCG-C Datasheet Revision 0.99 2009/03/06 iPlayTM MP620DUCG-C Datasheet TABLE OF CONTENT 1 GENERAL DESCRIPTION .......................................................................................................................................3 2 FEATURES .................................................................................................................................................................4 3 BLOCK DIAGRAM ....................................................................................................................................................6 4 FUNCTIONAL DESCRIPTION.................................................................................................................................7 4.1 IMAGE PROCESSING UNIT (IPU)...................................................................................................................... 7 4.2 IMAGE DISPLAY UNIT (IDU) ............................................................................................................................. 7 4.3 JPEG CODEC ................................................................................................................................................ 8 4.4 CPU ................................................................................................................................................................. 9 4.5 MEMORY MAPPING........................................................................................................................................... 9 4.6 DMA CONTROLLER ........................................................................................................................................ 10 4.7 MEMORY CARD CONTROLLER ....................................................................................................................... 11 4.8 USB DEVICE CONTROLLER ........................................................................................................................... 11 4.9 ANALOG AUDIO INTERFACE ............................................................................................................................ 11 4.9.1 External Circuit for Speaker Amplifier................................................................................................11 4.9.2 External Circuit for Headphone Amplifier ......................................................................................... 12 4.10 GPIO.............................................................................................................................................................. 13 5 OPERATION MODES..............................................................................................................................................14 6 PIN CONFIGURATION............................................................................................................................................15 7 ELECTRICAL CHARACTERISTICS ....................................................................................................................31 7.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................................................... 31 7.2 RECOMMENDED OPERATING CONDITIONS .................................................................................................... 31 7.3 DC CHARACTERISTICS .................................................................................................................................. 31 7.4 CAPACITANCE ................................................................................................................................................. 32 7.5 AC CHARACTERISTICS ................................................................................................................................... 32 7.5.1 Reset Timing ........................................................................................................................................ 32 7.5.2 Input Clock............................................................................................................................................ 32 7.5.3 SDRAM Interface Timing .................................................................................................................... 33 7.5.4 Display Output...................................................................................................................................... 33 7.6 8 PACKAGE DIMENSIONS .................................................................................................................................. 36 REVISION HISTORY ...............................................................................................................................................40 Magic Pixel Confidential -2- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 1 General Description The MP620D is a high integration SOC (System On Chip) for digital picture frame application. It implements all necessary peripherals in one chip and high performance JPEG Codec engine (Decoding Speed: 24MPixel/sec) and Audio DAC/Power Amplifier/USB Device 2.0/USB OTG 2.0 /Digital TCON/ VGH/VGL(PWM)/LED Driver inside. The central part of the chip is a high performance 32-bit RISC CPU which allows flexible system control. High qualities Audio DAC & Power Amplifier are integrated to MP620D, the user can playback MP3, WMA as the background music when playing Slide-Show. It can also support Motion JPEG captured by digital camera up to VGA@30FPS / 1280x720@15FPS. It supports true-color (24bit) On-Screen Display with high-resolution for friendly user interface. MP620D provides a versatile hardwired interface to support most of popular memory card standards, including SD/ mini SD/ Micro SD (It can support SD2.0 for SDHC specification), MMC/RS-MMC, xD, Memory Stick/Pro/MSPROHG. It offers the maximum flexibility and reliable to the customer. For data transfer to/from PC/Pict-Bridge enabled printer, it provides both USB and popular UART interfaces. It includes a USB 2.0 device controller that is compliant with the USB 2.0 standard. 4 endpoints have been implemented to achieve variety of requirements for image/audio data upload or download. It also includes an IR (Infra-Red) controller supporting NEC Button and Remote Point Mouse protocols. For flexible peripheral control and user interface, it provides several GPIOs, including PWM output. The mass storage interface is designed to support boot from SLC/MLC NAND Flash. With the abundant features and superior performance and quality, MP620D provides a best cost-effective solution for digital photo frame. Magic Pixel Confidential -3- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 2 Features z Power - z Dual Power. 1.8V for core, 3.3V/1.8V for I/O Image Processing Unit - Hardware scaling engine to scale up and down images with edge enhancement filter for resolution conversion or image zooming to avoid zigzag. - z New scaling down engine to minimize the jaggy side-effect. JPEG Codec - Support JPEG resolution up to 64MPixel (8K x 8K) - High speed JPEG compression and decompression (24MPixel/sec) - Support image sub-sampling after JPEG decompression - Support image rotation (by S/W) / Zoom In / Panning. - Restore photos to NOR Flash is possible due to the resizing & Hardware JPEG encoding capabilities of MP620D. Audio/Video decoding accelerator ‧ Full bit-rate support of MP3, WMA ‧ Hardware Motion-JPEG up to VGA@30fps /1280x720@15FPS Multiple Boot up methods ‧ Boot from parallel NOR Flash ‧ Boot from NAND Flash ‧ Boot from SD * Embedded boot loader to reduce the risk of “boot from SLC/MLC” z Memory Interface - SDRAM support z - - Support both SDRAM/DDR SDRAM. NAND Flash support z Support SLC/MLC NAND-type Flash memory (support 4-bit ECC) z Support big-size NAND Flash with multiple-die NAND Flash (e.g. 8Gb/16Gb/32Gb) Support Parallel NOR-type Flash memory, up to 4MB with x8 bit data width for both BIOS access and data storage. z Memory Card and Hard drive Interface ‧ Support Security Disk (SD1.1 & SDHC with SD 2.0 ), Multi-Media Card, Memory Stick Pro/MSPROHG, xD Picture Card ‧ Support multi-sector DMA Magic Pixel Confidential -4- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet z Embedded Audio DAC & Power Amplifier - Audio DAC z High performance Audio DAC (16bit, 93dB) - Audio Headphone Driver - Audio Power Amplifier z z 1 Watt Stereo (0.5W +0.5W) USB Interface - Embedded one port USB OTG 2.0 & one port Device 2.0 - High-speed USB 2.0 device function with embedded USB PHY - Support Direct Print function (Pict-Bridge) - Power saving control to comply with USB spec. - Support uploading and downloading capability - Support USB Mass Storage Class for both High Speed Device and High Speed Host functions z Display Interface ‧ Embedded Digital TCON z Built-in charge pump for VGH/VGL & LED Driver z Colorful Graphic OSD - Support true color (24bit) On-Screen-Display with high resolution for content-rich display user-interface - 2nd OSD engine supports 2-, 4- or 8-bit palette-indexed Bit-mapped On Screen Display (OSD). z CPU & Misc. - Embedded high performance 32-bit RISC processor and 512MB memory addressing capability - BIOS storage in Flash memory with in-system-programming (ISP) capability - Embedded Spectrum phase-locked loop(PLL) with independently programmable multiple clock outputs to reduce the EMI cost. - Support up to 160MHz system clock - Flexible GPIO control for variety of peripheral control. z Package - z 216-pin LQFP (24mm x 24mm x 1.6mm) System Development Kit & Software Support - Support real time-OS u-iTron - Schematics and application note - UI (User Interface) Builder Magic Pixel Confidential -5- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 3 Block diagram Clock Generator PLL JPEG Codec GPIO Interrupt Controller 32-bit RISC CPU Bus Interface Unit Scaler I-Cache D-Cache Memory Card Controller Memory Card NOR Flash DDR/ SDRAM Memory Controller DMA Controller Peripheral Amp Audio Codec Digital Audio Interface Speaker/ Headphone USB 2.0 Device Controller UART Controller PC USB-OTG Controller USB Storage Device Display Controller TCON LCD Figure 3-1 MP620D Block Diagram Magic Pixel Confidential -6- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 4 Functional Description The MP620D is a high-integration SOC (System On Chip) for DPF (Digital Picture Frame) application. It implements all necessary peripherals in one chip. 4.1 Image Processing Unit (IPU) To be capable of full screen display and image zoom-in function for variable size of pictures, the MP620D embeds a flexible scaling engine. The core of image resizing is a bi-linear scaler and two image sub-sampling blocks. Image shrinking and enlargement are both supported. By applying multi-pass image scaling, the allowable processing resolution is virtually unlimited. 4.2 Image Display Unit (IDU) The Image Display Unit supports variety of analog LCD interface. A programmable color space conversion unit is also implemented to support both RGB and YCbCr/YPbPr outputs. MP620D provides great flexibility in display timing settings. Typical display output timing is illustrated in Fig. 4-2-1 and Fig. 4-2-2. All the parameters shown in the figures are programmable. Clock signal (VDCK) Horizontal sync. signal (VHSYNC) Ths Thbp Thdis Thfp Data enable signal (VDVALID) Data signal (VD0 - VD7) Horizontal data invalid period D1 D2 Horizontal data invalid period Dn-1 Dn Fig. 4-2-1. Display output horizontal timing diagram Horizontal sync. signal (VHSYNC) Vertical sync. signal (VVSYNC) Tvs Data signal (VD0 - VD7) Tvbp Vertical data invalid period Tvdis DH1 DH2 Tvfp DHm-1 DHm Vertical data invalid period Fig. 4-2-2. Display output vertical timing diagram Magic Pixel Confidential -7- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet A bitmap OSD is also included. 8 , 4 or 2 bits index per pixel can be chosen. With 8-bit index, 128 OSD colors and 8 programmable blending colors can be selected. Or with 2-bit index, only 3 programmable blending colors can be used. But the latter case will save the required memory size of the OSD bitmap. Through the Palette registers that specify the OSD color and blending ratio, it allows quite flexible and content-rich user interface. An analog TCON is also included to support glue-less connection with variety of panels. With most parameters programmable, it can support variety of panels with maximum flexibility. 4.3 JPEG CODEC A standard JPEG Compression/Decompression engine is embedded. It is compliant to the Baseline JPEG Standard. It accepts image data in YCbCr 4:2:2 or 4:4:4 format. YCbCr 4:2:0 compression format is also supported, but the source image in DRAM buffer should be in 4:2:2 format still. CDU will perform the sub-sampling on Cb and Cr. 4:2:0 4:2:2 4:4:4 Y Y Y Y Cb Cr 8 MCU Types 8 Y 8 Y 16 × 16 MCU size Cb 16 × 8 Cr 8 8 8 Y Cb Cr 8×8 Table 4-3-1. MCU types supported by CDU It is capable of processing image with resolution up to 8Kx8K. The image source and compressed stream are both acquired from and delivered to SDRAM through DMA. It needs no CPU intervention for data transfer. Single cycle throughput can be achieved to allow real-time capturing. It can always catch up and deliver high performance for continuous image or video capturing. It supports two sets of Quantization and Huffman tables respectively. They are both programmable for better compression quality adjustment. The latter is usually fixed in factory, while the Quantization table can be adjusted with pre-determined values for image quality and compression ratio tradeoff controlled by the end users. It also supports Restart Marker insertion and detection when enabled. Other markers or headers should be handled by the firmware instead. The JPEG module consists of System Bus Interface, configuration registers, dedicated SRAM modules, system memory interface, Scaling Unit and Control Unit. CPU can configure and start/stop encoding/decoding process via the 32-bit System Bus Interface. In encoding mode, it reads in images pixel data, from external system SDRAM and outputs the encoded stream data back to SDRAM. While decoding, stream data is read from SDRAM, with header information (Huffman tables, quantization tables, etc.) already peeled by CPU. Pixel data is output MCU by MCU. An interrupt is triggered when encoding/decoding process is finished. Magic Pixel Confidential -8- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 4.4 CPU The MP620D embeds a 32-bit RISC CPU, with a 32-bit MAC unit and instruction extension for audio performance enhancement. It offers good performance for audio processing and other application extensions that require intensive signal processing. The operating frequency of CPU can be dynamically adjusted. Lower frequency setting can be used to save the power consumption. SLEEP instruction can also be used to put the CPU into sleep mode, which will reduce the power consumption of CPU to the minimum level. Any enabled interrupt can then be used to wake up the CPU to normal operation. It supports complete tool chain, including firmware, driver and debug utilities to facilitate software development. 4.5 Memory Mapping The CPU supports 4GB of virtual addressing. It is divided into 4 segments as the following table. The 4GB of virtual address space are mapped to 512MB of physical space by ignoring the 3 MSBs. Virtual Address Space 0xE000_0000 ~ 0xFFFF_FFFF 0xC000_0000 ~ 0xDFFF_FFFF 0xA000_0000 ~ 0xBFFF_FFFF 0x8000_0000 ~ 0x9FFF_FFFF 0x6000_0000 ~ 0x7FFF_FFFF 0x4000_0000 ~ 0x5FFF_FFFF 0x2000_0000 ~ 0x3FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF Description KSEG2. 1GB. Addressable in Kernel mode. Cached KSEG1. 512MB. Addressable in Kernel mode. Uncached KSEG0. 512MB. Addressable in Kernel mode. Cached KUSEG. 2GB. Addressable in Kernel or User mode. Cached Mapped Physical Address 0x0000_0000 ~ 0x1FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF 0x0000_0000 ~ 0x1FFF_FFFF The 512MB of physical space is further mapped as follows: Physical Space 0x1C00_0000 ~ 0x1FFF_FFFF 0x1800_6000 ~ 0x1BFF_FFFF 0x1800_0000 ~ 0x1800_5FFF 0x1400_0000 ~ 0x17FF_FFFF 0x1000_0000 ~ 0x13FF_FFFF 0x0800_0000 ~ 0x0FFF_FFFF 0x0000_0000 ~ 0x07FF_FFFF Range 448 ~ 512MB 408 ~ 448MB 384 ~ 408MB 320 ~ 384MB 256 ~ 320MB 128 ~ 256MB 0 ~ 128MB Description Code Flash/ROM Reserved Scratch Pad Data Memory Reserved Peripheral Register File DRAM The following table also summarizes the register file mapping. Magic Pixel Confidential -9- Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Physical Space 0x0FC0_8000 ~ 0x0FC0_83FF 0x0FC0_0000 ~ 0x0FC0_3FFF 0x0803_8000 ~ 0x0FBF_FFFF 0x0803_4000 ~ 0x0803_7FFF 0x0803_0000 ~ 0x0803_3FFF 0x0802_6000 ~ 0x0802_FFFF 0x0802_4000 ~ 0x0802_5FFF 0x0802_2000 ~ 0x0802_3FFF 0x0802_0000 ~ 0x0802_1FFF 0x0801_E000 ~ 0x0801_FFFF 0x0801_C000 ~ 0x0801_DFFF 0x0801_A000 ~ 0x0801_BFFF 0x0801_9000 ~ 0x0801_9FFF 0x0801_8000 ~ 0x0801_8FFF 0x0801_6000 ~ 0x0801_7FFF 0x0801_4000 ~ 0x0801_5FFF 0x0801_2000 ~ 0x0801_3FFF 0x0801_0000 ~ 0x0801_1FFF 0x0800_E000 ~ 0x0800_FFFF 0x0800_C000 ~ 0x0800_DFFF 0x0800_B000 ~ 0x0800_BFFF 0x0800_A000 ~ 0x0800_AFFF 0x0800_8000 ~ 0x0800_9FFF 0x0800_4000 ~ 0x0800_4FFF 0x0800_0000 ~ 0x0800_1FFF Contents Reserved Reserved Reserved Reserved Reserved Reserved Reserved CDU Registers Memory Card Control Registers IDU/OSD Registers GPIO Registers RTC Registers USB-OTG Registers USB 2.0 Device Registers Reserved AIU Registers UARTH Registers SIO Registers Timer Registers DMA Control Registers Interrupt Handler Control Registers Clock Generator Registers BIU/System Control Registers IPU SRAM Registers IPU Registers 4.6 DMA Controller The DMA Controller manages all the SDRAM access requests from internal module or external peripheral. It arbitrates among the requests with the pre-defined priority. Through each channel, data is transferred from DRAM to device, or vice versa. The DMA channels that require real-time and high data bandwidth are assigned with high priorities. Memory to memory DMA can also be supported in certain configuration. It can also be enabled to take advantage of the bank-interleave feature of SDRAM to increase the memory bandwidth. To save the SDRAM power consumption, several levels of power down mode can also be employed. A quite flexible addressing scheme is supported to maximize SDRAM space usage. It supports a wide range of SDRAM types, from 16Mb to 256Mb, x16-bit bus. It also supports DDR SDRAM, from 16Mb to 256Mb, x16-bit bus. It allows the customer to make the best choice for their application. The SDRAM timing is also programmable to be fit to variety of SDRAM performance. Besides SDRAM, it also takes care of the ROM/Code Flash and external peripheral accesses. The DMA Controller arbitrates among the 3 types of requests automatically. A Memory Bus Interface Unit is included to handle the interfaces with these 3 kinds of devices. It supports multiple configurations and programmable timing for maximum compatibility. Up to 8MB of Code Flash/ROM can be supported. Not only for firmware code, the NOR Flash interface can also be used for image storage if desired. Magic Pixel Confidential - 10 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 4.7 Memory Card Controller The Memory Card Controller is responsible of controlling the data accesses with external image storage media. It supports Secure Digital Memory Card (SD), Multi Media Card (MMC), xD , Memory Stick, Memory Stick Pro and Memory Stick Pro HG. Coexist with the memory cards, on-board NAND Flash can also be supported. Hardware ECC and CRC are implemented for MMC/SD support respectively. For MMC or SD, however, it allows only through DMA. The bus interface timing is programmable for maximum compatibility. 4.8 USB Device Controller The built-in USB Device Controller support several endpoints for communication with USB Host. - Control Read/Write transfer - Interrupt Transfer - Downstream Bulk Transfer from Host - Upstream Bulk Transfer to Host - Upstream Video Isochronous /Bulk Transfer to Host - Upstream Audio Isochronous /Bulk Transfer to Host The upstream bulk or isochronous transfer is accomplished with DMA operation. The software we provided includes the protocol of MSDC (Mass Storage Device Class) which is compatible with the OSs Microsoft Windows 2000, Windows XP, Windows Vista, Mac OS X 10.2.4 or later. 4.9 Analog Audio Interface MP620D supports stereo head phone output, speaker and auxiliary audio outputs. 4.9.1 External Circuit for Speaker Amplifier AEQ1, AEQ2 and AEQ3 can be used to fine-tune the speaker tone and gain. The reference circuit is shown as below. ASPKEQ1 C1 R1 ASPKEQ2 R2 C2 ASPKEQ3 Magic Pixel Confidential - 11 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Figure 4-1 RC filter circuit for Speaker Amplifier C1, R1 and C2, R2 are used to set the low and high cut-off frequency of the Speaker Amplifier respectively. Gain = R2 R1 f1 = 1 2π × R1 × C1 f2 = 1 2π × R 2 × C 2 Gain 0dB -3dB f1 4.9.2 f2 Frequency External Circuit for Headphone Amplifier The reference circuit for Headphone is shown as below: Headphone Amplifer CD RL CD : capacitance of the DC blocking capacitor RL : DC loading resistance of the Headset Figure 4-2 Reference circuit for Headphone CD and RL determines the cut-off frequency of the hi-pass filter as the following equation: Fc = 1 2π × CD × RL Magic Pixel Confidential - 12 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet e.g. 1. CD = 10 μF Æ Fc = 1/(2x3.14x10μx 32ohm) = 497HZ 2. CD = 22 μF Æ Fc = 1/(2x3.14x22μx 32ohm) = 226HZ 3. CD = 47 μF Æ Fc = 1/(2x3.14x47μx 32ohm) = 105HZ rd For MP3 application, it is suggested to use the 3 value for better bass performance. Gain 0dB -3dB Frequency FC 4.10 GPIO The MP620D provides 8 dedicated GPIO pins. There are also additional 68 pins can be configured as GPIO if the associated function is not used. Most of the pins can be programmed for alternative functions by setting corresponding configuration register. Those dedicated GPIO pins can be enabled to generate interrupt with level or edge trigger. The polarity of level or edge interrupt is programmable to fit variety of application requirement. The GPIO input pins with interrupt capability, when enabled, can also be used to wake up the chip from deep power down mode. Magic Pixel Confidential - 13 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 5 Operation Modes To fulfill the functions that a digital photo frame requires, the MP620D can be used in, but not limited to, the following operation modes: z Playback/OS command mode The stored images/audio files can be played back to LCD panel, and speaker output port in this - mode - Executable software can be run at this mode for any application - Manage the available modules of DPF z The stored images/audio can be uploaded to PC for further application - z - USB upload mode USB download mode DPF firmware can be updated by downloading the new firmware code and activated automatically - Executable codes for 32-bit RISC can be downloaded from PC and run at embedded OS environment - Image or MP3 files can be playback by using the existing hardware inside the DPF Magic Pixel Confidential - 14 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 6 Pin Configuration Magic Pixel Confidential - 15 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 1. Memory Interface (44) Default Pin Name Function MD[7:0] MD[11:8] MD[15:12] MA[7:0] MA[12:8] MBA[0] MBA[1] MRASx MCASx MWEx MDQM[0] MD[7:0] MD[11:8]/ MA[21:18] MD[15:12]/ MA[25:22] MA[7:0] MA[12:8] BA[0]/MA[13] BA[1]/MA[14] RAS#/MA[15] CAS#/MOE# MWE# DQM[0]/ MA[16] MDQM[1] DQM[1]/ MA[17] MSDCK MSDCKE MSDCSx MROMCSx MSDCKx MSDVREF MSDLDQS MSDUDQS SDCLK SDCKE SDRAMCS# MROMCS# SDCLKx MSDVREF LDQS UDQS SDRAM PROM / NOR Flash Alt. Func. 1 Alt. Func. 2 Type IO MD[7:0] MD[7:0] MD[11:8] MA[21:18] MD[15:12] MA[7:0] MA[12:8] BA[0] BA[1] RAS# CAS# MWE# MA[25:22] MA[7:0] MA[12:8] MA[13] MA[14] MA[15] MOE# MWE# DQM[0] MA[16] IO DQM[1] MA[17] IO SDCLK SDCKE SDRAMCS# MROMCS# SDCLKx MSDVREF LDQS UDQS Magic Pixel Confidential - 16 - IO IO IO IO IO IO IO IO IO IO IO IO O IO I IO IO Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Pin Name MD[7:0] MD[7:0] Pin Number I/O Definition 9, 8, 7,6, I/O DRAM Data Bus bit 7~0 212, 211,210,209 MD[11:8] MD[11:8] PROM/NOR Flash Data bit 7~0 15, 14,11,10 MA[21:18] MD[15:12] MD[15:12] 19, 18, 17, 16 I/O DRAM Data Bus bit 11~8 O PROM/NOR Flash Address bit 21~18 I/O DRAM Data Bus bit 15 MA[25:22] MA[7:0] MA[7:0] PROM/NOR Flash Address bit 25~22 O 193,192,191,190, PROM/NOR Flash Address Bus bit 7~0 188,187,186,185 MA[12:8] MA[12:8] 204,197, 196, 195, O BA[0] 183 O MA[13] MBA[1] BA[1] RAS# 184 O 199 O CAS# MWE# DRAM Row Address Strobe (Active low) PROM/NOR Flash Address Bus bit 15 201 O MOE# MWEx DRAM Bank Selection 1 PROM/NOR Flash Address Bus bit 14 MA[15] MCASx DRAM Bank Selection 0 PROM/NOR Flash Address Bus bit 13 MA[14] MRASx DRAM Address Bus bit 12~8 PROM/NOR Flash Address Bus bit 12~8 194 MBA[0] DRAM Address Bus bit 7~0 DRAM Column Address Strobe (Active low) PROM/NOR Flash Output Enable (Active low) 200 O DRAM Write Enable (Active low) PROM/NOR Flash Write Enable (Active low) MDQM[0] DQM[0] 208 O MA[16] MDQM[1] DQM[1] DRAM Data Input/Output Mask 0 PROM/NOR Flash Address Bus bit 16 5 O MA[17] DRAM Data Input/Output Mask 1 PROM/NOR Flash Address Bus bit 17 MSDCK SDCLK 205 I/O (1) SDCLK: Output Clock to SDRAM MSDCKx SDCLK# 207 I/O (2) SDCLK&SDCLK#: Output Clock to DDR SDRAM SDCLK and SDCLK# are differential clock Outputs. MSDCKE SDCKE 203 O Clock Enable Signal for DRAM Clock MSDCSx SDRAMCS# 202 O DRAM Chip Select MROMCSx MROMCS# 177 O PROM/NOR Flash Chip Select MSDVREF MSDVREF 3 MSDLDQS LDQS 214 I/O Data Strobe : Output with read data, input with write data. MSDUDQS UDQS 1 I/O Edge-aligned with read data, centered in write data. Used to Analog DRAM Reference Voltage capture write data. Magic Pixel Confidential - 17 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 2. Memory Card Interface (SD/MMC/MS Pro/xD) (29) Alt. Func. 1 Pin Name Default FSD_CLK FSD_CMD FSD_DAT[3:0] FSD_DAT[7:4] FSDIO_CMD FCLE FALE FA2 FA3 FMS_CLK FMS_BS FMS_DAT[3:0] FRB FNAND_CE0 FNAND_CE1 FNAND_CE2 FXD_CD FSD_CD FMS_INS FSD_WP FGPIO[0] FGPIO[1] FGPIO[5:2] FGPIO[9:6] FGPIO[10] FGPIO[11] FGPIO[12] FGPIO[13] FGPIO[14] FGPIO[16] FGPIO[17] FGPIO[21:18] FGPIO[23] FGPIO[24] FGPIO[25] FGPIO[26] FGPIO[31] FGPIO[32] FGPIO[33] FGPIO[34] SD SD_CLK SDIO SDIO_CLK MMC MS Pro (HG) NAND SM/xD MMC_CLK SD_CMD MMC_CMD RE# RE# SD_DAT[3:0] MMC_DAT[3:0] DAT[3:0] DAT[3:0] MMC_DAT[7:4] DAT[7:4] DAT[7:4] WE# WE# MS_DAT[4] CLE CLE MS_DAT[5] ALE ALE R/B# R/B# SDIO_DAT[3:0] SDIO_CMD MS_DAT[6] MS_DAT[7] MS_CLK MS_BS MS_DAT[3:0] CE0# CE1# CE2# CD# SD_CD# SD_CD# SD_WP_IN# SD_WP_IN# MS_INS Magic Pixel Confidential - 18 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Pin Name FSD_CLK FSD_CMD FSDIO_CMD FMS_CLK Pin Number I/O Definition O SD Clock SDIO_CLK O SDIO Clock MMC_CLK O MMC Clock FGPIO[0] I/O General purpose I/O 0 shared with memory card I/O SD Command MMC_CMD I/O MMC Command RE# I/O SM/xD Read Enable Strobe (Active low) RE# I/O NAND Read Enable Strobe (Active low) FGPIO[1] I/O General purpose I/O 1 shared with memory card I/O SDIO Command WE# I/O SM/xD Write Enable Strobe (Active low) WE# I/O NAND Write Enable Strobe (Active low) FGPIO[10] I/O General purpose I/O 10 shared with memory card O Memory Stick Pro (HG) Clock I/O General purpose I/O 16 shared with memory card O Memory Stick Pro (HG) Bus State I/O General purpose I/O 17 shared with memory card I/O SD Data Bus 3~0 MMC_DAT[3:0] I/O MMC Data Bus 3~0 DAT[3:0] I/O SM/xD Data Bus 3~0 DAT[3:0] I/O NAND Flash Data Bus 3~0 FGPIO[5:2] I/O General purpose I/O 5~2 shared with memory card I/O SDIO Data Bus 3~0 MMC_DAT[7:4] I/O MMC Data Bus 7~4 DAT[7:4] I/O SM/xD Data Bus 7~4 DAT[7:4] I/O NAND Flash Data Bus 7~4 FGPIO[9:6] I/O General purpose I/O 9~6 shared with memory card I/O Memory Stick Pro (HG) Data Bus 3~0 SD_CLK SD_CMD SDIO_CMD MS_CLK 89 91 93 98 FGPIO[16] FMS_BS MS_BS 99 FGPIO[17] FSD_DAT[3:0] FSD_DAT[7:4] FMS_DAT[3:0] SD_DAT[3:0] SDIO_DAT[3:0] MS_DAT[3:0] 83, 82, 81, 80 87, 86, 85, 84 103, 102 101 100 Magic Pixel Confidential - 19 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet FGPIO[21:18] FCLE FALE FNAND_CE0 I/O General purpose I/O 21~18 shared with memory card O MEMORY STICK PRO HG Data Bus 4 CLE O SM/xD Command Latch Enable CLE O NAND Command Latch Enable FGPIO[11] I/O General purpose I/O 11 shared with memory card O MEMORY STICK PRO HG Data Bus 5 ALE O SM/xD Address Latch Enable ALE O NAND Address Latch Enable FGPIO[12] I/O General purpose I/O 12 shared with memory card I/O NAND FLASH Chip Enable Strobe 0 (Active low) I/O General purpose I/O 24 shared with memory card I/O NAND FLASH Chip Enable Strobe 1 (Active low) I/O General purpose I/O 25 shared with memory card I/O SM/xD Chip Enable Strobe (Active low) I/O General purpose I/O 26 shared with memory card I/O NAND FLASH Ready & Busy R/B# I/O SM/xD Ready & Busy FGPIO[23] I/O General purpose I/O 23 shared with memory card I/O MMC/SD Write Protect(Active low) I/O General purpose I/O 34 shared with memory card I/O SM/xD Card Detect(Active low) I/O General purpose I/O 31 shared with memory card I/O MMC/SD Card Detect(Active low) I/O General purpose I/O 32 shared with memory card I/O MEMORY STICK PRO (HG) Insert I/O General purpose I/O 33 shared with memory card I/O MEMORY STICK PRO HG Data Bus 6 I/O General purpose I/O 13 shared with memory card O MEMORY STICK PRO HG Data Bus 7 I/O General purpose I/O 14 shared with memory card MS_DAT[4] MS_DAT[5] CE#0 94 95 105 FGPIO[24] FNAND_CE1 CE#1 106 FGPIO[25] FNAND_CE2 CE#2 107 FGPIO[26] FRB FSD_WP R/B# SD_WP_IN# 104 115 FGPIO[34] FXD_CD CD# 112 FGPIO[31] FSD_CD SD_CD# 113 FGPIO[32] FMS_INS MS_INS 114 FGPIO[33] FA2 MS_DAT[6] 96 FGPIO[13] FA3 MS_DAT[7] FGPIO[14] 97 Magic Pixel Confidential - 20 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 3. UART Interface (6) Pin Name HURX_A HUTX_A HURTS_A HUCTS_A HURX_B HUTX_B Default UGPIO[0] UGPIO[1] UGPIO[2] UGPIO[3] UGPIO[4] UGPIO[5] Pin Name HURX_A Alt. Fnuc. 1 HURX_A HUTX_A HURTS_A HUCTS_A HURX_B HUTX_B Pin Number HURX_A 32 UGPIO[0] HUTX_A HUTX_A HURTS_A 33 34 UGPIO[2] HUCTS_A HUCTS_A HURX_B HURX_B 35 UGPIO[3] 36 UGPIO[4] HUTX_B HUTX_B UGPIO[5] I/O I I/O UGPIO[1] HURTS_A Type IO IO IO IO IO IO 37 Definition High-Speed UART Receive signal A General purpose I/O 0 shared with UART O High-Speed UART Transmit signal A I/O General purpose I/O 1 shared with UART I High-Speed UART flow control of HURX_A I/O General purpose I/O 2 shared with UART O High-Speed UART flow control of HUTX_A I/O General purpose I/O 3 shared with UART I/O High-Speed UART Receive signal B I/O General purpose I/O 4 shared with UART I/O High-Speed UART Transmit signal B I/O General purpose I/O 5 shared with UART Magic Pixel Confidential - 21 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 4. USB OTG 2.0 Interface (8) Pin Name USBOTG_VRES USBOTG_VBUS USBOTG_DM USBOTG_DP USBOTG_ID DRVVBUS UHSXTALI UHSXTALO Default Type USBOTG_VRES Analog IO USBOTG_VBUS 5V Analog IO USBOTG_DM Analog IO USBOTG_DP Analog IO USBOTG_ID Analog IO DRVVBUS O UHSXTALI I UHSXTALO O Pin Name Pin I/O Definition Number USBOTG_VRES 125 ANALOG External resistor connection for current 5VAnalog USB OTG bus power reference USBOTG_VRES USBOTG_VBUS USBOTG_VBUS 126 USBOTG_DM USBOTG_DM 129 ANALOG USB OTG high/full speed D- signal USBOTG_DP USBOTG_DP 130 ANALOG USB OTG high/full speed D+ signal USBOTG_ID USBOTG_ID 131 ANALOG USB OTG ID USBOTG_DRVVBUS 135 O USB OTG 5V power control 137 I The input for 12MHz reference clock USBOTG_DRVVBUS UHSXTALI source UHSXTALI O 136 UHSXTALO The output for 12MHz reference clock source UHSXTALO 5. USB Device 2.0 (4) Pin Name Default Type USBD_VRES USBD_VRES Analog I/O USBD_VBUS USBD_VBUS 5V Analog I/O USBD_DM USBD_DM Analog I/O USBD_DP USBD_DP Analog I/O Pin Name Pin Number I/O Definition USBD_VRES USBD_VRES 124 ANALOG External resistor connection for current reference USBD_VBUS USBD_VBUS 123 ANALOG USB Device bus power USBD_DM USBD_DM 120 ANALOG USB Device high/full speed D- signal USBD_DP USBD_DP 119 ANALOG USB Device high/full speed D+ signal Magic Pixel Confidential - 22 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 6. Digital LCD Interface (28) Pin Name Default VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VD16 VD17 VD18 VGPIO[0] VGPIO[1] VGPIO[2] VGPIO[3] VGPIO[4] VGPIO[5] VGPIO[6] VGPIO[7] VGPIO[8] VGPIO[9] VGPIO[10] VGPIO[11] VGPIO[12] VGPIO[13] VGPIO[14] VGPIO[15] VGPIO[16] VGPIO[17] VGPIO[18] VDCK VGPIO[19] VHSYNC VDVALID VVSYNC VSPOL VSREV VSLD VGOEV VDRVPDN VGPIO[20] VGPIO[21] VGPIO[22] VGPIO[23] VGPIO[24] VGPIO[25] VGPIO[26] VGPIO[27] Pin Name VD0 VD1 Alt. Func. 1 CCIR-656 YC[0] YC[1] YC[2] YC[3] YC[4] YC[5] YC[6] YC[7] VCCIR_C[0] VCCIR_C[1] VCCIR_C[2] VCCIR_C[3] VCCIR_C[4] VCCIR_C[5] VCCIR_C[6] VCCIR_C[7] VY[0] VY[1] VY[2] VY[3] VY[4] VY[5] VY[6] VY[7] VCb[0] VCb[1] VCb[2] VCb[3] VCb[4] VCb[5] VCb[6] VCb[7] VCr[0] VCr[1] VCr[2] VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7 VG0 VG1 VG2 VG3 VG4 VG5 VG6 VG7 VB0 VB1 VB2 R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 GPOL IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VDCK (27 MHz …) VDCK VDCK VPXCK SCKH IO VHSYNC VDVALID VVSYNC VHSYNC VDVALID VVSYNC VHSYNC VDVALID VVSYNC VCr[3] VCr[4] VCr[5] VCr[6] VCr[7] DVHSYNC DVDVALID DVVSYNC VB3 VB4 VB5 VB6 VB7 SSTH GSTV GCKV SPOL SREV SLD GOEV PWRDN IO IO IO IO IO IO IO IO YC[0] YC[1] YC[2] YC[3] YC[4] YC[5] YC[6] YC[7] Pin Number I/O Definition O CCIR656/CCIR601 Data Bus Bit 0 VY[0] O YCbCr Data Bus Y Bit 0 VR0 O RGB 24bit Data Bus Bit 0 R0 O TCON Data Bus R Bit 0 VGPIO[0] I/O General purpose I/O 0 Shared with Video Output pin YC[0] YC[1] 162 O CCIR656/CCIR601 Data Bus Bit 1 VY[1] O YCbCr Data Bus Y Bit 1 VR1 O RGB 24bit Data Bus Bit 1 R1 O TCON Data Bus R Bit 1 I/O General purpose I/O 1 Shared with Video Output pin O CCIR656/CCIR601 Data Bus Bit 2 VY[2] O YCbCr Data Bus Y Bit 2 VR2 O RGB 24bit Data Bus Bit 2 R2 O TCON Data Bus R Bit 2 I/O General purpose I/O 2 Shared with Video Output pin O CCIR656/CCIR601 Data Bus Bit 3 VY[3] O YCbCr Data Bus Y Bit 3 VR3 O RGB 24bit Data Bus Bit 3 R3 O TCON Data Bus R Bit 3 163 YC[2] 164 VGPIO[2] VD3 Type Alt. Func. 3 RGB 24bit VGPIO[1] VD2 CCIR-601 Alt. Func. 2 (TCON + RGB-666) YCbCr 24bit YC[3] 165 Magic Pixel Confidential - 23 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet VGPIO[3] VD4 YC[4] VD6 O CCIR656/CCIR601 Data Bus Bit 4 O YCbCr Data Bus Y Bit 4 VR4 O RGB 24bit Data Bus Bit 4 R4 O TCON Data Bus R Bit 4 I/O General purpose I/O 4 Shared with Video Output pin O CCIR656/CCIR601 Data Bus Bit 5 VY[5] O YCbCr Data Bus Y Bit 5 VR5 O RGB 24bit Data Bus Bit 5 R5 O TCON Data Bus R Bit 5 VGPIO[5] I/O General purpose I/O 5 Shared with Video Output pin 166 YC[5] YC[6] 167 O CCIR656/CCIR601 Data Bus Bit 6 VY[6] O YCbCr Data Bus Y Bit 6 VR6 O RGB 24bit Data Bus R Bit 6 G0 O TCON Data Bus G Bit 0 I/O General purpose I/O 6 Shared with Video Output pin O CCIR656/CCIR601 Data Bus Bit 7 VY[7] O YCbCr Data Bus Y Bit 7 VR7 O RGB 24bit Data Bus R Bit 7 G1 O TCON Data Bus G Bit 1 I/O General purpose I/O 7 Shared with Video Output pin O CCIR601 Data Bus Bit 8 VCb[0] O YCbCr data bus Cb bit 0 VG0 O RGB 24bit data bus G bit 0 G2 O TCON Data Bus G Bit 2 VGPIO[8] I/O General purpose I/O 8 Shared with Video Output pin 168 VGPIO[6] VD7 YC[7] 169 VGPIO[7] VD8 VD9 VCCIR_C[0] VCCIR_C[1] 170 O CCIR601 Data Bus Bit 9 VCb[1] O YCbCr data bus Cb bit 1 VG1 O RGB 24bit data bus G bit 1 G3 O TCON Data Bus G Bit 3 I/O General purpose I/O 9 Shared with Video Output pin O CCIR601 Data Bus Bit 10 VCb[2] O YCbCr data bus Cb bit 2 VG2 O RGB 24bit data bus G bit 2 G4 O TCON Data Bus G Bit 4 VGPIO[10] I/O General purpose I/O 10 Shared with Video Output pin O CCIR601 Data Bus Bit 11 VCb[3] O YCbCr data bus Cb bit 3 VG3 O RGB 24bit data bus G bit 3 G5 O TCON Data Bus G Bit 5 VGPIO[11] I/O General purpose I/O 11 Shared with Video Output pin 171 VGPIO[9] VD10 VD11 VD12 General purpose I/O 3 Shared with Video Output pin VY[4] VGPIO[4] VD5 I/O VCCIR_C[2] VCCIR_C[3] VCCIR_C[4] 172 21 O CCIR601 Data Bus Bit 12 VCb[4] O YCbCr data bus Cb bit 4 VG4 O RGB 24bit data bus G bit 4 B0 O TCON Data Bus B Bit 0 VGPIO[12] I/O General purpose I/O 12 Shared with Video Output pin 22 Magic Pixel Confidential - 24 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet VD13 VD14 VCCIR_C[5] O CCIR601 Data Bus Bit 13 VCb[5] O YCbCr data bus Cb bit 5 VG5 O RGB 24bit data bus G bit 5 B1 O TCON Data Bus B Bit 1 VGPIO[13] I/O General purpose I/O 13 Shared with Video Output pin VCCIR_C[6] 23 O CCIR601 Data Bus Bit 14 VCb[6] O YCbCr data bus Cb bit 6 VG6 O RGB 24bit data bus G bit 6 B2 O TCON Data Bus B Bit 2 I/O General purpose I/O 14 Shared with Video Output pin O CCIR601 Data Bus Bit 15 VCb[7] O YCbCr data bus Cb bit 7 VG7 O RGB 24bit data bus G bit 7 B3 O TCON Data Bus B Bit 3 VGPIO[15] I/O General purpose I/O 15 Shared with Video Output pin 24 VGPIO[14] VD15 VD16 VCCIR_C[7] VCr[0] 25 O YCbCr data bus Cr bit 0 VB0 O RGB 24bit data bus B bit 0 B4 O TCON Data Bus B Bit 4 I/O General purpose I/O 16 Shared with Video Output pin O YCbCr data bus Cr bit 1 VB1 O RGB 24bit data bus B bit 1 B5 O TCON Data Bus B Bit 5 I/O General purpose I/O 17 Shared with Video Output pin O YCbCr data bus Cr bit 2 VB2 O RGB 24bit data bus B bit 2 GPOL O TCON Gate Driver Polarity Select I/O General purpose I/O 18 Shared with Video Output pin O CCIR656/CCIR601 CLOCK VDCK O YCbCr CLOCK VPXCK O RGB 24bit CLOCK SCKH O TCON CLOCK VGPIO[19] I/O General purpose I/O 19 Shared with Video Output pin 26 VGPIO[16] VD17 VCr[1] 27 VGPIO[17] VD18 VCr[2] 28 VGPIO[18] VDCK VHSYNC VDVALID VDCK VHSYNC 139 O CCIR656/CCIR601 VHSYNC VHSYNC O YCbCr VHSYNC DVHSYNC O RGB 24bit VHSYNC SSTH O Horizontal Start Pulse Input VGPIO[20] I/O General purpose I/O 20 Shared with Video Output pin VDVALID 173 O CCIR656/CCIR601 VDVALID VDVALID O YCbCr VDVALID DVDVALID O RGB 24bit VDVALID GSTV O TCON Gate driver Start Pulse I/O General purpose I/O 21 Shared with Video Output pin O CCIR656/CCIR601 VVSYNC VVSYNC O YCbCr VVSYNC DVVSYNC O RGB 24bit VVSYNC GCKV O TCON Gate Driver Shift Clock 174 VGPIO[21] VVSYNC VVSYNC 175 Magic Pixel Confidential - 25 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet VGPIO[22] VSPOL I/O General purpose I/O 22 Shared with Video Output pin O YCbCr data bus Cr bit 3 O RGB 24bit data bus B bit 3 SPOL O TCON Source Driver Polarity Select VGPIO[23] I/O General purpose I/O 23 Shared with Video Output pin O YCbCr data bus Cr bit 4 O RGB 24bit data bus B bit 4 SREV O TCON Source Driver Data Reverse Control VGPIO[24] I/O General purpose I/O 24 Shared with Video Output pin O YCbCr data bus Cr bit 5 O RGB 24bit data bus B bit 5 SLD O TCON Source Driver Latch Pulse and Output Enable VGPIO[25] I/O General purpose I/O 25 Shared with Video Output pin O YCbCr data bus Cr bit 6 O RGB 24bit data bus B bit 6 GOEV O TCON Gate Driver Output Disable VGPIO[26] I/O General purpose I/O 26 Shared with Video Output pin O YCbCr data bus Cr bit 7 VB7 O RGB 24bit data bus B bit 7 PWRDN O TCON Power Down Timing VGPIO[27] I/O General purpose I/O 27 Shared with Video Output pin VCr[3] 150 VB3 VSREV VCr[4] 151 VB4 VSLD VCr[5] 152 VB5 VGOEV VCr[6] 153 VB6 VDRVPDN VCr[7] 154 7. LCD Driver (DTD)(6) Pin Name SROUT0 (VGH) B12_0 SROUT1 (VGL) B12_1 SROUT2 (LED) B12_2 Pin Name Default Type O AI O AI O AI Pin Number I/O Definition SOUT0 SOUT0 40 O VGH SOUT1 SOUT1 41 O VGL SOUT2 SOUT2 42 O LED B12_0 B12_0 50 AI B12_1 B12_1 51 AI B12_2 B12_2 52 AI Magic Pixel Confidential - 26 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 8. Audio DAC Analog Interface (14) Pin Name ASPKLP ASPKLN ASPKRP ASPKRN ASPKEQ1 ASPKEQ2 ASPKEQ3 ASPKEQ4 ASPKEQ5 ASPKEQ6 AHPL AHPR AVCOM EXTRC Default ASPKLP ASPKLN ASPKRP ASPKRN ASPKEQ1 ASPKEQ2 ASPKEQ3 ASPKEQ4 ASPKEQ5 ASPKEQ6 AHPL AHPR AVCOM EXTRC Pin Name Type A A A A A A A A A A A A A A Pin Number I/O 77 I/O Definition Non-inverting L speaker-driver output. The maximum signal ASPKLP ASPKLP swing = 3.2 volt. peak-to-peak for 8 Ohm load between ASPKLP and ASPKLN. Inverting L speaker-driver output. The maximum signal ASPKLN ASPKLN 78 I/O swing = 3.2 volt. peak-to-peak for 8 Ohm load between ASPKLP and ASPKLN. Non-inverting R speaker-driver output. The maximum signal ASPKRP ASPKRP 73 I/O swing = 3.2 volt. peak-to-peak for 8 Ohm load between ASPKRP and ASPKRN. Inverting R speaker-driver output. The maximum signal ASPKRN ASPKRN 74 I/O ASPKEQ1 ASPKEQ1 67 I/O ASPKEQ2 ASPKEQ2 Equalizer pin 1. 68 I/O Equalizer pin 2. ASPKEQ3 ASPKEQ3 69 I/O Equalizer pin 3. ASPKEQ4 ASPKEQ4 66 I/O Equalizer pin 4. ASPKEQ5 ASPKEQ5 65 I/O Equalizer pin 5. ASPKEQ6 ASPKEQ6 64 I/O Equalizer pin 6. AHPL AHPL 58 I/O AHPR AHPR 57 I/O AVCOM AVCOM 56 I/O EXTRC EXTRC 63 I/O swing = 3.2 volt. peak-to-peak for 8 Ohm load between ASPKRP and ASPKRN. Headphone L channel output, the maximum signal swing is 1.6 volt. peak-to-peak for 32 Ohm load. Headphone R channel output, the maximum signal swing is 1.6 volt. peak-to-peak for 32 Ohm load. Analog reference voltage. The voltage is about half of the voltage of AVDD. External RC Magic Pixel Confidential - 27 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 9. GPIO Interface (8) Pin Name Default GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Pin Name GPIO0 Alt. Func. 1 GPIO0 GPIO1 GPIO2/IRDIN GPIO3 GPIO4 GPIO5 GPIO6/SSCKI GPIO7 IRDIN is the IR data input SSCKI and SSDQ are for I2C slave SSDQ Default Pin Number I/O GPIO0 141 I/O Dedicated General purpose I/O 0 O I2C interface clock pin (Master mode) I/O Dedicated General purpose I/O 1 O I2C interface data pin (Master mode) I/O Dedicated General purpose I/O 2 GPIO1 142 GPIO2 143 IRDIN GPIO3 Type PWMQ3 SMDQ GPIO2 Alt.Func. 3 SMCKO and SMDQ are for I2C master SMCKO GPIO1 Alt. Func. 2 SMCKO SMDQ GPIO3 I 144 PWMQ3 Definition Infra Red signal data input I/O Dedicated General purpose I/O 3 O Pulse width Modulated Output 3 GPIO4 GPIO4 145 I/O Dedicated General purpose I/O 4 GPIO5 GPIO5 146 I/O Dedicated General purpose I/O 5 GPIO6 GPIO6 147 I/O Dedicated General purpose I/O 6 I/O I2C interface clock pin (Slave mode) I/O Dedicated General purpose I/O 7 I/O I2C interface data pin (Slave mode) I/O Definition SSCKI GPIO7 GPIO7 148 SSDQ 10. RTC Interface (3) Pin Name RXIN RXOUT RALARM Default RXIN RXOUT RALARM Pin Name Type I O O Pin Number RXIN RXIN 45 I RTC clock input RXOUT RXOUT 46 O RTC clock output RALARM RALARM 47 O RTC alarm Magic Pixel Confidential - 28 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 11. Miscellaneous (4) Pin Name RESETx CLKIN CLKOUT TESTMD Default RESETx CLKIN CLKOUT TESTMD Pin Name Type I I O I Pin Number I/O Definition RESETx RESETx 38 I Chip master reset, active low CLKIN CLKIN 180 I Master OSC input, 13.5MHz typically CLKOUT CLKOUT 179 O Master OSC output, 13.5MHz typically TESTMD TESTMD 39 I Test mode; tie to ground in normal function 12. Power / Ground (74) Pin Name Pin Number I/O Definition VPP_M1 12 SDRAM/DDR SDRAM I/O supply voltage, 3.3V/2.5V GND_M1 13 SDRAM/DDR SDRAM ground pin GND1 20 Ground pin VPP1 29 General I/O supply voltage, 3.3V VDD1 30 General core supply voltage, 1.8V GND2 31 Ground pin RVPP 43 RTC I/O supply voltage, 1.8V RVDD 44 RTC core supply voltage, 1.8V GND3 48 Ground pin DTD_PVPP 49 PWM I/O supply voltage, 3.3V VDD_AUD1 53 Audio core supply voltage, 1.8V GNDA_A3 54 Audio ground pin VPPA_A3 55 Audio power supply volatge, 3.3V GNDA_A2 59 Audio ground pin VPPA_A2 60 Audio power supply volatge, 3.3V VPPA_A1 61 Audio power supply volatge, 3.3V GNDA_A1 62 Audio ground pin GND_AUD 70 Audio ground pin VDD_AUD2 71 Audio core supply voltage, 1.8V VPPA_SPKR 72 Speaker R-channel supply voltage, 3.75V GNDA_SPKR 75 Speaker R-channel ground pin VPPA_SPKL 76 Speaker L-channel supply voltage, 3.75V GNDA_SPKL 79 Speaker L-channel ground pin VPP2 88 General I/O supply voltage, 3.3V GND4 90 Ground pin VDD2 92 General core supply voltage, 1.8V VPP3 108 General I/O supply voltage, 3.3V Magic Pixel Confidential - 29 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet GND5_1 109 Ground pin GND5_2 110 Ground pin VDD3 111 General core supply voltage, 1.8V USBD_VSDL 117 USB-device digital ground pin USBD_VDDL 118 USB-device digital power supply voltage, 1.8V USBD_VSSA 121 USB-device analog ground pin USBD_VPPA 122 USB-device analog power supply voltage, 3.3V USBOTG_VPPA 127 USB-OTG analog power supply voltage, 3.3V USBOTG_VSSA 128 USB-OTG analog ground pin USBOTG_VDDL 132 USB-OTG digital power supply voltage, 1.8V USBOTG_VSDL 133 USB-OTG digital ground pin GND_DUMMY 134 Ground pin GND6 138 Ground pin VDD4 140 General core supply voltage, 1.8V VPP4 149 General I/O supply voltage, 3.3V RGB_AGNDR 156 RGB-DAC ground pin RGB_AVPP3 159 RGB-DAC power supply voltage, 3.3V GND7 160 Ground pin VPP5 176 General I/O supply voltage, 3.3V VDD5 178 General core supply voltage, 1.8V GNDA_P123 181 PLL1, PLL2 & PLL3 ground pin VDDA_P123 182 PLL1, PLL2 & PLL3 power supply voltage, 1.8V VPP_M2 189 SDRAM/DDR SDRAM I/O supply voltage, 3.3V/2.5V GND_M2 198 SDRAM/DDR SDRAM ground pin VPP_M3 206 SDRAM/DDR SDRAM I/O supply voltage, 3.3V/2.5V GND8 213 Ground pin VDD6 215 General core supply voltage, 1.8V VPP_M4 216 SDRAM/DDR SDRAM I/O supply voltage, 3.3V/2.5V GND_M3 2 SDRAM/DDR SDRAM ground pin NC 155, 157, 158, No connection 161 Magic Pixel Confidential - 30 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Symbol VPP VPPA Vin5 Vin TSTG Parameter I/O supply Voltage (VPP1~4, VPPM1~3, UHVPP) Audio I/O supply Voltage (VPPA_A1, VPPA_HP, VPPA_SPKR, VPPA_SPKL) Core supply Voltage (VDD1~6, VDDA_P12, VDDA_P3, RVPP, RVDD) DC Input Voltage for 5V-tolerant I/O 2 DC Input Voltage for non-5V-tolerant I/O Storage Temperature ESD ESD Rating (Rzap = 1.5K Ω, Czap = 100pf) VDD Value -1.0 to 4.6 -0.5 to 4.5 Units V V -1.0 to 4.6 V -1.0 to 5.5 -1.0 to 4.6 -40 to 125 V V °C TBD V Note: 1. Permanent device damage may occurs if the specification for the Absolute Maximum Ratings are exceeded. 2. 5V tolerant I/O including HURX, HUTX, GPIO[7:0]. 3. All voltages are defined with respect to ground. 7.2 Recommended Operating Conditions Symbol VPP VPPA VDD TA Parameter I/O supply Voltage (VPP1~4, VPPM1~3, UHVPP) Audio I/O supply Voltage (VPPA_A1, VPPA_HP, VPPA_SPKR, VPPA_SPKL) Core supply Voltage (VDD1~6, VDDA_P12, VDDA_P3, RVPP, RVDD) Ambient Operating Temperature Min. 3.1 2.7 Typ. 3.3 3.6 Max. 3.6 4.2 Units V V 1.68 1.8 1.98 V 0 - 70 °C 7.3 DC Characteristics Symbol VIL VIH VIL –SCH 1 Parameter Input Low Voltage Input High Voltage Schmitt-triggered Input Low Voltage 1 Schmitt trig. Input High VIH –SCH Voltage Output Low Voltage VOL Output High Voltage VOH Rd 2 Ii Ioz Pull Down Resistance Input Leakage Current Tri-state Output Leakage Current Condition TTL TTL Schmitt Trig. TTL Min Schmitt Trig. TTL 1.9 4mA load 4mA load Typ Max 0.8 2.2 0.9 V 0.4 V V 215 1µA 1µA KΩ 0.8*VPP Vo = 3.3V or 0V Vo = 3.3V or 0V 91 - Units V V V 120 10nA 10nA Note: 1. The I/O with Schmitt-trigger: TESTMD, RESETx and GP[1:0]. Magic Pixel Confidential - 31 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 2. The I/O with pull-down: TESTMD. 7.4 Capacitance Symbol CXIN CIN CBI Parameter Clock Input, CLKIN, capacitance Input pin capacitance Bidirectional pin capacitance Min. Typ. 7 5 5 Max. Units pF pF pF CBI5 Bidirectional pin capacitance for 5V-tolerant I/O 7 pF COUT Output pin capacitance 5 pF 7.5 AC Characteristics 7.5.1 Reset Timing TRSTW Fig. 7-1 Reset Timing Symbol TRSTW Parameter Reset Pulse Width Min. 1 Typ. Max. Unit ms Typ. 13.5 74 Max. Unit MHZ ns ns ns % 7.5.2 Input Clock Fig. 7-2 CLKIN AC Characteristic TCLKIN_P CLKIN TCLKIN_L Symbol FCLKIN TCLKIN_P TCLKIN_L TCLKIN_H DTCLKIN TCLKIN_H Parameter CLKIN Master Clock Input Frequency CLKIN Master Clock Input Period CLKIN Master Clock Input Low Width CLKIN Master Clock Input High Width CLKIN Duty Cycle Magic Pixel Confidential - 32 - Min. 33.3 33.3 45 40.7 40.7 55 Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 7.5.3 SDRAM Interface Timing TSDCK_P TSDCK_L MSDCK TMDI_HLD TMDI_SU TSDCK_H MD (CAS Latency 2) R0 MDQM (CAS Latency 2) MD (CAS Latency 3) MDQM (CAS Latency 2) MRASx, MCASx, MWEx, MSDCSx TMDO_D R1 R2 R3 R0 R1 R2 W0 W1 W2 W3 R3 W0 W1 W2 W3 ACTB WRB TSDCMD_D ACTA RDA PRE PRE TMA_D MA ROW ADR 0 COL ADR n ROW ADR COL ADR 0 TMA_D MBA BANK A BANK B Fig. 7-3 Basic SDRAM Interface Timing Symbol TSDCK_P TSDCK_H TSDCK_L TMDI_SU TMDI_HLD TMA_D TMDO_D TSDCMD_D Parameter SDRAM Clock Output Period SDRAM Clock Output High Pulse Width SDRAM Clock Output Low Pulse Width SDRAM Data Input Setup Time SDRAM Data Input Hold Time SDRAM Address Valid Delay SDRAM Data Output Valid Delay SDRAM Command Valid Delay Min. 13.9 4.6 4.6 TBD TBD Typ. Max. TBD TBD TBD Unit ns ns ns ns ns ns ns ns 7.5.4 Display Output Clock signal (VDCK) Horizontal sync. signal (VHSYNC) Ths Thbp Thdis Thfp Data enable signal (VDVALID) Data signal (VD0 - VD7) Horizontal data invalid period D1 D2 Dn-1 Dn Horizontal data invalid period Fig. 7-4 Display/CCIR-601 Output Horizontal Timing Magic Pixel Confidential - 33 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Horizontal sync. signal (VHSYNC) Vertical sync. signal (VVSYNC) Tvs Data signal (VD0 - VD7) Tvbp Vertical data invalid period Tvdis DH1 DH2 Tvfp Vertical data invalid period DHm-1 DHm Fig. 7-5 Progressive Display Output Vertical Timing Horizontal sync. signal (VHSYNC) Vertical sync. signal (VVSYNC) Tvs1 Data signal (VD0 - VD7) Tvbp Vertical data invalid period Tvdis DH1 DH2 Tvfp DHm-1 DHm Tvs2 Vertical data invalid period Fig. 7-6 Progressive Display Output Vertical Timing Clock signal (VGCP=2x pixel clock) Horizontal sync. signal (VHSYNC) Thfp Thdis Thbp Ths Data enable signal (VDVALID) Data signal (VD0 - VD7) 10 80 10 SAV D1 D2 Dn-1 Dn EAV 80 10 Fig. 7-7 CCIR-656 Output Horizontal Timing Magic Pixel Confidential - 34 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet TH TC Output Clock (VDCK, VGCP) TL Data signal (VD0-VD7) TOD Fig. 7-8 Display Output Clock, and Data Sample Timing Symbol Parameter TC TH TL TOD Min. Typ. Max. Unit Ths Horizontal Sync. Pulse Width 1 256 VDCK Thbp Display Horizontal Back Porch Width 1 256 VDCK Thdis Horizontal Display Enable Width 1 2048 VDCK Thfp Display Horizontal Front Porch Width 1 256 VDCK Tvs Vertical Sync. Pulse Width 1 256 line Tvbp Tvdis Display Vertical Back Porch Width Vertical Display Enable Width 1 1 256 2048 line line Tvfp Display Vertical Back Porch Width 1 256 line VDCK VDCK Clock Cycle Time 65 ns VGCP VGCP (2x of VDCK) Clock Cycle Time 33 ns VDCK VDCK Clock High Pulse Width 20 ns VGCP VGCP (2x of VDCK) Clock High Pulse Width 11 ns VDCK VDCK Clock Low Pulse Width 20 ns VGCP VGCP (2x of VDCK) Clock Low Pulse Width 11 ns VDCK Display Data Output delay time relative to the rising edge of VDCK TBD ns VGCP Display Data Output delay time relative to the rising edge of VGCP TBD ns Magic Pixel Confidential - 35 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 7.6 Package Dimensions MP620DUCG-C Package Outline for LQFP 216 Pin ( 24mm x 24mm x 1.4mm, Pin Pitch = 0.4mm) Magic Pixel Confidential - 36 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Magic Pixel Confidential - 37 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Magic Pixel Confidential - 38 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet Magic Pixel Confidential - 39 - Revision 0.99 - 2009.03.06 iPlayTM MP620DUCG-C Datasheet 8 Revision History Date April. 11. 2008 Feb. 13. 2009 Revision 0.91 0.96 Feb. 18. 2009 0.97 Feb. 20. 2009 0.98 Mar. 6, 2009 0.99 Description Initial Version Modify USBD_VBUS pin-No. and add RVPP, RVDD power pins. Change JPEG decode speed from 48Mpixel/sec to 24Mpixel/sec. Modify the description for all power / ground pins. Page 16, change pin count number at corner to 216. Modify the pin number for all power / ground pins. Change MP620DUCG to MP620DUCG-C. Remove sec. 4.9 “Digital Audio Interface Unit”. It’s not supported. Magic Pixel Confidential - 40 - Revision 0.99 - 2009.03.06