AD AD53508JP

a
PPMU Circuit
AD53508
FEATURES
Dual Measurement Channels
Precision Four-Quadrant-Per-Pin V/I Source
Programmable Current Force Ranges
ⴞ204.8 ␮A and ⴞ2.048 mA
Five Current Measurement Ranges
204.8 nA to ⴞ2.048 mA
Output Voltage Range: –4 V to +9 V
Power Supplies: +15 V, +5 V, and –10 V
44-Lead Plastic J-Leaded Chip Carrier Package
The device provides a remote force/sense capability to ensure
accuracy at the tester pin. A guard output is available to drive
the shield of a force/sense pair.
APPLICATIONS
Can Be Used with the AD53032 DCL to Extend Current
Force Range to 35 mA
Recommended Use of the PPMU with AD53032 DCL
Two input references per channel permit controlled switching to
different voltage or current levels. The forced voltage or current
levels can be switched back to the measurement system to read
back the analog levels for system calibration.
The circuit is powered by +15 V, +5 V and –10 V supplies and
dissipates 230 mW nominally.
The PPMU can be used with the AD53032 DCL to extend the
Current Force Range beyond 2 mA VCOM can be set to the
maximum spec allowance of 8 V, which would allow the maximum Current Force of IOL of 35 mA. The combination of the
PPMU and the DCL would have a few benefits including:
GENERAL DESCRIPTION
The AD53508 is a custom dual-channel parametric measurement circuit for use in semiconductor automatic test equipment.
It contains programmable modes to force a pin voltage and
measure its current or to integrate and hold a current value.
Alternatively, a current can be forced and the compliance voltage measured.
1. Accurately measuring low currents.
2. Can take parallel measurements by using one PMU per pin.
FUNCTIONAL BLOCK DIAGRAM
S8
SENSE
AD53508
DAC1
DAC2
EXT RC
S6
S7
C1
S10
VF
IF
OUTPUT
S4
S5
S2
VM
S3
IM
INTEGRATE
R1
1k⍀
2mA
R2
INT/IM
S11
FORCE
S12
S13
1.25R
+2.5V
S1
40pF
MAIN
ENABLE
DSR
SENSE
S9
DIFF
R
10k⍀
200␮A
S14
S17
S15
S16
UNITY
MEAS OUT
CON
1.25R
R
GUARD
S18
GUARD
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD53508–SPECIFICATIONS (T = 25ⴗC, rated power supplies unless otherwise noted)
A
Parameter
Condition
VOLTAGE FORCE/MEASURE MODE
Voltage Swing, ± 2 mA Range
± 2 mA Drive
± 100 µA Drive
ACCURACY
Gain (± 0.1% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Current Measure CMRR (at MEAS_OUT)
Max
Unit1
–4
–5
+9
+12
V
V
0.999
1.001
± 15
± 0.02
± 0.31
V/V
mV
% of Span
mV/V
± 20
ppm (PV
or MV)/°C
µV/°C
Min
Typ
DRIFT
Gain Error Temperature Coefficient
± 100
Offset Drift
CURRENT FORCE/MEASURE MODE RANGES
0 (High)
1 (Low)
ACCURACY—HIGH RANGE
Transconductance (± 3% Tolerance)
Transresistance (± 3% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced
Transconductance/Error
± 2.0
± 200
Force Mode
Measure Mode
0.776
1.21
Force Mode
–0.2
0.8
1.25
DRIFT—HIGH RANGE
Gain Error Temperature Coefficient
Offset Drift
ACCURACY—LOW RANGE
Transconductance (± 3% Tolerance)
Transresistance (± 3% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced
Transconductance/Error
Force Mode
Measure Mode
77.6
12.1
Force Mode
–0.02
80
12.5
DRIFT—LOW RANGE
Gain Error Temperature Coefficient
mA
µA
0.824
1.29
± 40
± 0.05
mA/V
V/mA
µA
% of Span
+0.4
µA/V
+10/–60
± 400
ppm (PV
or MV)/°C
nA/°C
82.4
12.9
±4
± 0.05
µA/V
V/mA
µA
% of Span
+0.04
µA/V
+10/–60
ppm (PV
or MV)/°C
nA/°C
± 40
Offset Drift
CURRENT MEASURE INTEGRATE MODE RANGES
High
Medium
Low
± 20.0
± 2.0
± 200
ACCURACY—HIGH RANGE
Transresistance Error (± 3% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced Transresistance Error
0.121
0.125
DRIFT—HIGH RANGE
Gain Error Temperature Coefficient
Offset Drift
ACCURACY—MEDIUM RANGE
Transresistance Error (± 3% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced Transresistance Error
1.21
DRIFT— MEDIUM RANGE
Gain Error Temperature Coefficient
Offset Drift
–2–
1.25
µA
µA
nA
0.129
± 400
± 0.05
± 2.5
V/µA
nA
% of Span
nA/V of Output
± 20
±2
ppm MV/°C
nA/°C
1.29
± 40
± 0.05
± 0.25
V/µA
nA
% of Span
nA/V of Output
± 20
± 250
ppm MV/°C
pA/°C
REV. 0
AD53508
Parameter
Condition
ACCURACY—LOW RANGE
Transresistance Error (± 3% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced Transresistance Error
Min
Typ
Max
Unit1
0.0121
0.0125
0.0129
±4
± 0.05
± 0.025
V/nA
nA
% of Span
nA/V of Output
± 20
± 70
ppm MV/°C
pA/°C
–4
–5
+9
+12
V
V
0.999
1.001
± 15
± 0.02
± 0.31
V/V
mV
% of Span
mV/V
± 20
ppm (PV or
MV)/°C
µV/°C
DRIFT—LOW RANGE
Gain Error Temperature Coefficient
Offset Drift
DISABLE MODE2
Voltage Swing, ± 2 mA Range
± 2 mA Drive
± 100 µA Drive
ACCURACY
Gain (± 0.1% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Current Measure CMRR (at MEAS_OUT)
DRIFT
Gain Error Temperature Coefficient
± 100
Offset Drift
OTHER SPECIFICATIONS
Power Supply Rejection Ratio
CURRENT MEASURE HOLD MODE LEAKAGE
CROSSTALK
f < 40 Hz, VCC
f < 40 Hz, VEE
f = 40 kHz, VCC
f = 40 kHz, VEE
70
60
35
25
dB
dB
dB
dB
TAMB = +70°C
3
SETTLING TIMES TO 0.01%
Voltage Force and Guard Voltage
Current Force (200 µA Range)
MEAS_OUT Pin
SHORT CIRCUIT CURRENT LIMIT MAGNITUDE
CLOAD = 100 pF
CLOAD = 2000 pF
ZLOAD = 100 pF储50 kΩ
CLOAD = 20 pF
Any Output Except Guards
± 1.2
nA
± 0.02
% of Span
20
2
50
2
µs
ms
µs
µs
8.5
20
mA
GUARD SCC LIMIT MAGNITUDE
2.5
10
mA
GUARD OFFSET (FROM SENSE INPUT PIN)
–65
0
mV
± 1.0
µA
0.8
10
V
V
µA
15.75
–9.0
5.25
15
–5
V
V
V
mA
mA
8
mA
–25
IB (DAC1, DAC2) CURRENT
DIGITAL INPUTS
VIH
VIL
IIN (Input leakage current)
2.4
POWER SUPPLIES
VCC (Positive Analog Supply Voltage)
VEE (Negative Analog Supply Voltage)
VDD (Logic Supply Voltage)
ICC (Positive Analog Supply Current)
IEE (Negative Analog Supply Current)
IDD (Logic Supply Current Is 0 with Inputs at Rails,
Worst Case @ 2.4 V IN)
14.0
–10.5
4.75
5
–15
NOTES
1
PV = Programmed Value, MV = Measured Value, FSR = Full-Scale Range = span.
Output connected: DAC2 and 2 mA range selected, unconditionally.
3
f < 40 Hz, both channels in current force mode; other channel output voltage swinging rail to rail.
2
Specifications subject to change without notice.
REV. 0
–3–
15.0
–10.0
5.0
AD53508
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
(TA = 25°C unless otherwise noted)
VDD to VEE
VCC to VEE
VDD to DGND
Digital Inputs to DGND
Power Dissipation
Operating Temperature
Range
Storage Temperature
Lead Temperature
Force/Sense Outputs
Min
Max
Unit
Condition
–0.3
–0.3
–0.3
–0.3
+26.4
+26.4
+6
VCC+0.3
700
V
V
V
V
mW
TA ≤ +75°C
25
–60
70
+125
+300
VEE–0.8 VCC+0.8
°C
°C
°C
V
Soldering (10 sec)
Or 75 mA,
Whichever Is Less
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD53508JP
25°C to 70°C
Plastic Leaded
Chip Carrier
P-44A
C1 A
EXT RC A
DAC1 A
DAC2 A
DSR 2.5
DAC2 B
DAC1 B
6
5
2
44 43 42 41 40
4
3
1
R1 B
R1 A
EXT RC B
C1 B
PIN CONFIGURATION
PIN 1
IDENTIFIER
R2 A 7
SENSE A 8
39
38
R2 B
SENSE B
FORCE A 9
37
GUARD A 10
MEAS OUT A 11
36
FORCE B
GUARD B
AD53508
35
MEAS OUT B
TOP VIEW
(Not to Scale)
34
VCC 12
M CON A* 13
VEE 14
VDD
33 M CON B*
32 DIGGND
FORCE I A* 15
31
FORCE EN A* 16
DAC1 SEL A* 17
30
FORCE I B*
FORCE EN B*
29
DAC1 SEL B*
INTEG B*
I RANGE0 B*
HOLD B*
I RANGE1 B*
OUTPUT CON B*
VERIFY*
OUTPUT CON A*
I RANGE1 A*
HOLD A*
I RANGE0 A*
INTEG A*
18 19 20 21 22 23 24 25 26 27 28
* = ACTIVE LO
Pin Name
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
2.5 V Reference Input
First of Two Switchable Inputs
Second of Two Switchable Inputs
External RS and C Common
External Capacitor
External Resistor
External Resistor
Sense Input
Force Output
Guard Drive Output
Measurement Output
+15 V Analog Supply
Connect Measure Output to Bus
–10 V Analog Supply
Force V (When Hi) or I (When Lo)
Control Input
Select DAC1 (When Lo) or DAC2
Control Input
Control Input
Select 2 mA Range (Active Lo)
Select 200 µA Range (Active Lo)
Measure Forced Voltage or Current
Connect Pin Drive (Active Lo)
Connect Pin Drive (Active Lo)
Select 200 µA Range (Active Lo)
Select 2 mA Range (Active Lo)
Control Input
Control Input
Select DAC1 (When Lo) or DAC2
Control Input
Force V (When Hi) or I (When Lo)
Digital Ground
Connect Measure Output to Bus
+5 V Digital Supply
Measurement Output
Guard Drive Output
Force Output
Sense Input
External Resistor
External Resistor
External Capacitor
External RS and C Common
Second of Two Switchable Inputs
First of Two Switchable Inputs
DSR_2.5
DAC2_A
DAC1_A
EXT_RC_A
C1_A
R1_A
R2_A
SENSE_A
FORCE_A
GUARD_A
MEAS_OUT_A
VCC
M_CON_A*
VEE
FORCE_I_A*
FORCE_EN_A*
DAC1_SEL_A*
INTEG_A*
HOLD_A*
I_RANGE0_A*
I_RANGE1_A*
VERIFY*
OUTPUT_CON_A*
OUTPUT_CON_B*
I_RANGE1_B*
I_RANGE0_B*
HOLD_B*
INTEG_B*
DAC1_SEL_B*
FORCE_EN_B*
FORCE_I_B*
DIGGND
M_CON_B*
VDD
MEAS_OUT_B
GUARD_B
FORCE_B
SENSE_B
R2_B
R1_B
C1_B
EXT_RC_B
DAC1_B
DAC2_B
* = Active Lo
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53508 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD53508
Table I. Data Table
Data Latch Bits
S1
S2
S3
S4
Voltage Force/Current Measure
Irange 0
On
Off
On
On
Irange 1
On
Off
On
On
Integrate Range
On
Off
On
On
Integrate
On
Off
On
On
Hold/Measure
On
Off
On
On
Current Force/Voltage Measure
Irange 0
On
On
Off
Off
Irange 1
On
On
Off
Off
S5
S6
S7
S9
S17
S8
S13,
S10
S15,
S14
S16
S11
S12
S18
Off
On
Off
Off
Off
On
On
On
Off
Off
Off
On
Off
On
Off
Off
Off
On
On
Off
On
Off
Off
On
Off
On
Off
Off
Off
On
On
Off
Off
On
On
On
Off
On
Off
Off
Off
On
Off
Off
Off
On
On
On
Off
On
Off
On
On
Off
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
On
Off
On
Off
Off
On
Disable Mode: Output Connected
X
X
X
On
Off
Off
On
Off
Off
On
X
On
Off
Off
Off
On
Verify/Voltage Force
On
On
Off
On
Off
On
Off
Off
Off
On
On
On
Off
Off
Off
On
Verify/Current Force
On
Off
On
Off
On
On
Off
Off
Off
On
On
On
Off
Off
Off
On
Disconnect
X
X
On
Off
X
X
On
Off
Off
On
Off
Off
Off
On
Off
X
X
Off
On
X
X
X
X
X
X
X
X
X
X
DAC2 Select: Enabled
X
X
X
CAPACITOR
CHARGE
INTEGRATE*
DISCHARGE
CAPACITOR
INTEGRATE
HOLD
HOLD*
* = ACTIVE LO
Figure 1. Integrate/Current Measure Timing Diagram
Table II. Truth Table
* = Active LO
FV/MI 2 mA
FV/MI 200 mA
Control
FV/MI Integrate DAC1
FV/MI Integrate DAC 2
Voltage
Inte-
Voltage
Inte-
FI/MV 2 mA
FI/MV 200 µA
FV/Verify
FI/Verify
Disconnect
Disable
Output
Input
DAC1
DAC2
DAC1
DAC2
Settle
grate
Hold
Settle
grate
Hold
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
M_CON*
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
Connected
X
X
VERIFY*
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
LO
X
X
FORCE_I*
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
LO
HI
HI
LO
LO
X
X
FORCE_EN*
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
X
HI
DAC1_SEL*
LO
HI
LO
HI
LO
LO
LO
HI
HI
HI
LO
HI
LO
HI
LO
HI
LO
HI
X
X
INTEG*
HI
HI
HI
HI
HI
LO
LO
HI
LO
LO
HI
HI
HI
HI
HI
HI
HI
HI
X
X
HOLD*
HI
HI
HI
HI
HI
HI
LO
HI
HI
LO
HI
HI
HI
HI
HI
HI
HI
HI
X
X
I_RANGE0*
LO
LO
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
HI
HI
X
X
X
X
X
X
I_RANGE1*
HI
HI
LO
LO
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
X
X
X
X
X
X
OUTPUT_CON*
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
HI
LO
REV. 0
–5–
AD53508
4. Computations for F1 are:
F1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
F1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
F1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
PPMU APPLICATION NOTES
The PPMU can be used in two modes: 1. VOLTAGE FORCE
with CURRENT MEASURE or VERIFY CURRENT FORCE;
2. CURRENT FORCE with VOLTAGE MEASURE or
VERIFY VOLTAGE FORCE. In both modes the following
setup is recommended:
Where LOW = –Full Scale and HIGH = +Full Scale.
The linearity tests for measuring current are as follows (at the
MEAS_OUT pin):
1. The value of the external integrate capacitor (EXT_RC to
C1) is 10 nF.
1. The voltage is constant for these measurements.
2. MEAS_OUT pin is loaded with 1 MΩ to ground.
2. The four ranges (M1, M2, M3, M4) correspond to
CURRENT MEASURE ranges (200 nA, 20 µA, 200 µA,
and 2 mA respectively).
3. VCC = +15.0 V, VDD = +4.5 V, DIGGND = 0.0 V,
VEE = –10 V, DSR = 2.5 V unless otherwise stated.
4. A 10 Ω resistor in series with the FORCE pin.
5. A 1 kΩ resistor in series with the SENSE pin.
3. The endpoints of the linearity curve are determined by the
–full scale (or LOW), and the +full scale (or HIGH) readings at the same FORCE pin voltage.
IN VOLTAGE FORCE WITH CURRENT MEASURE OR
VERIFY CURRENT FORCE
4. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
To measure the leakage in the current measure and hold mode,
the PPMU has to be into the Force Voltage/Measure Current
Integrate mode.
5. Computations for M1 are:
M1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
M1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
M1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
1. The FORCE_A (Force Output) pin has to be programmed
to +9 V.
Where LOW = –Full Scale, and HIGH = +Full Scale.
2. The PPMU has to be programmed to INTEGRATE mode.
3. The PPMU has to be programmed to HOLD mode.
The M_CON pin can be used for disconnecting the MEAS_OUT
pin by:
4. Sample MEAS_OUT.
1. Raising M_CON to 2.4 V.
5. Wait 100 ms.
2. Measuring MEAS_OUT (which is loaded with 100 kΩ).
6. Sample MEAS_OUT again.
3. MEAS_OUT should ideally be 0 V.
7. The difference between 2 and 4 must be less than 15 mV.
The OUTPUT_CON pin can be used for disconnecting the
DUT by:
The linearity tests for forcing voltage are as follows (at the
FORCE pin):
1. Disabling the SENSE pin (OUTPUT_CON = 2.4 V).
2. Loading FORCE_OUT with 2 kΩ to ground.
1. The four ranges of CURRENT MEASURE ranges (200 nA,
20 µA, 200 µA, and 2 mA) correspond to F1, F2, F3, and F4.
3. Programming the DAC1 input to +FS (+9 V) and measuring
the FORCE_OUT voltage (FV1).
2. The endpoints of the linearity curve are determined by –full
scale (or LOW), and the +full scale (or HIGH) readings at
the same FORCE pin current.
4. Programming the DAC1 input to –FS (–4 V) and measuring the FORCE_OUT voltage (FV2).
3. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
DAC2
EXT RC
S6
40pF
MAIN
S7
C1
S10
VF
IF
S4
S5
INTEGRATE
R1
1k⍀
2mA
R2
OUTPUT
S2
VM
S3
IM
INT/IM
FORCE 10⍀
S11
S12
TO DUT
S13
1.25R
2.5V
S1
SENSE 1k⍀
S8
S9
ENABLE
DSR
6. A change of 1.3 mV implies a switch off-resistance of 20 MΩ.
SENSE
AD53508
FORCING
VOLTAGE
DAC1
5. FV1–FV2 < 1.3 mV.
DIFF
R
10k⍀
200␮A
S14
S17
S15
S16
UNITY
MEAS OUT
CON
1.25R
R
GUARD
S18
GUARD
Figure 2. Guarded Voltage Force/Current Measure, IRANGE 1: I ≤ 2 mA
–6–
REV. 0
AD53508
IN CURRENT FORCE WITH VOLTAGE MEASURE OR
VERIFY CURRENT FORCE
7. Measure voltage at MEAS_OUT and compare to 4.
The linearity tests for forcing current at the FORCE pin:
9. DAC1 = 0 V.
1. The FORCE pin is loaded with a voltage source.
10. FORCE pin loaded with –4 V source.
2. The two ranges of CURRENT FORCE ranges (2 mA and
200 µA) correspond to F1 and F2. The endpoints of the
linearity curve are determined by full scale (or LOW), and
the full scale (or HIGH) readings at the same FORCE pin
voltage.
11. Measure current at FORCE.
8. VCC = 15 V.
12. Measure voltage at MEAS_OUT.
13. VEE = –9.5 V.
14. Measure current at FORCE and compare to 11.
3. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
15. Measure voltage at MEAS_OUT and compare to 12.
16. VEE = –10 V.
4. Computations for F1 are:
F1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
F1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
F1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
VOLTAGE FORCE WITH CURRENT MEASURE
(2 mA RANGE)
1. DAC1 = 9 V.
Where LOW = –Full Scale and HIGH = +Full Scale.
2. FORCE pin loaded with 2 mA current source.
The linearity test for measuring voltage is as follows (at the
MEAS_OUT pin):
3. Measure voltage at FORCE.
1. The endpoints of the linearity curve are determined by the
–full scale (or LOW), and the +full scale (or HIGH) readings.
4. Measure current at MEAS_OUT.
2. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
6. Measure voltage at FORCE and compare to 3:
Limit = ± 237 µV.
3. Computations for M1 are:
M1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
M1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
M1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
7. Measure current at MEAS_OUT and compare to 4:
Limit = ± 237 µV.
5. VCC = 14.25 V.
8. VCC = 15 V.
9. DAC1 = –4 V.
Where LOW = –Full Scale, and HIGH = +Full Scale.
10. FORCE pin loaded with 2 mA current sink.
CURRENT FORCE WITH VOLTAGE MEASURE
(2 mA RANGE)
11. Measure voltage at FORCE.
12. Measure current at MEAS_OUT.
1. DAC1 = 5 V.
13. VEE = –9.5 V.
2. FORCE pin loaded with 9 V source.
3. Measure current at FORCE.
14. Measure voltage at FORCE and compare to 11:
Limit = ± 474 µV.
4. Measure voltage at MEAS_OUT.
15. Measure current at MEAS_OUT and compare to 12.
5. VCC = 15 V.
16. VEE = –10 V.
6. Measure current at FORCE and compare to 3.
FORCING
VOLTAGE
DAC1
DAC2
EXT RC
S6
40pF
MAIN
S7
C1
S10
VF
IF
S4
S5
OUTPUT
S2
VM
S3
IM
INTEGRATE
R1
1k⍀
2mA
R2
INT/IM
S11
FORCE
S12
S13
1.25R
2.5V
S1
SENSE
S9
ENABLE
DSR
S8
SENSE
AD53508
DIFF
R
10k⍀
200␮A
S14
S17
S15
S16
UNITY
MEAS OUT
CON
1.25R
R
GUARD
S18
GUARD
Figure 3. Guarded Current Force/Voltage Measure, IRANGE 1: I ≤ 2 mA
REV. 0
–7–
AD53508
1
51
52
34
39
40
41
32
VEE
VCC
39nF
CHDCPL
VH 47
VTERM 45
AD53032
DATA 38
25
50⍀
IOD 43
DRIVER
IOD 42
30
22
RLD 49
VHDCPL
39nF
CLDCPL
VOUT
TO DUT
VLDCPL
TO DUT (SENSE)
GUARD
RLD 50
VL 31
HCOMP 16
C3609–2.5–10/99
DATA 37
LEH 13
LEH 12
QH 7
QHB 6
COMPARATOR
QL 4
QL
"CONNECT TO HIGH QUALITY,
LOW NOISE SIGNAL (GND)"
3
LEL 11
LEL 10
LCOMP 17
ACTIVE LOAD
+1
VCOMI 25
24
VCOMS
23
IOL
DSR
V/I
FORCE
IOLRTN 22
*
IOHRTN 27
PPMU
INHL 36
26
IOH
INHL 35
15
THERM
14
NC
SENSE
DAC1
1.0␮A/K
IOHC 29
V/I
9, 33, 44, 46, 48
PWRGND
2, 5, 8
19
GUARD*
DAC2
28
MEAS_OUT
ECLGND HQGND2 HQGND
TO V/I DAC
(PER CHANNEL)
TO SYSTEM
VOLTMETER
FROM OTHER PMUs
Figure 4. Recommended Use of the PPMU with a DCL
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Leaded Chip Carrier (PLCC)
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
6
7
0.025 (0.63)
0.015 (0.38)
40
39
PIN 1
IDENTIFIER
0.050
(1.27) 0.63 (16.00)
BSC 0.59 (14.99)
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
17
0.032 (0.81)
0.026 (0.66)
29
28
18
0.020
(0.50)
R
PRINTED IN U.S.A.
IOLC 30
0.040 (1.01)
0.025 (0.64)
0.656 (16.66)
SQ
0.650 (16.51)
0.695 (17.65)
SQ
0.685 (17.40)
–8–
0.110 (2.79)
0.085 (2.16)
REV. 0