AD AD5522_08

Quad Parametric Measurement Unit with
Integrated 16-Bit Level Setting DACs
AD5522
FEATURES
APPLICATIONS
Quad parametric measurement unit (PMU)
FV, FI, FN (high-Z), MV, MI functions
4 programmable current ranges (internal RSENSE)
±5 μA, ±20 μA, ±200 μA, and ±2 mA
1 programmable current range up to ±80 mA (external RSENSE)
22.5 V FV range with asymmetrical operation
Integrated 16-bit DACs provide programmable levels
Gain and offset correction on chip
Low capacitance outputs suited to relayless systems
On-chip comparators per channel
FI voltage clamps and FV current clamps
Guard drive amplifier
System PMU connections
Programmable temperature shutdown
SPI- and LVDS-compatible interfaces
Compact 80-lead TQFP with exposed pad (top or bottom)
Automated test equipment (ATE)
Per-pin parametric measurement unit
Continuity and leakage testing
Device power supply
Instrumentation
Source measure unit (SMU)
Precision measurement
FUNCTIONAL BLOCK DIAGRAM
AVSS
AGND
VREF
REFGND
16
16
16
X1 REG
M REG
C REG
16
16
16
DGND
DVCC
AVDD
CCOMP[0:3]
×4
16-BIT
CLH DAC
16
X2 REG
SYS_FORCE SYS_SENSE
EN
CLH
OFFSET DAC
×6
–
16-BIT
16 FIN DAC
FIN
INTERNAL RANGE SELECT
(±5µA, ±20µA, ±200µA, ±2mA) 60Ω
SW1
+
AGND
X2 REG
FOH[0:3]
FORCE
AMPLIFIER
MEASVH
(Hi-Z)
SW5
–
SW2
16
X2 REG
RSENSE
SW4
16-BIT
CLL DAC
×2
4kΩ
SW6
EXTMEASIH[0:3]
CLL
VMID TO
CENTER
I RANGE
SW10
×2
+
–
2kΩ
SW12
AGND
16
16
16
MEASOUT
MUX AND GAIN
×1/×0.2
SW7
X1 REG
M REG
C REG
×6
16
X2 REG
MEASVH[0:3]
+
–
16-BIT
CPH DAC
AGND
GUARD[0:3]
SW13
+
×1
16
16
16
CPH
×6
X1 REG
M REG
C REG
×6
16
16-BIT
CPL DAC
X2 REG
SW9
4kΩ
MEASURE
CURRENT
IN-AMP
SW11
×6
EXTMEASIL[0:3]
+
–
–
TEMP
SENSOR
–
+
–
GUARD AMP
DUTGND
+
–
–
CPL
COMPARATOR
SW16
SW14
GUARDIN[0:3]/
DUTGND[0:3]
DUT
DUTGND
MEASURE
VOLTAGE
IN-AMP
+
EXTERNA L
RSENSE
(CURRENTS
UP TO ±80mA)
SW8
+
×5 or ×10
MEASOUT[0:3]
1kΩ
+
×6
X1 REG
M REG
C REG
CFF[0:3]
×2
×2
X1 REG
M REG
C REG
16
16
16
EXTFOH[0:3]
SW3
SW15
10kΩ
AGND
16-BIT
OFFSET
DAC
16
TO ALL DAC
OUTPUT
AMPLIFIERS
TO
MEASOUT
MUX
TEMP
SENSOR
TMPALM
16
RESET SDO
SCLK SDI SYNC BUSY
CLAMP AND
GUARD
ALARM
LOAD
SPI/ CPOL0/
LVDS SCLK
CPOH0/
SDI
CPOL1/
SYNC
CPOH1/
SDO
CPOL2/ CPOH2/
CPO0
CPO1
CPOL3/
CPO2
CPOH3/
CPO3
CGALM
06197-001
POWER-ON
RESET
SERIAL
INTERFACE
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD5522
TABLE OF CONTENTS
Features .............................................................................................. 1 Reference Selection .................................................................... 35 Applications ....................................................................................... 1 Calibration................................................................................... 36 Functional Block Diagram .............................................................. 1 System Level Calibration ........................................................... 37 Revision History ............................................................................... 3 Circuit Operation ........................................................................... 38 General Description ......................................................................... 4 Force Voltage (FV) Mode .......................................................... 38 Specifications..................................................................................... 6 Force Current (FI) Mode ........................................................... 39 Timing Characteristics .............................................................. 11 Serial Interface ................................................................................ 40 Absolute Maximum Ratings.......................................................... 15 SPI Interface ................................................................................ 40 Thermal Resistance .................................................................... 15 LVDS Interface............................................................................ 40 ESD Caution ................................................................................ 15 Serial Interface Write Mode ...................................................... 40 Pin Configurations and Function Descriptions ......................... 16 RESET Function ......................................................................... 40 Typical Performance Characteristics ........................................... 22 BUSY and LOAD Functions ..................................................... 40 Terminology .................................................................................... 28 Register Update Rates ................................................................ 41 Theory of Operation ...................................................................... 29 Register Selection ....................................................................... 41 Force Amplifier ........................................................................... 29 Write System Control Register ................................................. 43 Comparators................................................................................ 29 Write PMU Register ................................................................... 45 Clamps ......................................................................................... 29 Write DAC Register ................................................................... 47 Current Range Selection ............................................................ 30 Read Registers ............................................................................. 50 High Current Ranges ................................................................. 30 Readback of System Control Register...................................... 51 Measure Current Gains.............................................................. 31 Readback of PMU Register ....................................................... 52 VMID Voltage ............................................................................. 31 Readback of Comparator Status Register ................................ 53 Choosing Power Supply Rails ................................................... 32 Readback of Alarm Status Register .......................................... 53 Measure Output (MEASOUTx Pins) ...................................... 32 Readback of DAC Register ........................................................ 54 Device Under Test Ground (DUTGND)................................. 32 Applications Information .............................................................. 55 Guard Amplifier ......................................................................... 33 Power-On Default ...................................................................... 55 Compensation Capacitors ......................................................... 33 Setting Up the Device on Power-On ....................................... 55 System Force and Sense Switches ............................................. 33 Changing Modes ........................................................................ 56 Temperature Sensor ................................................................... 33 Required External Components ............................................... 56 DAC Levels ...................................................................................... 34 Power Supply Decoupling ......................................................... 57 Offset DAC .................................................................................. 34 Power Supply Sequencing ......................................................... 57 Gain and Offset Registers .......................................................... 34 Typical Application for the AD5522 ........................................ 57 Cached X2 Registers................................................................... 35 Outline Dimensions ....................................................................... 59 Reference Voltage (VREF)......................................................... 35 Ordering Guide .......................................................................... 60 Rev. A | Page 2 of 60
AD5522
REVISION HISTORY
10/08—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 6
Change to 4 DAC X1 Parameter, Table 2 .....................................11
Changes to Table 3 ..........................................................................12
Change to Reflow Soldering Parameter, Table 4 .........................15
Changes to Figure 18, Figure 19, Figure 20, and Figure 21 .......23
Changes to Figure 25 ......................................................................24
Changes to Force Amplifier Section .............................................29
Changes to Clamps Section ...........................................................29
Changes to High Current Ranges Section ...................................30
Changes to Choosing Power Supply Rails Section ..................... 32
Changes to Compensation Capacitors Section ........................... 33
Added Table 14, Renumbered Tables Sequentially ..................... 36
Changes to Reference Selection Example .................................... 36
Changes to Table 15 and BUSY and LOAD Functions
Section .............................................................................................. 40
Changes to Table 17 and Register Update Rates Section ........... 41
Added Table 38 ................................................................................ 57
Changes to Ordering Guide ........................................................... 60
7/08—Revision 0: Initial Version
Rev. A | Page 3 of 60
AD5522
GENERAL DESCRIPTION
The AD5522 is a high performance, highly integrated parametric
measurement unit consisting of four independent channels. Each
per-pin parametric measurement unit (PPMU) channel includes
five 16-bit, voltage output DACs that set the programmable input
levels for the force voltage inputs, clamp inputs, and comparator
inputs (high and low). Five programmable force and measure
current ranges are available, ranging from ±5 μA to ±80 mA.
Four of these ranges use on-chip sense resistors; one high current
range up to ±80 mA is available per channel using off-chip sense
resistors. Currents in excess of ±80 mA require an external amplifier. Low capacitance DUT connections (FOH and EXTFOH)
ensure that the device is suited to relayless test systems.
The PMU functions are controlled via a simple 3-wire serial
interface compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards. Interface clocks of 50 MHz allow fast updating
of modes. The low voltage differential signaling (LVDS) interface
protocol at 83 MHz is also supported. Comparator outputs are
provided per channel for device go-no-go testing and characterization. Control registers allow the user to easily change force or
measure conditions, DAC levels, and selected current ranges.
The SDO (serial data output) pin allows the user to read back
information for diagnostic purposes.
Rev. A | Page 4 of 60
AD5522
AVSS
AGND
VREF
REFGND
16
16
16
X1 REG
M REG
C REG
16
16
16
DVCC
AVDD
DGND
CCOMP0
CH0
16-BIT
CLH DAC
16
X2 REG
EN
CLH
×2
OFFSET DAC
X1 REG
M REG
C REG
–
16-BIT
16 FIN DAC
FIN
INTERNAL RANGE
SELECT
(±5µA, ±20µA, ±200µA, ±2mA)
SW1
+
+
AGND
X2 REG
FOH0
FORCE
AMPLIFIER
MEASVH
(Hi-Z)
×6
SW5
–
RSENSE
SW2
X1 REG
M REG
C REG
CFF0
SW3
×2
×6
16
16
16
EXTFOH0
16
X2 REG
16-BIT
CLL DAC
×2
SW10
×2
SW6
SW4
4kΩ
EXTMEASIH0
CLL
VMID TO
CENTER
I RANGE
+
–
2kΩ
+
×5 OR ×10
MEASOUT0
SW12
AGND
16
16
16
MEASOUT
MUX AND GAIN
×1/×0.2
EXTMEASIL0
TEMP
SENSOR
16
MEASURE
CURRENT
IN-AMP
X2 REG
MEASVH0
+
–
16-BIT
CPH DAC
AGND
CPH
×6
×6
X1 REG
M REG
C REG
16-BIT CPL
CPL DAC
16
X2 REG
–
–
+
SW16
SW13
+
+
–
–
+
DUTGND
SW14
GUARDIN0/
DUTGND0
MEASURE
VOLTAGE
IN-AMP
COMPARATOR
DUT
GUARD0
GUARD AMP
DUTGND
×1
16
16
16
SW9
4kΩ
×6
X1 REG
M REG
C REG
SW7
+
–
–
SW11
×6
EXTERNAL
RSENSE
(CURRENTS
UP TO ±80mA)
SW8
SW15
10kΩ
CPOL0/SCLK
AGND
CPOH0/SDI
EXTFOH1
CFF1
FOH1
CCOMP1
CH1
MEASOUT1
CPOL1/SYNC
EXTMEASIH1
EXTMEASIL1
CPOH1/SDO
AGND
MEASVH1
GUARD1
GUARDIN1/DUTGND1
MUX
MUX
SYS_SENSE
SYS_FORCE
EXTFOH2
CCOMP2
CFF2
MEASOUT2
FOH2
EXTMEASIH2
CH2
CPOL2/CPO0
CPOH2/CPO1
AGND
EXTMEASIL2
MEASVH2
GUARD2
GUARDIN2/DUTGND2
EN
CCOMP3
X1 REG
M REG
C REG
16
16
16
16-BIT
CLH DAC
16
X2 REG
CLH
CH3
×2
×2
OFFSET DAC
×6
X1 REG
M REG
C REG
–
16-BIT
16 FIN DAC
FIN
+
AGND
FOH3
FORCE
AMPLIFIER
MEASVH
(Hi-Z)
×6
SW5
–
RSENSE
SW2
16
16
16
X1 REG
M REG
C REG
16
X2 REG
16-BIT
CLL DAC
×2
SW6
VMID TO
CENTER
I RANGE
EXTMEASIH3
CLL
+
–
SW12
AGND
16
16
16
MEASOUT
MUX AND GAIN
x1/x0.2
2kΩ
X1 REG
M REG
C REG
MEASURE
CURRENT
IN-AMP
X2 REG
AGND
CPH
×6
X1 REG
M REG
C REG
×6
16
X2 REG
MEASVH3
+
–
16-BIT
CPH DAC
+
–
GUARD AMP
DUTGND
+
–
–
16-BIT CPL
CPL DAC
–
SW13
+
x1
16
16
16
EXTMEASIL3
SW9
4kΩ
TEMP
SENSOR
×6
16
SW7
+
–
–
SW11
×6
SW16
SW14
16
10kΩ
DUTGND
SW15a
TO
MEASOUT
MUX
TEMP
SENSOR
TMPALM
CLAMP AND
GUARD
ALARM
CGALM
16
POWER-ON
RESET
10kΩ
SERIAL
INTERFACE
CPOL3/
RESET SDO SCLK SDI SYNC BUSY LOAD SPI/
LVDS CPO2
AGND
CPOH3/
CPO3
Figure 2. Detailed Block Diagram
Rev. A | Page 5 of 60
DUT
SW15
AGND
TO ALL DAC
OUTPUT
AMPLIFIERS
GUARD3
GUARDIN3/
DUTGND3
MEASURE
VOLTAGE
IN-AMP
+
COMPARATOR
16-BIT
OFFSET
DAC
EXTERNAL
RSENSE
(CURRENTS
UP TO ±80mA)
SW8
+
x5 or x10
MEASOUT3
4kΩ
SW4
SW10
×2
CFF3
INTERNAL RANGE
SELECT
(±5µA, ±20µA, ±200µA, ±2mA)
SW1
+
X2 REG
EXTFOH3
SW3
06197-002
16
16
16
AD5522
SPECIFICATIONS
AVDD ≥ 10 V; AVSS ≤ −5 V; |AVDD − AVSS| ≥ 20 V and ≤ 33 V; DVCC = 2.3 V to 5.25 V; VREF = 5 V; REFGND = DUTGND = AGND
= 0 V; gain (M), offset (C), and DAC offset registers at default values; TJ = 25°C to 90°C, unless otherwise noted. (FV = force voltage,
FI = force current, MV = measure voltage, MI = measure current, FS = full scale, FSR = full-scale range, FSVR = full-scale voltage range,
FSCR = full-scale current range.)
Table 1.
Parameter
FORCE VOLTAGE
FOHx Output Voltage Range2
EXTFOHx Output Voltage
Range2
Output Voltage Span
Offset Error
Offset Error Tempco2
Gain Error
Gain Error Tempco2
Linearity Error
Short-Circuit Current Limit2
Min
Max
Unit
Test Conditions/Comments
AVSS + 4
AVDD − 4
V
AVSS + 3
AVDD − 3
V
All current ranges from FOHx at full-scale current;
includes ±1 V dropped across sense resistor
External high current range at full-scale current;
does not include ±1 V dropped across sense resistor
22.5
−50
−0.5
+0.5
0.5
V
mV
μV/°C
% FSR
ppm/°C
% FSR
−0.01
+0.01
−150
−10
+150
+10
mA
mA
nV/√Hz
+1.125
V
320
Differential Input Voltage
Range2
Output Voltage Span
−1.125
Offset Error
Offset Error Tempco2
Gain Error
−0.5
Common-Mode Voltage Range2
Common-Mode Error
+50
−10
Noise Spectral Density (NSD)2
MEASURE CURRENT
Gain Error Tempco2
Linearity Error
Typ1
22.5
V
+0.5
−0.015
+0.015
% FSCR
μV/°C
% FSCR
% FSCR
ppm/°C
% FSCR
−0.01
+0.01
% FSCR
AVSS + 4
−0.005
AVDD − 4
+0.005
V
% FSVR/V
1
−1
−0.5
+1
+0.5
−2
Sense Resistors
200
50
5
0.5
kΩ
kΩ
kΩ
kΩ
±5
±20
±200
±2
μA
μA
μA
mA
mA
Measure Current Ranges2
±80
Noise Spectral Density (NSD)2
400
nV/√Hz
Rev. A | Page 6 of 60
Measured at midscale code; prior to calibration
Standard deviation = 20 μV/°C
Prior to calibration
Standard deviation = 0.5 ppm/°C
FSR = full-scale range (±10 V), gain and offset errors
calibrated out
±80 mA range
All other ranges
1 kHz, at FOHx in FV mode
Measure current = (IDUT × RSENSE × gain); amplifier
gain = 5 or 10, unless otherwise noted
Voltage across RSENSE; gain = 5 or 10
Measure current block with VREF = 5 V, MEASOUT
scaling happens after
V(RSENSE) = ±1 V, measured with zero current flowing
Referred to MI input; standard deviation = 4 μV/°C
Using internal current ranges
Measure current amplifier alone
Standard deviation = 2 ppm/°C
Gain and offset errors calibrated out; MEASOUTx
gain = 1; MI gain = 10
Gain and offset errors calibrated out; MEASOUTx
gain = 1; MI gain = 5
% of full-scale change at measure output per V
change in DUT voltage
Sense resistors are trimmed to within 1%
±5 μA range
±20 μA range
±200 μA range
±2 mA range
Specified current ranges are achieved with VREF = 5 V
and MI gain = 10, or with VREF = 2.5 V and MI gain = 5
Set using internal sense resistor
Set using internal sense resistor
Set using internal sense resistor
Set using internal sense resistor
Set using external sense resistor; internal amplifier
can drive up to ±80 mA
1 kHz, MI amplifier only, inputs grounded
AD5522
Parameter
FORCE CURRENT
Voltage Compliance, FOHx2
Voltage Compliance, EXTFOHx2
Offset Error
Offset Error Tempco2
Gain Error
Gain Error Tempco2
Linearity Error
Force Current Ranges
Min
Typ 1
AVSS + 4
AVSS + 3
−0.5
Max
Unit
AVDD − 4
AVDD − 3
+0.5
V
V
% FSCR
ppm
FS/°C
% FSCR
ppm/°C
% FSCR
5
−1.5
+1.5
−6
−0.02
+0.02
±5
±20
±200
±2
±80
MEASURE VOLTAGE
Measure Voltage Range2
Offset Error
Offset Error Tempco2
Gain Error
Gain Error Tempco2
Linearity Error
Noise Spectral Density (NSD)2
OFFSET DAC
Span Error
COMPARATOR
Comparator Span
Offset Error
Offset Error Tempco2
Propagation Delay2
VOLTAGE CLAMPS
Clamp Span
Positive Clamp Accuracy
Negative Clamp Accuracy
CLL to CLH2
Recovery Time2
Activation Time2
CURRENT CLAMPS
Clamp Accuracy
CLL to CLH2
AVSS + 4
−10
−25
AVDD − 4
+10
+25
100
V
mV
mV
μV/°C
% FSR
% FSR
ppm/°C
% FSR
nV/√Hz
±30
mV
−1
−0.25
−0.5
+0.25
+0.5
1
−0.01
−2
+0.01
22.5
+1
+2
1
0.25
22.5
155
−155
500
0.5
1.5
Programmed
clamp value
Programmed
clamp value
5
1.5
3
Programmed
clamp value + 10
Programmed
clamp value + 20
0.5
1.5
V
mV
μV/°C
μs
10
Recovery Time2
Activation Time2
μA
μA
μA
mA
mA
1.5
3
Rev. A | Page 7 of 60
V
mV
mV
mV
μs
μs
% FSCR
% FSCR
% of
IRANGE
% of
IRANGE
μs
μs
Test Conditions/Comments
Measured at midscale code, 0 V, prior to calibration
Standard deviation = 5 ppm/°C
Prior to calibration
Standard deviation = 5 ppm/°C
Specified current ranges achieved with VREF = 5 V and
MI gain = 10, or with VREF = 2.5 V and MI gain = 5 V
Set using internal sense resistor, 200 kΩ
Set using internal sense resistor, 50 kΩ
Set using internal sense resistor, 5 kΩ
Set using internal sense resistor, 500 Ω
Set using external sense resistor; internal amplifier
can drive up to ±80 mA
Gain = 1, measured at 0 V
Gain = 0.2, measured at 0 V
Standard deviation = 6 μV/°C
MEASOUTx gain = 1
MEASOUTx gain = 0.2
Standard deviation = 4 ppm/°C
Gain = 1
1 kHz; measure voltage amplifier only, inputs
grounded
Measured directly at comparator; does not include
measure block errors
Standard deviation = 2 μV/°C
CLL < CLH and minimum voltage apart
MI gain = 10, clamp current scales with selected
range
MI gain = 5, clamp current scales with selected range
CLL < CLH and minimum setting apart, MI gain = 10
CLL < CLH and minimum setting apart, MI gain = 5
AD5522
Parameter
FOHx, EXTFOHx, EXTMEASILx,
EXTMEASIHx, CFFx PINS
Pin Capacitance2
Leakage Current
Leakage Current Tempco2
MEASVHx PIN
Pin Capacitance2
Leakage Current
Leakage Current Tempco2
SYS_SENSE PIN
Pin Capacitance2
Switch Impedance
Leakage Current
Leakage Current Tempco2
SYS_FORCE PIN
Pin Capacitance2
Switch Impedance
Leakage Current
Leakage Current Tempco2
COMBINED LEAKAGE AT DUT
Leakage Current
Leakage Current Tempco2
DUTGND PIN
Voltage Range
Leakage Current
MEASOUTx PIN
Output Voltage Span
Output Impedance
Output Leakage Current
Output Capacitance2
Maximum Load Capacitance2
Output Current Drive2
Short-Circuit Current
Slew Rate2
Enable Time2
Disable Time2
MI to MV Switching Time2
GUARDx PIN
Output Voltage Span
Output Offset
Short-Circuit Current
Maximum Load Capacitance2
Output Impedance
Tristate Leakage Current2
Slew Rate2
Alarm Activation Time2
Min
Typ 1
Max
Unit
+3
pF
nA
10
−3
±0.01
Individual pin on or off switch leakage, measured with
±11 V stress applied to pin, channel enabled, but
tristate
nA/°C
3
−3
Test Conditions/Comments
+3
pF
nA
±0.01
nA/°C
3
1
1.3
+3
pF
kΩ
nA
nA/°C
80
+3
pF
Ω
nA
nA/°C
Measured with ±11V stress applied to pin, channel
enabled, but tristate
SYS_SENSE connected, force amplifier inhibited
−3
±0.01
Measured with ±11 V stress applied to pin, switch off
SYS_FORCE connected, force amplifier inhibited
6
60
−3
±0.01
−15
−25
+15
+25
nA
nA
nA/°C
+500
+30
mV
nA
±0.1
−500
−30
22.5
60
−3
80
+3
15
0.5
2
−10
+10
2
150
400
200
320
1100
22.5
−10
−15
+10
+15
100
85
−30
+30
5
200
Rev. A | Page 8 of 60
V
Ω
nA
pF
μF
mA
mA
V/μs
ns
ns
ns
V
mV
mA
nF
Ω
nA
V/μs
μs
Measured with ±11 V stress applied to pin, switch off
Includes FOHx, MEASVHx, SYS_SENSE, SYS_FORCE,
EXTMEASILx, EXTMEASIHx, EXTFOHx, and CFFx;
calculation of all the individual leakage contributors
TJ = 25°C to 70°C
TJ = 25°C to 90°C
With respect to AGND
Software programmable output range
With SW12 off
Closing SW12, measured from BUSY rising edge
Opening SW12, measured from BUSY rising edge
Measured from BUSY rising edge; does not include
slewing or settling
When guard amplifier is disabled
CLOAD = 10 pF
Alarm delayed to eliminate false alarms
AD5522
Parameter
FORCE AMPLIFIER2
Slew Rate
Gain Bandwidth
Max Stable Load Capacitance
Min
Typ1
Max
Unit
Test Conditions/Comments
10,000
V/μs
MHz
pF
100
nF
0.4
1.3
±80 mA Range
±2 mA Range
±200 μA Range
±20 μA Range
±5 μA Range
MI SETTLING TIME TO 0.05% OF FS2
22
24
40
300
1400
40
40
80
μs
μs
μs
μs
μs
±80 mA Range
±2 mA Range
±200 μA Range
±20 μA Range
±5 μA Range
FI SETTLING TIME TO 0.05% OF FS2
22
24
60
462
1902
40
40
100
μs
μs
μs
μs
μs
±80 mA Range
±2 mA Range
±200 μA Range
±20 μA Range
±5 μA Range
MV SETTLING TIME TO 0.05% OF FS2
24
24
50
450
2700
55
60
120
μs
μs
μs
μs
μs
±80 mA Range
±2 mA Range
±200 μA Range
±20 μA Range
±5 μA Range
DAC SPECIFICATIONS
Resolution
Output Voltage Span2
Differential Nonlinearity2
COMPARATOR DAC DYNAMIC
SPECIFICATIONS2
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
REFERENCE INPUT
VREF DC Input Impedance
VREF Input Current
VREF Range2
DIE TEMPERATURE SENSOR
Accuracy2
Output Voltage at 25°C
Output Scale Factor2
Output Voltage Range2
24
24
50
450
2700
55
60
120
μs
μs
μs
μs
μs
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, larger CLOAD requires larger
CCOMP
CCOMPx = 1 nF, larger CLOAD requires larger CCOMP
Midscale to full-scale change; measured from SYNC
rising edge, clamps on
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
Midscale to full-scale change; driven from force
amplifier in FV mode, so includes FV settling time;
measured from SYNC rising edge, clamps on
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF
Midscale to full-scale change; measured from SYNC
rising edge, clamps on
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
Midscale to full-scale change; driven from force
amplifier in FV mode, so includes FV settling time;
measured from SYNC rising edge, clamps on
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
CCOMPx = 100 pF, CLOAD = 200 pF
16
Bits
V
LSB
VREF = 5 V, within a range of −16.25 V to +22.5 V
Guaranteed monotonic by design over temperature
FV SETTLING TIME TO 0.05% OF FS2
22.5
−1
+1
1
5.5
20
10
1
−10
2
100
+0.03
μs
V/μs
nV-s
mV
+10
5
MΩ
μA
V
3
°C
V
mV/°C
V
±7
1.5
4.6
0
Rev. A | Page 9 of 60
500 mV change to ±½ LSB
AD5522
Typ 1
Max
Unit
Test Conditions/Comments
0.05
0.65
mV
DC Crosstalk (MEASOUTx)
0.05
0.65
mV
DC Crosstalk Within a Channel
0.05
DC change resulting from a dc change in any DAC
in the device, FV and FI modes, ±2 mA range, CLOAD
= 200 pF, RLOAD = 5.6 kΩ
DC change resulting from a dc change in any DAC
in the device, MV and MI modes, ±2 mA range,
CLOAD = 200 pF, RLOAD = 5.6 kΩ
All channels in FVMI mode, one channel at
midscale; measure the current for one channel in
the lowest current range for a change in
comparator or clamp DAC levels for that PMU
Parameter
INTERACTION AND CROSSTALK2
DC Crosstalk (FOHx)
SPI INTERFACE LOGIC INPUTS
Input High Voltage, VIH
Min
1.7/2.0
V
Input Low Voltage, VIL
Input Current, IINH, IINL
Input Capacitance, CIN2
CMOS LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Tristate Leakage Current
Output Capacitance2
OPEN-DRAIN LOGIC OUTPUTS
Output Low Voltage, VOL
Output Capacitance2
LVDS INTERFACE LOGIC INPUTS
REDUCED RANGE LINK2
Input Voltage Range
Input Differential Threshold
External Termination Resistance
Differential Input Voltage
LVDS INTERFACE LOGIC OUTPUTS
REDUCED RANGE LINK
Output Offset Voltage
Output Differential Voltage
POWER SUPPLIES
AVDD
AVSS
DVCC
AIDD
AISS
−1
AIDD
AISS
DICC
Maximum Power Dissipation2
0.7/0.8
V
+1
10
μA
pF
0.4
+2
+1
10
V
V
μA
μA
pF
(2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant
input levels
(2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant
input levels
SDO, CPOx
DVCC − 0.4
−2
−1
875
−100
80
100
100
0.4
10
V
pF
1575
+100
120
mV
mV
Ω
mV
1200
400
10
−23
2.3
IOL = 500 μA.
SDO, CPOH1/SDO
All other output pins
BUSY, TMPALM, CGALM
IOL = 500 μA, CLOAD = 50 pF, RPULLUP = 1 kΩ
mV
mV
28
−5
5.25
26
−26
AIDD
AISS
mV
V
V
V
mA
mA
28
−28
mA
mA
36
−36
1.5
7
Rev. A | Page 10 of 60
mA
mA
mA
W
|AVDD − AVSS| ≤ 33 V
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard disabled
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard disabled
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard enabled
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard enabled
External range, excluding load conditions
External range, excluding load conditions
Maximum power that should be dissipated in this
package under worst-case load conditions; careful
consideration should be given to supply selection
and thermal design
AD5522
Parameter
Power Supply Sensitivity2
ΔForced Voltage/ΔAVDD
ΔForced Voltage/ΔAVSS
ΔMeasured Current/ΔAVDD
ΔMeasured Current/ΔAVSS
ΔForced Current/ΔAVDD
ΔForced Current/ΔAVSS
ΔMeasured Voltage/ΔAVDD
ΔMeasured Voltage/ΔAVSS
ΔForced Voltage/ΔDVCC
ΔMeasured Current/ΔDVCC
ΔForced Current/ΔDVCC
ΔMeasured Voltage/ΔDVCC
1
2
Min
Typ 1
Max
Unit
−80
−80
−85
−75
−75
−75
−85
−80
−90
−90
−90
−90
Test Conditions/Comments
From dc to 1 kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Typical specifications are at 25°C and nominal supply, ±15.25 V, unless otherwise noted.
Guaranteed by design and characterization; not production tested. Tempco values are mean and standard deviation, unless otherwise noted.
TIMING CHARACTERISTICS
AVDD ≥ 10 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 20 V and ≤ 33 V, DVCC = 2.3 V to 5.25 V, VREF = 5 V, TJ = 25°C to 90°C, unless
otherwise noted.
Table 2. SPI Interface
Parameter
tWRIT E 4
1, 2, 3
t1
t2
t3
t4
t54
t6
t7
t8
t9
t10
1 DAC X1
2 DAC X1
3 DAC X1
4 DAC X1
Other Registers
t11
t12
t13
t14
t15
DVCC, Limit at TMIN, TMAX
2.3 V to 2.7 V
2.7 V to 3.6 V 4.5 V to 5.25 V
1030
735
735
950
655
655
Unit
ns min
ns min
30
8
8
10
150
20
8
8
10
150
20
8
8
10
150
ns min
ns min
ns min
ns min
ns min
70
70
70
ns min
10
5
9
120
5
5
7
75
5
5
4.5
55
ns min
ns min
ns min
ns max
1.5
2.1
2.7
3.3
270
20
20
150
0
100
1.5
2.1
2.7
3.3
270
20
20
150
0
100
1.5
2.1
2.7
3.3
270
20
20
150
0
100
μs max
μs max
μs max
μs max
ns max
ns min
ns min
ns min
ns min
ns max
Rev. A | Page 11 of 60
Description
Single channel update cycle time (X1 register write)
Single channel update cycle time (any other register
write)
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time in write mode after X1
register write (one channel)
Minimum SYNC high time in write mode after any
other register write
29th SCLK falling edge to SYNC rising edge
Data setup time
Data hold time
SYNC rising edge to BUSY falling edge
BUSY pulse width low; see Table 17
System control register/PMU registers
29th SCLK falling edge to LOAD falling edge
LOAD pulse width low
BUSY rising edge to FOHx output response time
BUSY rising edge to LOAD falling edge
LOAD rising edge to FOHx output response time
AD5522
Parameter 1, 2, 3
t16
t17
t18
t19 5, 6
DVCC, Limit at TMIN, TMAX
2.3 V to 2.7 V
2.7 V to 3.6 V 4.5 V to 5.25 V
1.8
1.2
0.9
670
700
750
400
400
400
60
45
25
Unit
ns min
μs max
ns min
ns max
Description
RESET pulse width low
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid; DVCC = 5 V to 5.25 V
1
Guaranteed by design and characterization; not production tested.
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 5 and Figure 6.
4
Writes to more than one X1 register, engages the calibration engine for longer times, shown by the BUSY low time, t10. Subsequent writes to one or more X1 registers
should either be timed or should wait until BUSY returns high (see Figure 53). This is required to ensure data is not lost or overwritten.
5
t19 is measured with the load circuit shown in Figure 4.
6
SDO output slows with lower DVCC supply and may require use of a slower SCLK.
2
Table 3. LVDS Interface
Parameter 1, 2, 3
t1
t2
t3
t4
t5
t6
t7 4
t8
DVCC, Limit at TMIN, TMAX
2.7 V to 3.6 V
4.5 V to 5.25 V
20
12
8
5
3
3
3
3
5
3
3
3
45
25
150
150
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
70
70
ns min
400
400
ns min
1
Description
SCLK cycle time
SCLK pulse width high and low time
SYNC to SCLK setup time
Data setup time
Data hold time
SCLK to SYNC hold time
SCLK rising edge to SDO valid
Minimum SYNC high time in write mode after X1
register write
Minimum SYNC high time in write mode after any
other register write
Minimum SYNC high time in readback mode
Guaranteed by design and characterization; not production tested.
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 7.
4
SDO output slows with lower DVCC supply and may require use of slower SCLK.
2
Rev. A | Page 12 of 60
AD5522
Circuit and Timing Diagrams
DVCC
200µA
2.2kΩ
50pF
VOH(MIN) – VOL(MAX)
2
200µA
06197-004
VOL
CLOAD
TO OUTPUT
PIN
CLOAD
50pF
06197-003
RLOAD
TO
OUTPUT
PIN
IOL
IOH
Figure 4. Load Circuit for SDO, BUSY Timing Diagram
Figure 3. Load Circuit for CGALM, TMPALM
t1
SCLK
1
29
2
29
1
t2
t3
t4
t6
SYNC
t5
t7
t8
SDI
DB0
DB28
DB0
DB28
t9
t10
BUSY
t11
t12
LOAD1
t13
FOHx1
t14
t12
LOAD2
t15
FOHx2
t16
RESET
06197-005
t17
BUSY
1LOAD ACTIVE DURING BUSY.
2LOAD ACTIVE AFTER BUSY.
Figure 5. SPI Write Timing (Write Word Contains 29 Bits)
Rev. A | Page 13 of 60
AD5522
SCLK
58
29
t19
t18
SYNC
SDI
DB28
DB23/
DB28
DB0
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB23/
DB28
DB0
06197-006
SDO
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 6. SPI Read Timing (Readback Word Contains 24 Bits and Can Be Clocked Out with a Minimum of 24 Clock Edges)
t8
SYNC
SYNC
t3
t1
t6
SCLK
SCLK
MSB
D28
t4
t2
MSB
D23/D28
LSB
D0
LSB
D0
SDI
t5
t7
SDO
MSB
DB23/
DB28
SDO
UNDEFINED
LSB
DB0
SELECTED REGISTER DATA CLOCKED OUT
Figure 7. LVDS Read and Write Timing (Readback Word Contains 24 Bits and Can Be Clocked Out with a Minimum of 24 Clock Edges)
Rev. A | Page 14 of 60
06197-007
SDI
AD5522
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage, AVDD to AVSS
AVDD to AGND
AVSS to AGND
VREF to AGND
DUTGND to AGND
REFGND to AGND
DVCC to DGND
AGND to DGND
Digital Inputs to DGND
Analog Inputs to AGND
Storage Temperature Range
Operating Junction Temperature
Range (J Version)
Reflow Soldering
Junction Temperature
Rating
34 V
−0.3 V to +34 V
+0.3 V to −34 V
−0.3 V to +7 V
AVDD + 0.3 V to AVSS − 0.3 V
AVDD + 0.3 V to AVSS − 0.3 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to DVCC + 0.3 V
AVSS − 0.3 V to AVDD + 0.3 V
−65°C to +125°C
25°C to 90°C
Thermal resistance values are specified for the worst-case
conditions, that is, a device soldered in a circuit board for
surface-mount packages.
Table 5. Thermal Resistance1 (JEDEC 4-Layer (1S2P) Board)
Package Type
TQFP Exposed Pad Down
No Heat Sink2
With Cooling Plate at 45°C3
TQFP Exposed Pad Up
No Heat Sink2
JEDEC Standard (J-STD-020)
150°C max
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
With Cooling Plate at 45°C3
1
Airflow
(LFPM)
θJA
0
200
500
N/A
22.3
17.2
15.1
5.4
0
200
500
N/A4
42.4
37.2
35.7
3.0
θJC
4.8
4.8
2
2
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
The information in this section is based on simulated thermal information.
These values apply to the package with no heat sink attached. The actual
thermal performance of the package depends on the attached heat sink and
environmental conditions.
3
Natural convection at 55°C ambient. Assumes perfect thermal contact
between the cooling plate and the exposed paddle.
3
N/A means not applicable.
2
ESD CAUTION
Rev. A | Page 15 of 60
AD5522
80 79 78 77 76 75 74
EXTFOH1
AVSS
MEASOUT3
MEASOUT2
MEASOUT1
MEASOUT0
AVSS
SYS_FORCE
AGND
SYS_SENSE
REFGND
VREF
DUTGND
AVDD
SPI/LVDS
CGALM
TMPALM
RESET
AVSS
EXTFOH0
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
73 72 71 70 69 68 67 66 65 64 63 62 61
60 AVDD
AVDD 1
CFF0 2
PIN 1
59 CFF1
58 CCOMP1
CCOMP0 3
EXTMEASIH0 4
57 EXTMEASIH1
EXTMEASIL0 5
56 EXTMEASIL1
FOH0 6
55 FOH1
54 GUARD1
GUARD0 7
AD5522
GUARDIN0/DUTGND0 8
53 GUARDIN1/DUTGND1
TOP VIEW
EXPOSED PAD ON BOTTOM
MEASVH0 9
AGND 10
52 MEASVH1
51 AGND
(Not to Scale)
AGND 11
50 AGND
MEASVH2 12
49 MEASVH3
GUARDIN2/DUTGND2 13
48 GUARDIN3/DUTGND3
GUARD2 14
47 GUARD3
FOH2 15
46 FOH3
EXTMEASIL2 16
45 EXTMEASIL3
EXTMEASIH2 17
44 EXTMEASIH3
CCOMP2 18
43 CCOMP3
CFF2 19
42 CFF3
AVDD 20
41 AVDD
06197-008
EXTFOH3
AVSS
CPOH3/CPO3
CPOL3/CPO2
CPOH2/CPO1
CPOL2/CPO0
DVCC
LOAD
SDO
CPOH1/SDO
DGND
CPOL1/SYNC
SYNC
SDI
CPOH0/SDI
CPOL0/SCLK
SCLK
BUSY
AVSS
EXTFOH2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NOTES:
1. FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Figure 8. Pin Configuration, Exposed Pad on Bottom
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Exposed pad
1, 20, 41,
60, 74
2
AVDD
3
4
5
6
7
8
CCOMP0
EXTMEASIH0
EXTMEASIL0
FOH0
GUARD0
GUARDIN0/
DUTGND0
9
10, 11, 50,
51, 69
12
MEASVH0
AGND
External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section.
Sense Input (High Sense) for High Current Range (Channel 0).
Sense Input (Low Sense) for High Current Range (Channel 0).
Force Output for Internal Current Ranges (Channel 0).
Guard Output Drive for Channel 0.
Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
DUT Voltage Sense Input (High Sense) for Channel 0.
Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry.
MEASVH2
DUT Voltage Sense Input (High Sense) for Channel 2.
CFF0
Description
The exposed pad is internally electrically connected to AVSS. For enhanced thermal, electrical, and board level
performance, the exposed paddle on the bottom of the package should be soldered to a corresponding
thermal land paddle on the PCB.
Positive Analog Supply Voltage.
Rev. A | Page 16 of 60
AD5522
Pin No.
13
Mnemonic
GUARDIN2/
DUTGND2
14
15
16
17
18
19
GUARD2
FOH2
EXTMEASIL2
EXTMEASIH2
CCOMP2
CFF2
21
EXTFOH2
22, 39, 62,
67, 79
23
AVSS
24
SCLK
25
CPOL0/SCLK
26
CPOH0/SDI
27
28
29
30
31
SDI
SYNC
CPOL1/SYNC
DGND
CPOH1/SDO
32
33
SDO
LOAD
34
35
DVCC
CPOL2/CPO0
36
CPOH2/CPO1
37
CPOL3/CPO2
38
CPOH3/CPO3
40
EXTFOH3
42
CFF3
43
44
45
46
47
48
CCOMP3
EXTMEASIH3
EXTMEASIL3
FOH3
GUARD3
GUARDIN3/
DUTGND3
BUSY
Description
Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
Guard Output Drive for Channel 2.
Force Output for Internal Current Ranges (Channel 2).
Sense Input (Low Sense) for High Current Range (Channel 2).
Sense Input (High Sense) for High Current Range (Channel 2).
Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section.
External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
Negative Analog Supply Voltage.
Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD
Functions section for more information.
Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This
pin operates at clock speeds up to 50 MHz.
Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS
Interface.
Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS
Interface.
Serial Data Input for SPI or LVDS Interface.
Active Low Frame Synchronization Input for SPI or LVDS Interface.
Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface.
Digital Ground Reference Point.
Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS
Interface.
Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes.
Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If
synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated
immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information.
Digital Supply Voltage.
Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS
Interface.
Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS
Interface.
Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS
Interface.
Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS
Interface.
Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section.
Sense Input (High Sense) for High Current Range (Channel 3).
Sense Input (Low Sense) for High Current Range (Channel 3).
Force Output for Internal Current Ranges (Channel 3).
Guard Output Drive for Channel 3.
Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
Rev. A | Page 17 of 60
AD5522
Pin No.
49
52
53
Mnemonic
MEASVH3
MEASVH1
GUARDIN1/
DUTGND1
54
55
56
57
58
59
GUARD1
FOH1
EXTMEASIL1
EXTMEASIH1
CCOMP1
CFF1
61
EXTFOH1
63
MEASOUT3
64
MEASOUT2
65
MEASOUT1
66
MEASOUT0
68
70
71
72
73
SYS_FORCE
SYS_SENSE
REFGND
VREF
DUTGND
75
SPI/LVDS
76
CGALM
77
TMPALM
78
RESET
80
EXTFOH0
Description
DUT Voltage Sense Input (High Sense) for Channel 3.
DUT Voltage Sense Input (High Sense) for Channel 1.
Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
Guard Output Drive for Channel 1.
Force Output for Internal Current Ranges (Channel 1).
Sense Input (Low Sense) for High Current Range (Channel 1).
Sense Input (High Sense) for High Current Range (Channel 1).
Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section.
External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is
referenced to AGND.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is
referenced to AGND.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is
referenced to AGND.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is
referenced to AGND.
External Force Signal Input. This pin enables the connection of the system PMU.
External Sense Signal Output. This pin enables the connection of the system PMU.
Accurate Analog Reference Input Ground.
Reference Input for DAC Channels (5 V for specified performance).
DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND
input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for
each PMU channel.
Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode.
This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default
to differential interface pins.
Open-Drain Output for Guard and Clamp Alarms. This open-drain pin provides shared alarm information
about the guard amplifier and clamp circuitry. By default, this output pin is disabled. The system control
register allows the user to enable this function and to set the open-drain output as a latched output. The user
can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. When this pin flags an
alarm, the origins of the alarm can be determined by reading back the alarm status register. Two flags per
channel in this word (one latched, one unlatched) indicate which function caused the alarm and whether the
alarm is still present.
Open-Drain Output for Temperature Alarm. This latched, active low, open-drain output flags a temperature
alarm to indicate that the junction temperature has exceeded the default temperature setting (130°C) or the
user programmed temperature setting. Two flags in the alarm status register (one latched, one unlatched)
indicate whether the temperature has dropped below 130°C or remains above 130°C. User action is required
to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers.
Digital Reset Input. This active low, level sensitive input resets all internal nodes on the device to their poweron reset values.
Force Output for High Current Range (Channel 0). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
Rev. A | Page 18 of 60
80 79 78 77 76 75 74
AVDD
CFF2
CCOMP2
EXTMEASIH2
EXTMEASIL2
FOH2
GUARD2
GUARDIN2/DUTGND2
MEASVH2
AGND
AGND
MEASVH0
GUARDIN0/DUTGND0
GUARD0
FOH0
EXTMEASIL0
EXTMEASIH0
CCOMP0
CFF0
AVDD
AD5522
73 72 71 70 69 68 67 66 65 64 63 62 61
60
EXTFOH2
59
AVSS
RESET 3
58
BUSY
TMPALM 4
57
SCLK
CGALM 5
56
CPOL0/SCLK
SPI/LVDS 6
55
CPOH0/SDI
AVDD 7
54
SDI
53
SYNC
52
CPOL1/SYNC
51
DGND
50
CPOH1/SDO
AGND 12
49
SDO
SYS_FORCE 13
48
LOAD
AVSS 14
47
DVCC
MEASOUT0 15
46
CPOL2/CPO0
MEASOUT1 16
45
CPOH2/CPO1
MEASOUT2 17
44
CPOL3/CPO2
MEASOUT3 18
43
CPOH3/CPO3
AVSS 19
42
AVSS
EXTFOH1 20
41
EXTFOH3
EXTFOH0 1
PIN 1
AVSS 2
AD5522
DUTGND 8
TOP VIEW
EXPOSED PAD ON TOP
VREF 9
REFGND 10
(Not to Scale)
SYS_SENSE 11
06197-009
AVDD
CFF3
CCOMP3
EXTMEASIH3
EXTMEASIL3
FOH3
GUARD3
GUARDIN3/DUTGND3
MEASVH3
AGND
AGND
MEASVH1
GUARDIN1/DUTGND1
GUARD1
FOH1
EXTMEASIL1
EXTMEASIH1
CCOMP1
CFF1
AVDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NOTES:
1. FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Figure 9. Pin Configuration, Exposed Pad on Top
Table 7. Pin Function Descriptions
Pin No.
1
Mnemonic
Exposed pad
EXTFOH0
2, 14, 19,
42, 59
3
AVSS
4
TMPALM
5
CGALM
RESET
Description
The exposed pad is electrically connected to AVSS.
Force Output for High Current Range (Channel 0). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
Negative Analog Supply Voltage.
Digital Reset Input. This active low, level sensitive input resets all internal nodes on the device to their poweron reset values.
Open-Drain Output for Temperature Alarm. This latched, active low, open-drain output flags a temperature
alarm to indicate that the junction temperature has exceeded the default temperature setting (130°C) or the
user programmed temperature setting. Two flags in the alarm status register (one latched, one unlatched)
indicate whether the temperature has dropped below 130°C or remains above 130°C. User action is required
to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers.
Open-Drain Output for Guard and Clamp Alarms. This open-drain pin provides shared alarm information
about the guard amplifier and clamp circuitry. By default, this output pin is disabled. The system control
register allows the user to enable this function and to set the open-drain output as a latched output. The user
can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. When this pin flags an
alarm, the origins of the alarm can be determined by reading back the alarm status register. Two flags per
channel in this word (one latched, one unlatched) indicate which function caused the alarm and whether the
alarm is still present.
Rev. A | Page 19 of 60
AD5522
Pin No.
6
Mnemonic
SPI/LVDS
7, 21, 40,
61, 80
8
AVDD
9
10
11
12, 30, 31,
70, 71
13
15
VREF
REFGND
SYS_SENSE
AGND
SYS_FORCE
MEASOUT0
16
MEASOUT1
17
MEASOUT2
18
MEASOUT3
20
EXTFOH1
22
CFF1
23
24
25
26
27
28
CCOMP1
EXTMEASIH1
EXTMEASIL1
FOH1
GUARD1
GUARDIN1/
DUTGND1
29
32
33
MEASVH1
MEASVH3
GUARDIN3/
DUTGND3
34
35
36
37
38
39
GUARD3
FOH3
EXTMEASIL3
EXTMEASIH3
CCOMP3
CFF3
41
EXTFOH3
43
CPOH3/CPO3
44
CPOL3/CPO2
45
CPOH2/CPO1
DUTGND
Description
Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode.
This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default
to differential interface pins.
Positive Analog Supply Voltage.
DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND
input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for
each PMU channel.
Reference Input for DAC Channels. 5 V for specified performance.
Accurate Analog Reference Input Ground.
External Sense Signal Output. This pin enables the connection of the system PMU.
Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry.
External Force Signal Input. This pin enables the connection of the system PMU.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is
referenced to AGND.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is
referenced to AGND.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is
referenced to AGND.
Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is
referenced to AGND.
Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section.
Sense Input (High Sense) for High Current Range (Channel 1).
Sense Input (Low Sense) for High Current Range (Channel 1).
Force Output for Internal Current Ranges (Channel 1).
Guard Output Drive for Channel 1.
Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
DUT Voltage Sense Input (High Sense) for Channel 1.
DUT Voltage Sense Input (High Sense) for Channel 3.
Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
Guard Output Drive for Channel 3.
Force Output for Internal Current Ranges (Channel 3).
Sense Input (Low Sense) for High Current Range (Channel 3).
Sense Input (High Sense) for High Current Range (Channel 3).
Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section.
External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS
Interface.
Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS
Interface.
Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS
Interface.
Rev. A | Page 20 of 60
AD5522
Pin No.
46
Mnemonic
CPOL2/CPO0
47
48
DVCC
LOAD
49
50
SDO
CPOH1/SDO
51
52
53
54
55
DGND
CPOL1/SYNC
SYNC
SDI
CPOH0/SDI
56
CPOL0/SCLK
57
SCLK
58
BUSY
60
EXTFOH2
62
CFF2
63
64
65
66
67
68
CCOMP2
EXTMEASIH2
EXTMEASIL2
FOH2
GUARD2
GUARDIN2/
DUTGND2
69
72
73
MEASVH2
MEASVH0
GUARDIN0/
DUTGND0
74
75
76
77
78
79
GUARD0
FOH0
EXTMEASIL0
EXTMEASIH0
CCOMP0
CFF0
Description
Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS
Interface.
Digital Supply Voltage.
Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If
synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated
immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information.
Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes.
Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS
Interface.
Digital Ground Reference Point.
Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface.
Active Low Frame Synchronization Input for SPI or LVDS Interface.
Serial Data Input for SPI or LVDS Interface.
Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS
Interface.
Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS
Interface.
Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This
pin operates at clock speeds up to 50 MHz.
Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD
Functions section for more information.
Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section.
Sense Input (High Sense) for High Current Range (Channel 2).
Sense Input (Low Sense) for High Current Range (Channel 2).
Force Output for Internal Current Ranges (Channel 2).
Guard Output Drive for Channel 2.
Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
DUT Voltage Sense Input (High Sense) for Channel 2.
DUT Voltage Sense Input (High Sense) for Channel 0.
Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
Guard Output Drive for Channel 0.
Force Output for Internal Current Ranges (Channel 0).
Sense Input (Low Sense) for High Current Range (Channel 0).
Sense Input (High Sense) for High Current Range (Channel 0).
Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section.
External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
Rev. A | Page 21 of 60
AD5522
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
5
TA = 25°C
0.8
4
0.6
3
0.4
2
LINEARITY (LSB)
0.2
0
–0.2
–0.4
DNL
INL
1
0
–1
–2
–0.6
–3
06197-010
DNL
INL
–0.8
–1.0
0
10,000
20,000
30,000
40,000
50,000
06197-013
LINEARITY (LSB)
TA = 25°C
–4
–5
0
60,000
10,000
20,000
30,000
CODE
40,000
50,000
Figure 10. Force Voltage Linearity vs. Code, All Ranges,
1 LSB = 0.0015% FSR (20 V FSR)
Figure 13. Measure Current Linearity vs. Code, All Ranges,
1 LSB = 0.0015% FSR (20 V FSR), MI Gain = 10, MEASOUTx Gain = 1
2.0
1.0
TA = 25°C
V = 0V
EXTFOHx
CFFx
FOHx
EXTMEASIHx
EXTMEASILx
MEASVHx
GUARDINx/DUTGNDx
COMBINED LEAKAGE
1.5
0.8
LEAKAGE CURRENT (nA)
0.5
0
–0.5
–1.0
0.6
0.4
0.2
0
–1.5
06197-011
DNL
INL
–2.0
0
10,000
20,000
30,000
40,000
50,000
–0.2
25
60,000
06197-014
LINEARITY (LSB)
1.0
35
45
CODE
55
65
75
85
95
TEMPERATURE (°C)
Figure 11. Force Current Linearity vs. Code, All Ranges,
1 LSB = 0.0015% FSR (20 V FSR)
Figure 14. Leakage Current vs. Temperature (Stress Voltage = 0 V)
2.0
2.0
TA = 25°C
V = 12V
EXTFOHx
CFFx
FOHx
EXTMEASIHx
EXTMEASILx
MEASVHx
GUARDINx/DUTGNDx
COMBINED LEAKAGE
1.5
1.5
LEAKAGE CURRENT (nA)
1.0
0.5
0
–0.5
–1.0
1.0
0.5
DNL
INL
–2.0
0
10,000
20,000
30,000
40,000
50,000
60,000
CODE
–0.5
25
06197-015
0
–1.5
06197-012
LINEARITY (LSB)
60,000
CODE
35
45
55
65
75
85
95
TEMPERATURE (°C)
Figure 12. Measure Voltage Linearity vs. Code, All Ranges,
1 LSB = 0.0015% FSR (20 V FSR), MEASOUTx Gain = 1 or 0.2
Figure 15. Leakage Current vs. Temperature (Stress Voltage = 12 V)
Rev. A | Page 22 of 60
AD5522
0
0.2
–10
0
VSS
ACPSRR (dB)
–30
–0.4
EXTFOHx
CFFx
FOHx
EXTMEASIHx
EXTMEASILx
MEASVHx
GUARDINx/DUTGNDx
COMBINED LEAKAGE
–0.8
–1.0
–1.2
25
35
45
55
VDD
–40
–50
VCC
–60
–70
V = –12V
–80
65
75
85
–90
–100
10
95
100
TEMPERATURE (°C)
1k
10k
FREQUENCY (Hz)
1M
100k
06197-019
–0.6
06197-016
LEAKAGE CURRENT (nA)
–20
–0.2
Figure 19. ACPSRR at FOHx in Force Current Mode vs. Frequency
(MI Gain = 10)
Figure 16. Leakage Current vs. Temperature (Stress Voltage = −12 V)
0.15
0
TA = 25°C
–10
0.10
ACPSRR (dB)
0
EXTFOHx
CFFx
FOHx
EXTMEASIHx
EXTMEASILx
MEASVHx
GUARDINx/DUTGNDx
COMBINED LEAKAGE
–0.10
–0.15
–0.20
–12 –10
–8
–6
–4 –2
0
2
4
STRESS VOLTAGE (V)
6
8
10
VDD
–40
–50
VCC
–60
–70
–80
–90
–100
–110
10
12
Figure 17. Leakage Current vs. Stress Voltage
100
1k
10k
FREQUENCY (Hz)
1M
100k
06197-119
–0.05
Figure 20. ACPSRR at FOHx in Force Current Mode vs. Frequency
(MI Gain = 5)
0
–20
VSS
–30
06197-017
LEAKAGE CURRENT (nA)
–20
0.05
0
AVDD ACPSRR
AVSS ACPSRR
DVCC ACPSRR
–10
VSS
–20
–30
–40
ACPSRR (dB)
ACPSRR (dB)
–40
–60
VDD
–50
VCC
–60
–70
–80
–80
–100
–100
–90
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 18. ACPSRR at FOHx in Force Voltage Mode vs. Frequency
–120
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
06197-020
100
06197-018
–110
–120
10
Figure 21. ACPSRR at MEASOUTx in Measure Voltage Mode vs. Frequency
(Measout Gain = 1)
Rev. A | Page 23 of 60
AD5522
0
0
–10
–10
–20
–20
VSS
–30
–40
–40
VDD
ACPSRR (dB)
–50
–60
VCC
–70
100
1k
10k
FREQUENCY (Hz)
1M
100k
–120
10
1k
10k
FREQUENCY (Hz)
1M
100k
Figure 25. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency
(MI Gain = 10, Measout Gain = 0.2)
0
0
–10
–10
VSS
–30
100
06197-122
–110
06197-120
–100
–20
–20
–30
VDD
VDD
–40
–50
ACPSRR (dB)
–40
ACPSRR (dB)
VDD
–90
–100
VCC
–60
–70
VSS
–50
VCC
–60
–70
–80
–80
–90
–100
–100
–110
–110
100
1k
10k
FREQUENCY (Hz)
1M
100k
06197-021
–90
–120
10
VCC
–70
–90
Figure 22. ACPSRR at MEASOUTx in Measure Voltage Mode vs. Frequency
(Measout Gain = 0.2)
Figure 23. ACPSRR at MEASOUTx in Measure Current Mode vs. Frequency
(MI Gain = 10, Measout Gain = 1)
–120
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 26. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency
(MI Gain = 5, Measout Gain = 0.2)
900
0
–10
MEASURE CURRENT IN-AMP
MEASURE VOLTAGE IN-AMP
FORCE AMP
800
–20
VSS
700
–30
VDD
600
–50
NSD (nV/ Hz)
–40
ACPSRR (dB)
–60
–80
–80
–110
10
VSS
–50
06197-123
ACPSRR (dB)
–30
VCC
–60
–70
–80
500
400
300
–90
200
100
100
1k
10k
FREQUENCY (Hz)
100k
1M
06197-121
–110
–120
10
06197-022
–100
Figure 24. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency
(MI Gain = 5, Measout Gain = 1)
Rev. A | Page 24 of 60
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 27. NSD vs. Frequency (Measured in FVMV and FVMI Mode)
AD5522
TA = 25°C
1
TA = 25°C
FOH0
1
FOHx VICTIM
2
MEASOUTx VICTIM
3
MEASOUTx
ATTACK
MEASOUT0
06197-023
4
LOAD
B
W
B
CH2 100mV
W
CH4 5.00V
CH1 Pk-Pk 39.00mV CH2 Pk-Pk 325.8mV
CH1 20.0mV
06197-026
2
TRIGGER
4
B
CH1 10.0mV
W CH2 50.0mV
CH3 5.00V
CH4 5.00V
CH2 Pk-Pk 14.38mV
M4.00µs
T
10.0000µs
Figure 28. AC Crosstalk, FVMI Mode, PMU 0, Full-Scale Transition on One CPH
DAC, MI Gain = 10, MEASOUTx Gain = 1, ±2 mA Range, CLOAD = 200 pF
B
W
M100µs
T
200.000µs
Figure 31. Shorted DUT AC Crosstalk, Victim PMU in FVMI Mode
(±200 μA Range)
1.80
TA = 25°C
1.75
MEASOUT1
1.65
1.60
1.55
1.50
06197-024
LOAD
1.40
25
B
CH2 100mV
M4.00µs
W
CH4 5.00V
T
10.0000µs
CH1 Pk-Pk 18.80mV CH2 Pk-Pk 140.0mV
CH1 20.0mV
NOMINAL SUPPLIES
±15.25V
5 DIFFERENT DEVICES
1.45
B
W
35
45
55
65
75
06197-127
FOH1
2
4
1.70
MEASOUTx VOLTAGE (V)
1
85
FORCED TEMPERATURE (°C)
Figure 29. AC Crosstalk, FVMI Mode, PMU 1, Full-Scale Transition on One CPH
DAC, MI Gain = 10, MEASOUTx Gain = 1, ±2 mA Range, CLOAD = 200 pF
Figure 32. Temperature Sensor Voltage on MEASOUTx
vs. Forced Temperature
T
SYNC
ATTACK FROM FIN1
16.70mV p-p
1
4
FOH0
3
BUSY
ATTACK FROM FIN2
10.35mV p-p
FOH0
1
ATTACK FROM FIN3
11.75mV p-p
FOH0
FOH0
11
CH1 10mV
B
W
06197-128
06197-025
1
M10µs
T
30.0µs
CH1 100mV
Figure 30. AC Crosstalk at FOH0 in FI Mode from FIN DAC of Each Other PMU (FullScale Transition), MI Gain = 10, MEASOUTx Gain = 1, ±2 mA Range, CLOAD = 200 pF
Rev. A | Page 25 of 60
B
B
W CH3 5.00V W
CH4 5.00V BW
M2.00µs
CH4
T
6.0000µs
2.10V
Figure 33. Range Change, PMU 0, ±5 μA to ±2 mA, CLOAD = 1 nF,
RLOAD = 620 kΩ, FV = 3 V
AD5522
SYNC
4
3
4
BUSY
SYNC
BUSY
3
FOH0
FOH0
CH1 50.0mV
B CH3 5.00V B
W
W
CH4 5.00V BW
M800ns
CH4
T
2.40000µs
06197-132
1
06197-129
1
CH1 100.0mV
2.10V
Figure 34. Range Change, PMU 0, ±2 mA to ±5 μA, CLOAD = 1 nF,
RLOAD = 620 kΩ, FV = 3 V
M2.00µs
CH4
T
6.00000µs
2.10V
Figure 37. Range Change, PMU 0, ±20 μA to ±2 mA, CLOAD = 1 nF,
RLOAD = 150 kΩ, FV = 3 V
SYNC
SYNC
4
3
B
B
W CH3 5.00V W
CH4 5.00V BW
4
BUSY
3
BUSY
FOH0
FOH0
CH1 20.0mV
B CH3 5.00V B
W
W
CH4 5.00V BW
M20.0µs
CH4
T
60.0000µs
06197-133
1
06197-130
1
CH1 50.0mV
2.10V
Figure 35. Range Change, PMU 0, ±5 μA to ±2 mA, CLOAD = 100 nF,
RLOAD = 620 kΩ, FV = 3 V
B CH3 5.00V B
W
W
CH4 5.00V BW
M2.000µs
CH4
T
6.00000µs
2.10V
Figure 38. Range Change, PMU 0, ±2 mA to ±20 μA, CLOAD = 1 nF,
RLOAD = 150 kΩ, FV = 3 V
SYNC
4
SYNC
4
BUSY
3
BUSY
3
FOH0
MEASOUTx (MI)
2
1
FOHx
CH1 20.0mV
B CH3 5.00V B
W
W
CH4 5.00V BW
M20.0µs
CH4
T
60.0000µs
06197-134
06197-131
1
CH1 2.00V
CH3 5.00V
2.10V
CH2 2.00V
CH4 5.00V
M10.0µs
CH1
3.84V
Figure 39. FV Settling, 0 V to 5 V, ±2 mA Range, CLOAD = 220 pF,
CCOMPx = 1 nF, RLOAD = 5.6 kΩ
Figure 36. Range Change, PMU 0, ±2 mA to ±5 μA, CLOAD = 100 nF,
RLOAD = 620 kΩ, FV = 3 V
Rev. A | Page 26 of 60
AD5522
SYNC
SYNC
4
4
BUSY
BUSY
3
3
MEASOUTx (MI)
MEASOUTx (MI)
2
2
FOHx
FOHx
1
06197-135
06197-137
1
CH1 2.00V
CH3 5.00V
CH2 2.00V
CH4 5.00V
M5.0µs
CH1
CH1 2.00V
CH3 5.00V
3.84V
CH2 10.0V
CH4 5.00V
M25.0µs
CH1
3.20V
Figure 42. FV Settling, 0 V to 5 V, ±20 μA Range, CLOAD = 220 pF,
CCOMPx = 100 pF, RLOAD = 270 kΩ
Figure 40. FV Settling, 0 V to 5 V, ±2 mA Range, CLOAD = 220 pF,
CCOMPx = 100 pF, RLOAD = 5.6 kΩ
SYNC
SYNC
4
4
BUSY
BUSY
3
3
MEASOUTx (MI)
MEASOUTx (MI)
2
2
FOHx
FOHx
1
06197-136
06197-138
1
CH1 2.00V
CH3 5.00V
CH2 10.00V
CH4 5.00V
M100µs
CH1
CH1 2.00V
CH3 5.00V
3.20V
CH2 10.0V
CH4 5.00V
M10.0µs
CH1
3.20V
Figure 43. FV Settling, 0 V to 5 V, ±200 μA Range, CLOAD = 220 pF,
CCOMPx = 100 pF, RLOAD = 27 kΩ
Figure 41. FV Settling, 0 V to 5 V, ±5 μA Range, CLOAD = 220 pF,
CCOMPx = 100 pF, RLOAD = 1 MΩ
Rev. A | Page 27 of 60
AD5522
TERMINOLOGY
Offset Error
Offset error is a measure of the difference between the actual
voltage and the ideal voltage at midscale or at zero current
expressed in mV or % FSR.
Gain Error
Gain error is the difference between full-scale error and zeroscale error. It is expressed in % FSR.
Gain Error = Full-Scale Error − Zero-Scale Error
where:
Full-Scale Error is the difference between the actual voltage and
the ideal voltage at full scale.
Zero-Scale Error is the difference between the actual voltage and
the ideal voltage at zero scale.
Linearity Error
Linearity error, or relative accuracy, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the full-scale range. It is measured after adjusting
for gain error and offset error and is expressed in % FSR.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.
Pin Capacitance
Pin capacitance is the capacitance measured at a pin when that
function is off or high impedance.
Slew Rate
The slew rate is the rate of change of the output voltage
expressed in V/μs.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a full-scale
input change.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the amount of energy that is
injected into the analog output at the major code transition. It
is specified as the area of the glitch in nV-s. It is measured by
toggling the DAC register data between 0x7FFF and 0x8000.
Digital Crosstalk
Digital crosstalk is defined as the glitch impulse transferred to
the output of one converter due to a change in the DAC register
code of another converter. It is specified in nV-s.
AC Crosstalk
AC crosstalk is defined as the glitch impulse transferred to the
output of one PMU due to a change in any of the DAC registers
in the package.
ACPSRR
Common-Mode (CM) Error
Common-mode (CM) error is the error at the output of the
amplifier due to the common-mode input voltage. It is
expressed in % of FSVR/V.
Leakage Current
Leakage current is the current measured at an output pin when
that function is off or high impedance.
ACPSRR is a measure of the ability of the device to avoid
coupling noise and spurious signals that appear on the supply
voltage pin to the output of the switch. The dc voltage on the
device is modulated by a sine wave of 0.2 V p-p. The ratio of the
amplitude of the signal on the output to the amplitude of the
modulation is the ACPSRR.
Rev. A | Page 28 of 60
AD5522
THEORY OF OPERATION
The AD5522 is a highly integrated, quad per-pin parametric
measurement unit (PPMU) for use in semiconductor automated
test equipment. It provides programmable modes to force a pin
voltage and measure the corresponding current (FVMI) and to
force a pin current and measure the corresponding voltage. The
device is also capable of all other combinations, including force
high-Z and measure high-Z. The PPMU can force or measure a
voltage range of 22.5 V. It can force or measure currents up to
±80 mA per channel using the internal amplifier; the addition
of an external amplifier enables higher current ranges. All the
DAC levels required for each PMU channel are on chip.
FORCE AMPLIFIER
The force amplifier drives the analog output FOH, which drives
a programmed current or voltage to the DUT (device under
test). Headroom and footroom requirements for this amplifier
are 3 V on either end. An additional ±1 V is dropped across the
sense resistor when maximum (rated) current is flowing
through it.
The force amplifier is designed to drive DUT capacitances up
to 10 nF, with a compensation value of 100 pF. Larger DUT
capacitive loads require larger compensation capacitances.
Local feedback ensures that the amplifiers are stable when
disabled. A disabled channel reduces power consumption by
2.5 mA per channel.
COMPARATORS
Per channel, the DUT measured voltage or current is monitored
by two comparators configured as window comparators. Internal
DAC levels set the CPL (comparator low) and CPH (comparator
high) threshold values. There are no restrictions on the voltage
settings of the comparator highs and lows. CPL going higher
than CPH is not a useful operation; however, it does not cause
any problems with the device. CPOLx (comparator output low)
and CPOHx (comparator output high) are continuous time
comparator outputs.
window. Information on whether the measurement was high or
low is available via the serial interface (comparator status register).
Table 9. Comparator Output Function Using LVDS Interface
Test Condition
(CPL < (VDUT or IDUT)) and ((VDUT or IDUT) < CPH)
(CPL > (VDUT or IDUT)) or ((VDUT or IDUT) > CPH)
CLAMPS
Current and voltage clamps are included on chip, one clamp for
each PMU channel. The clamps protect the DUT in the event of
an open-circuit or short-circuit condition. Internal DAC levels
set the CLL (clamp low) and CLH (clamp high) levels. The clamps
work to limit the force amplifier if a voltage or current at the
DUT exceeds the set levels. The clamps also protect the DUT if
a transient voltage or current spike occurs when changing to a
different operating mode or when programming the device to a
different current range.
The voltage clamps are available while forcing current, and the
current clamps are available while forcing voltage. The user can
set up the clamp status using the serial interface (system control
register or PMU register).
Each clamp has a smooth, finite transition region between
normal (unclamped) operation and the final clamped level, and
an internal flag is activated within this transition zone. The
open-drain CGALM pin indicates whether one or more PMU
channels has clamped. The clamp status of an individual PMU
can be determined by polling the alarm status register using the
SPI or LVDS interface.
CLL should never be greater than CLH. For the voltage clamps,
there should be 500 mV between the CLL and CLH levels to
ensure that a region exists in the middle of the clamps where
both are off. Similarly, set current clamps ±250 mV away from 0 A.
The transfer function for voltage clamping in FI mode is
VCLL or VCLH = 4.5 × VREF × (DAC_CODE/216) −
(3.5 × VREF × (OFFSET_DAC_CODE/216)) + DUTGND
Table 8. Comparator Output Function Using SPI Interface
Test Condition
VDUT or IDUT > CPH
VDUT or IDUT < CPH
VDUT or IDUT > CPL
VDUT or IDUT < CPL
CPH > VDUT or IDUT > CPL
CPOLx
1
0
1
CPOHx
0
1
CPOx Output
1
0
See the DAC Levels section for more information.
The transfer function for current clamping in FV mode is
ICLL or ICLH = 4.5 × VREF × ((DAC_CODE −
32,768)/216)/(RSENSE × MI_Amplifier_Gain)
1
When using the SPI interface, full comparator functionality is
available. When using the LVDS interface, the comparator
function is limited to one output per comparator, due to the
large pin count requirement of the LVDS interface.
When using the LVDS interface, the comparator output available
pins, CPO0 to CPO3, provide information on whether the measured voltage or current is inside or outside the set CPH and CPL
where:
RSENSE is the sense resistor of the selected current range.
MI_Amplifier_Gain is the gain of the measure current
instrumentation amplifier, either 5 or 10.
Do not change clamp levels while the channel is in force mode
because this can affect the forced voltage or current applied to
the DUT. Similarly, the clamps should not be enabled or
disabled during a force operation.
Rev. A | Page 29 of 60
AD5522
In the ±200 μA range with the 5 kΩ sense resistor and an ISENSE
gain of 10, the maximum current range possible is ±225 μA.
Similarly, for the other current ranges, there is an overrange of
12.5% to allow for error correction.
CURRENT RANGE SELECTION
Integrated thin film resistors minimize the need for external
components and allow easy selection of any of these current
ranges: ±5 μA (200 kΩ), ±20 μA (50 kΩ), ±200 μA (5 kΩ), and
±2 mA (500 Ω). One current range up to ±80 mA can be
accommodated per channel by connecting an external sense
resistor. For current ranges in excess of ±80 mA, it is necessary
that an external amplifier be used.
Also, the forced current range is the quoted full-scale range only
with an applied reference of 5 V or 2.5 V (with ISENSE amplifier
gain = 5). The ISENSE amplifier is biased by the VMID DAC
voltage in such a way as to center the measure current output
irrespective of the voltage span used.
For the suggested current ranges, the maximum voltage drop
across the sense resistors is ±1 V. However, to allow for error
correction, there is some overrange available in the current
ranges (±12.5% or ±0.125 V across RSENSE). The full-scale
voltage range that can be loaded to the FIN DAC is ±11.5 V;
the forced current can be calculated as follows:
When using the EXTFOHx outputs for current ranges up to
±80 mA, there is no switch in series with the EXTFOHx line,
ensuring minimum capacitance present at the output of the
force amplifier. This feature is important when using a pin
electronics driver to provide high current ranges.
FI = 4.5 × VREF × ((DAC_CODE − 32,768)/216)/(RSENSE ×
MI_Amplifier_Gain)
HIGH CURRENT RANGES
With the use of an external high current amplifier, one high
current range in excess of ±80 mA is possible. The high current
amplifier buffers the force output and provides the drive for the
required current. The AD8397 is a dual high current output
amplifier (300 mA depending on supply conditions). To achieve
full swing from this amplifier, it should be used with a gain of 2
or more, thus requiring a voltage divider at the output of
EXTFOHx. This amplifier is available in an SOIC exposed pad
package which is well-suited to high power applications.
where:
FI is the forced current.
RSENSE is the selected sense resistor.
MI_Amplifier_Gain is the gain of the measure current
instrumentation amplifier. This gain can be set to 5 or 10
via the serial interface.
To eliminate any timing concerns when switching between the
internal ranges and the external high current range, there is a
mode where the internal ±80 mA stage can be enabled at all
times. See Table 25 for more information.
HIGH
CURRENT
AMPLIFIER
EN
EXTFOHx
CFFx
INTERNAL RANGE SELECT
(±5µA, ±20µA, ±200µA, ±2mA)
DAC
FIN
+
FOHx
RSENSE
–
4kΩ
VMID TO
CENTER
I RANGE
×5 or ×10
–
EXTMEASILx
+
–
4kΩ
MEASVHx
AGND
+
–
DUT
+
DUTGND
×1
–
+
–
Figure 44. Addition of High Current Amplifier for Wider Current Range (>±80 mA)
Rev. A | Page 30 of 60
06197-028
×1 OR
×0.2
RSENSE
2kΩ
+
MEASOUTx
EXTMEASIHx
+
–
AD5522
VREF = 3.5 V results in a ±7.87 V range. Using a gain setting of
10, there is ±0.785 V maximum across RSENSE, resulting in
current ranges of ±3.92 μA, ±15.74 μA, and so on (including
overrange of ±12.5% to allow for error correction).
MEASURE CURRENT GAINS
The measure current amplifier has two gain settings, 5 and 10.
The two gain settings allow users to achieve the quoted/specified
current ranges with large or small voltage swing. Use the 10 gain
setting with a 5 V reference, and use the 5 gain setting with a
2.5 V reference. Both combinations ensure the specified current
ranges. Using other VREF/gain setting combinations should
achieve smaller current ranges only. Achieving greater current
ranges than the specified ranges is outside the intended
operation of the AD5522. The maximum guaranteed voltage
across RSENSE = ±1.125 V.
VMID VOLTAGE
The midcode voltage (VMID) is used in the measure current
amplifier block to center the current ranges about 0 A. This
is required to ensure that the quoted current ranges can be
achieved when using offset DAC settings other than the default.
VMID corresponds to 0x8000 or the DAC midcode value, that
is, the middle of the voltage range set by the offset DAC setting
(see Table 13). See the block diagram in Figure 45.
Following are examples of VREF/gain setting combinations. In
these examples, the offset DAC is at its default value of 0xA492.
•
VREF = 5 V results in a ±11.25 V range. Using a gain setting
of 10, there is ±1.125 V maximum across RSENSE, resulting in
current ranges of ±5.625 μA, ±22.5 μA, and so on (including overrange of ±12.5% to allow for error correction).
VREF = 2.5 V results in a ±5.625 V range. Using a gain setting
of 5 results in current ranges of ±5.625 μA, ±22.5 μA, and
so on (including overrange of ±12.5% to allow for error
correction).
or
VMID = 3.5 × VREF × ((42,130 − OFFSET_DAC_CODE)/216)
VMIN = −3.5 × VREF × (OFFSET_DAC_CODE/216)
VREF
VTOP
VDAC_MID
VMID
DATA
ADDRESS
DAC
DAC HV AMP
VOFFSET
2R
7R
VDAC_MIN
VMIN
REFGND
DAC HV AMP
VOFFSET
2R
10R
7R
MEASURE
CURRENT
IN-AMP
SEL×10
ATTB
SEL×5
1R
ATT
5R
INAMP10
MEASOUTx
50Ω
INT/EXTMEASIHx
1R
1R
INT/EXTMEASILx
1R
MI
5R
10R
SEL×5
ATTB
SEL×10
1R
ATTB
AGND
1R
MEASVHx
5R
INAMP1
ATT
MV
DUTGND
1R
1R
R
AGND
ATT = ATTENUATION FOR MEASOUTx ×0.2
MI = MEASURE CURRENT
MV = MEASURE VOLTAGE
SEL×5 = MI GAIN = 5
SEL×10 = MI GAIN = 10
Figure 45. Measure Block and VMID Influence
Rev. A | Page 31 of 60
MEASURE
VOLTAGE
IN-AMP
06197-043
•
VMID = 4.5 × VREF × (32,768/216) − (3.5 × VREF ×
(OFFSET_DAC_CODE/216))
AD5522
CHOOSING POWER SUPPLY RAILS
MEASURE OUTPUT (MEASOUTx PINS)
As noted in the Specifications section, the minimum supply
variation across the part |AVDD − AVSS| ≥ 20 V. For the
AD5522 circuits to operate correctly, the supply rails must take
into account not only the force voltage range, but also the
internal DAC minimum voltage level, as well as headroom and
so on. The DAC amplifier gains VREF by 4.5, and the offset
DAC centers that range about some chosen point.
The measured DUT voltage or current (voltage representation
of DUT current) is available on the MEASOUTx pin with respect
to AGND. The default MEASOUTx range is the forced voltage
range for voltage measure and current measure (nominally
±11.25 V, depending on the reference voltage and offset DAC)
and includes some overrange to allow for offset correction.
The supplies need to cater to the DAC output voltage range to
avoid impinging on other parts of the circuit (for example, if the
measure current block for rated current ranges has a gain of
10/5, the supplies need to provide sufficient headroom and
footroom to not clip the measure current circuit when full
current range is required).
Also, the measout gain = 0.2 setting uses the VMIN level for
scaling purposes; if there is not enough footroom for this
VMIN level, then the MV and MI output voltage range is
affected.
The serial interface allows the user to select another MEASOUTx
range of 0.9 × VREF to AGND, allowing an ADC with a 5 V
input range to be used. The MEASOUTx line for each PMU
channel can be made high impedance via the serial interface.
The offset DAC directly offsets the measured output voltage level,
but only when GAIN1 = 0. When the MEASOUTx gain is 0.2, the
minimum code from the DAC is used to center the MEASOUTx
voltage and to ensure that the voltage is within the range of 0 to
0.9 × VREF (see Figure 45).
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the DAC output range (set by the
VREF and offset DAC setting).
For the measout gain = 0.2 setting, it is important to choose
AVSS based on the following:
DEVICE UNDER TEST GROUND (DUTGND)
AVSS ≤ −3.5 × (VREF × (OFFSET_DAC_CODE/216)) −
AVSS_footroom − VDUTGND − (RCABLE × ILOAD)
By default, there is one DUTGND input available for all four
PMU channels. However, in some PMU applications, it is
necessary that each channel operate from its own DUTGND
level. The dual function pin, GUARDINx/DUTGNDx, can be
configured as an input to the guard amplifier (GUARDIN) or
as a DUTGND input for each channel.
where:
AVSS_footroom = 4 V.
VDUTGND is the voltage range anticipated at DUTGND.
RCABLE is the cable/path resistance.
ILOAD is the maximum load current.
The pin function can be configured through the serial interface
on power-on for the required operation. The default connection
is SW13b (GUARDIN) and SW14b (shared DUTGND).
Table 10. MEASOUTx Output Ranges for GAIN1 = 0, MEASOUT Gain = 1
MEASOUT
Function
MV
MI
GAIN0 = 0
GAIN0 = 1
1
Output Voltage Range for VREF = 5 V 1
Offset DAC = 0x0
Offset DAC = 0xA492 Offset DAC = 0xED67
0 V to 22.5 V
±11.25 V
−16.26 V to +6.25 V
Measure
Current Gain
5 or 10
Transfer Function
±VDUT
10
5
(IDUT × RSENSE × 10) + VMID
(IDUT × RSENSE × 5) + VMID
0 V to 22.5 V
0 V to 11.25 V
(VREF = 2.5 V)
±11.25 V
±5.625 V
(VREF = 2.5 V)
−16.26 V to +6.25 V
−8.13 V to +3.12 V
(VREF = 2.5 V)
VREF = 5 V unless otherwise noted.
Table 11. MEASOUTx Output Ranges for GAIN1 = 1, MEASOUT Gain = 0.2
MEASOUT
Function
MV
MI
GAIN0 = 0
GAIN0 = 1
1
2
Measure
Current Gain
5 or 10
Transfer Function
VDUT × 0.2 + (0.45 × VREF)
Output Voltage Range for VREF = 5 V 1, 2
0 V to 4.5 V (±2.25 V centered around 2.25 V)
10
5
(IDUT × RSENSE × 10 × 0.2) + (0.45 × VREF)
(IDUT × RSENSE × 5 × 0.2) + (0.45 × VREF)
0 V to 4.5 V (±2.25 V centered around 2.25 V)
1.125 V to 3.375 V (±1.125 V, centered around 2.25 V)
0 V to 2.25 V (±1.125 V, centered around 1.125 V)
(VREF = 2.5 V)
VREF = 5 V unless otherwise noted.
The offset DAC setting has no effect on the output voltage range.
Rev. A | Page 32 of 60
AD5522
When configured as DUTGND per channel, this dual function
pin is no longer connected to the input of the guard amplifier.
Instead, it is connected to the low end of the instrumentation
amplifier (SW14a), and the input of the guard amplifier is
connected internally to MEASVHx (SW13a).
MEASVH[0:3]
+
–
a
SW13
AGND
SW14 a
b GUARD GUARD[0:3]
AMP
GUARDIN[0:3]/
DUTGND[0:3]
+
–
b
DUTGND
MEASURE
VOLTAGE
IN-AMP
06197-029
+
x1
–
DUT
SW16
capacitances must be driven, an external multiplexer connected
to the CCOMP pin allows optimization of settling time vs.
stability. The series resistance of a switch placed on CCOMP
should typically be <50 Ω.
Suitable multiplexers for use here are the ADG1404, ADG1408,
or one of the multiplexers in the ADG4xx family which
typically have on resistances less than 50 Ω.
Similarly, connecting the CFF node to an external multiplexer
accommodates a wide range of CDUT in FV mode. The
ADG1204 or ADG1209 family of multiplexers meet these
requirements. The series resistance of the multiplexer used
should be such that
1/(2π × RON × CDUT) > 100 kHz
Figure 46. Using the DUTGND per Channel Feature
Table 12. Suggested Compensation Capacitor Selection
GUARD AMPLIFIER
A guard amplifier allows the user to bootstrap the shield of the
cable to the voltage applied to the DUT, ensuring minimal drops
across the cable. This is particularly important for measurements
requiring a high degree of accuracy and in leakage current testing.
If not required, all four guard amplifiers can be disabled via the
serial interface (system control register). Disabling the guard
amplifiers decreases power consumption by 400 μA per channel.
As described in the Device Under Test Ground (DUTGND)
section, GUARDINx/DUTGNDx are dual function pins. Each
pin can function either as a guard amplifier input for one
channel or as a DUTGND input for one channel, depending
on the requirements of the end application (see Figure 46).
CLOAD
≤1 nF
≤10 nF
≤100 nF
CCOMP
100 pF
100 pF
CLOAD/100
CFF
220 pF
1 nF
CLOAD/10
SYSTEM FORCE AND SENSE SWITCHES
Each channel has switches to allow connection of the force
(FOHx) and sense (MEASVHx) lines to a central PMU for
calibration purposes. There is one set of SYS_FORCE and
SYS_SENSE pins per device. It is recommended that these
connections be made individually to each PMU channel.
FOH0
A guard alarm event occurs when the guard output moves more
than 100 mV away from the guard input voltage for more than
200 μs. In this case, the event is flagged via the open-drain
output CGALM. Because the guard and clamp alarm functions
share the same alarm output, CGALM, the alarm information
(alarm trigger and alarm channel) is available via the serial
interface in the alarm status register.
FOH1
SYS_FORCE
FOH2
FOH3
MEASVH0
MEASVH1
Alternatively, the serial interface allows the user to set up the
CGALM output to flag either the clamp status or the guard
status. By default, this open-drain alarm pin is an unlatched
output, but it can be configured as a latched output via the serial
interface (system control register).
Figure 47. SYS_FORCE and SYS_SENSE Connections to FOHx and MEASVHx Pins
COMPENSATION CAPACITORS
TEMPERATURE SENSOR
Each channel requires an external compensation capacitor
(CCOMP) to ensure stability into the maximum load capacitance
while ensuring that settling time is optimized. In addition, one
CFF pin per channel is provided to further optimize stability
and settling time performance when in force voltage (FV) mode.
When changing from force current (FI) mode to FV mode, the
switch connecting the CFF capacitor is automatically closed.
An on-board temperature sensor monitors die temperature. The
temperature sensor is located at the center of the die. If the
temperature exceeds the factory specified value (130°C) or a
user programmable value, the device protects itself by shutting
down all channels and flagging an alarm through the latched,
open-drain TMPALM pin. Alarm status can be read back from
the alarm status register or the PMU register, where latched and
unlatched bits indicate whether an alarm has occurred and
whether the temperature has dropped below the set alarm
temperature. The shutdown temperature is set using the system
control register.
Although the force amplifier is designed to drive load capacitances
up to 10 nF (with CCOMP = 100 pF), it is possible to use larger
compensation capacitor values to drive larger loads, at the
expense of an increase in settling time. If a wide range of load
MEASVH3
Rev. A | Page 33 of 60
06197-042
SYS_SENSE
MEASVH2
AD5522
DAC LEVELS
Each channel contains five dedicated DAC levels: one for the
force amplifier, one each for the clamp high and clamp low levels,
and one each for the comparator high and comparator low levels.
The power supplies should be selected to support the required
range and should take into account amplifier headroom and
footroom and sense resistor voltage drop (±4 V).
The architecture of a single DAC channel consists of a 16-bit
resistor-string DAC followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity. The
16-bit binary digital code loaded to the DAC register determines
at which node on the string the voltage is tapped off before
being fed into the output amplifier.
Therefore, depending on the headroom available, the input to
the force amplifier can be unipolar positive or bipolar, either
symmetrical or asymmetrical about DUTGND, but always
within a voltage span of 22.5 V.
The transfer function for DAC outputs is as follows:
VOUT = 4.5 × VREF × (X2/216) − (3.5 × VREF ×
(OFFSET_DAC_CODE/216)) + DUTGND
where:
VREF is the reference voltage and is in the range of 2 V to 5 V.
X2 is the calculated DAC code value and is in the range
of 0 to 65,535 (see the Gain and Offset Registers section).
OFFSET_DAC_CODE is the code loaded to the offset DAC. It is
multiplied by 3.5 in the transfer function. On power-up, the
default code loaded to the offset DAC is 0xA492; with a 5 V
reference, this gives a span of ±11.25 V.
OFFSET DAC
The AD5522 is capable of forcing a 22.5 V (4.5 × VREF) voltage
span. Included on chip is one 16-bit offset DAC (one for all four
channels) that allows for adjustment of the voltage range.
The usable range is −16.25 V to +22.5 V. Zero scale loaded to
the offset DAC gives a full-scale range of 0 V to 22.5 V, midscale
gives ±11.25 V, and the most useful negative range is −16.25 V
to +6.25 V. Full scale loaded to the offset DAC does not give a
useful output voltage range, because the output amplifiers are
limited by the available footroom. Table 13 shows the effect of
the offset DAC on the other DACs in the device.
Table 13. Relationship of Offset DAC to Other DACs
(VREF = 5 V)
Offset DAC Code
0
32,768
42,130
60,855
65,535
DAC Code
0
32,768
65,535
0
32,768
65,535
0
32,768
65,535
0
32,768
65,535
DAC Output Voltage (V)
0
+11.25
+22.50
−8.75
+2.50
+13.75
−11.25
0
+11.25
−16.25
−5.00
+6.25
Footroom limitations
The offset DAC offsets all DAC functions. It also centers the
current range so that zero current always flows at midscale
code, regardless of the offset DAC setting.
Rearranging the transfer function for the DAC output gives the
following equation to determine which offset DAC code is
required for a given reference and output voltage range.
OFFSET_DAC_CODE = (216 × (VOUT − DUTGND))/(3.5 ×
VREF) − ((4.5 × DAC_CODE)/3.5)
When the output range is adjusted by changing the default value
of the offset DAC, an extra offset is introduced due to the gain
error of the offset DAC channel. The amount of offset is dependent on the magnitude of the reference and how much the
offset DAC channel deviates from its default value. See the
Specifications section for this offset. The worst-case offset
occurs when the offset DAC channel is at positive or negative
full scale. This value can be added to the offset present in the
main DAC channel to give an indication of the overall offset
for that channel. In most cases, the offset can be removed by
programming the C register of the channel with an appropriate
value. The extra offset caused by the offset DAC needs to be
taken into account only when the offset DAC is changed from
its default value.
GAIN AND OFFSET REGISTERS
Each DAC level has an independent gain (M) register and an
independent offset (C) register, which allow trimming out of
the gain and offset errors of the entire signal chain, including
the DAC. All registers in the AD5522 are volatile, so they must
be loaded on power-on during a calibration cycle. Data from
the X1 register is operated on by a digital multiplier and adder
controlled by the contents of the M and C registers. The
calibrated DAC data is then stored in the X2 register.
The digital input transfer function for each DAC can be
represented as follows:
X2 = [(M + 1)/2n × X1] + (C − 2n − 1)
where:
X2 is the data-word loaded to the resistor-string DAC.
X1 is the 16-bit data-word written to the DAC input register.
M is the code in gain register (default code = 216 − 1).
C is the code in offset register (default code = 215).
n is the DAC resolution (n = 16).
Rev. A | Page 34 of 60
AD5522
CACHED X2 REGISTERS
Each DAC has a number of cached X2 registers. These registers
store the result of a gain and offset calibration in advance of a mode
change. This enables the user to preload registers, allowing the
calibration engine to calculate the appropriate X2 value and store
it until a change in mode occurs. Because the data is ready and
held in the appropriate register, mode changing is as time efficient
as possible. If an update occurs to a DAC register set that is
currently part of the operating PMU mode, the DAC output is
updated immediately (depending on the LOAD condition).
Gain and Offset Registers for the Clamp DACs
The clamp DAC levels contain independent gain and offset
control registers that allow the user to digitally trim gain and
offset. There are two sets of X1, M, and C registers: one set for
the force voltage mode and one set for all five current ranges.
Two X2 registers store the calculated DAC values, ready to load
to the DAC register upon a PMU mode change.
VREF
16
16
16
16
OFFSET DAC
VREF
SERIAL I/F
16
X2 REG
16-BIT
FIN DAC
FIN
06197-030
X1 REG
M REG
C REG ×6
Figure 48. FIN DAC Registers
Gain and Offset Registers for the Comparator DACs
The comparator DAC levels contain independent gain and
offset control registers that allow the user to digitally trim gain
and offset. There are six sets of X1, M, and C registers: one set
for the force voltage mode and one set for each force current
range (four internal current ranges and one external current
range). In this way, X2 can be preprogrammed, which allows for
efficient switching into the required compare mode. Six X2
registers store the calculated DAC values, ready to load to the
DAC register upon a PMU mode change.
16
16
16
X2 REG
X1 REG
M REG
C REG ×6
X2 REG
SERIAL I/F
X1 REG
M REG
C REG
X2 REG
16-BIT
16 CLL DAC
CLL
×2
16
16-BIT
CPH DAC
CPH
16
16-BIT
CPL DAC
CPL
REFERENCE VOLTAGE (VREF)
One buffered analog input, VREF, supplies all 21 DACs with the
necessary reference voltage to generate the required dc levels.
REFERENCE SELECTION
The voltage applied to the VREF pin determines the output
voltage range and span applied to the force amplifier, clamp, and
comparator inputs. The AD5522 can be used with a reference
input ranging from 2 V to 5 V; however, for most applications,
a reference input of 5 V or 2.5 V is sufficient to meet all voltage
range requirements. The DAC amplifier gain is 4.5, which gives
a DAC output span of 22.5 V. The DACs have gain and offset
registers that can be used to trim out system errors.
In addition, the gain register can be used to reduce the DAC
output range to the desired force voltage range. The FIN DAC
retains 16-bit resolution even with a gain register setting of
quarter scale (0x4000). Therefore, from a single 5 V reference,
it is possible to obtain a voltage span as high as 22.5 V or as low
as 5.625 V.
When using the gain and offset registers, the selected output
range should take into account the system gain and offset errors
that need to be trimmed out. Therefore, the selected output
range should be larger than the actual required range.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
Also, the forced current range is the quoted full-scale range only
with an applied reference of 5 V (ISENSE amplifier gain = 10) or
2.5 V (ISENSE amplifier gain = 5).
16
16
16
CLH
SERIAL I/F
06197-031
VREF
X1 REG
M REG
C REG ×6
X2 REG
Figure 50. Clamp Registers
The force amplifier input (FIN) DAC level contains independent
gain and offset control registers that allow the user to digitally
trim gain and offset. There are six sets of X1, M, and C registers:
one set for the force voltage range and one set for each force
current range (four internal current ranges and one external
current range). Six X2 registers store the calculated DAC values,
ready to load to the DAC register upon a PMU mode change.
16
16-BIT
CLH DAC
16
X1 REG
M REG
C REG ×2
16
Gain and Offset Registers for the FIN DAC
16
16
16
06197-032
The calibration engine is engaged only when data is written to
the X1 register. The calibration engine is not engaged when data
is written to the M or C register. This has the advantage of
minimizing the initial setup time of the device. To calculate a
result that includes new M or C data, a write to X1 is required.
Figure 49. Comparator Registers
Rev. A | Page 35 of 60
AD5522
Table 14. References Suggested For Use with AD5522 1
Part No.
ADR435
ADR445
ADR431
ADR441
1
Voltage (V)
5
5
2.5
2.5
Initial
Accuracy %
0.04
0.04
0.04
0.04
Ref Out
TC (ppm/°C)
1
1
1
1
Ref Output
Current (mA)
30
10
30
10
Supply Voltage
Range (V)
+7 to +18
+5.5 to +18
+4.5 to +18
+3 to +18
Package
MSOP, SOIC
MSOP, SOIC
MSOP, SOIC
MSOP, SOIC
Subset of the possible references suitable for use with the AD5522. Visit www.analog.com for more options.
For other voltage and current ranges, the required reference
level can be calculated as follows:
1.
2.
3.
4.
5.
Identify the nominal range required.
Identify the maximum offset span and the maximum gain
required on the full output signal range.
Calculate the new maximum output range, including the
expected maximum gain and offset errors.
Choose the new required VOUTMAX and VOUTMIN, keeping
the VOUT limits centered on the nominal values. Note that
AVDD and AVSS must provide sufficient headroom.
Calculate the value of VREF as follows:
VREF = (VOUTMAX − VOUTMIN)/4.5
Reference Selection Example
In this case, the optimum reference is a 2.5 V reference; the user
can use the M and C registers and the offset DAC to achieve the
required −2 V to +8 V range. Change the ISENSE amplifier gain to
5 to ensure a full-scale current range of the specified values (see
the Current Range Selection section). This gain also allows optimization of power supplies and minimizes power consumption
within the device.
It is important to bear in mind when choosing a reference value
that values other than 5 V (MI gain= 10) and 2.5 V (MI gain=
5) result in current ranges other than those specified. See the
Measure Current Gains section for more details.
CALIBRATION
Offset error = ±100 mV
Calibration involves determining the gain and offset of each
channel in each mode and overwriting the default values in the
M and C registers of the individual DACs. In some cases (for
example, FI mode), the calibration constants, particularly those
for gains, may be range dependent.
Gain error = ±0.5%, and
Reducing Zero-Scale Error
REFGND = AGND = 0 V
Zero-scale error can be reduced as follows:
Then
1.
2.
If
Nominal output range = 10 V (−2 V to +8 V)
Gain error = ±0.5%
=> Maximum positive gain error = +0.5%
=> Output range including gain error = 10 V + 0.005(10 V) =
10.05 V
3.
Set the output to the lowest possible value.
Measure the actual output voltage and compare it to the
required value. This gives the zero-scale error.
Calculate the number of LSBs equivalent to the zero-scale
error and add this number to the default value of the C
register. Note that only negative zero-scale error can be
reduced.
Offset error = ±100 mV
=> Maximum offset error span = 2(100 mV) = 0.2 V
=> Output range including gain error and offset error =
10.05 V + 0.2 V = 10.25 V
Reducing Gain Error
VREF calculation
Actual output range = 10.25 V, that is, −2.125 V to +8.125 V
(centered);
VREF = (8.125 V + 2.125 V)/4.5 = 2.28 V
1.
2.
3.
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
4.
•
•
•
Gain error can be reduced as follows:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select a convenient reference level above VREF and modify
the gain and offset registers to digitally downsize the reference.
In this way, the user can use almost any convenient reference level.
Use a combination of these two approaches.
Measure the zero-scale error.
Set the output to the highest possible value.
Measure the actual output voltage and compare it to the
required value. This is the gain error.
Calculate the number of LSBs equivalent to the gain error
and subtract this number from the default value of the M
register. Note that only positive gain error can be reduced.
Calibration Example
Nominal offset coefficient = 32,768
Nominal gain coefficient = 65,535
For example, the gain error = 0.5%, and the offset error = 100 mV.
Rev. A | Page 36 of 60
AD5522
2.
Gain error (0.5%) calibration:
65,535 × 0.995 = 65,207
=> Load Code 1111 1110 1011 0111 to the M register.
Calibrate the measure voltage (2 points).
Connect SYS_FORCE to FOHx and SYS_SENSE to
MEASVHx, and close the internal force/sense switch (SW7).
Force voltage on FOHx via SYS_FORCE and measure the
voltage at MEASOUTx. The difference is the error between
the actual forced voltage and the voltage at MEASOUTx.
Offset error (100 mV) calibration:
LSB size = 10.25/65,535 = 156 μV;
Offset coefficient for 100 mV offset = 100/0.156 = 641 LSBs
=> Load Code 0111 1101 0111 1111 to the C register.
3.
The techniques described in the previous section are usually
sufficient to reduce the zero-scale and gain errors. However,
there are limitations whereby the errors may not be sufficiently
reduced. For example, the offset (C) register can only be used to
reduce the offset caused by negative zero-scale error. A positive
offset cannot be reduced. Likewise, if the maximum voltage is
below the ideal value, that is, a negative gain error, the gain (M)
register cannot be used to increase the gain to compensate for
the error. These limitations can be overcome by increasing the
reference value.
Calibrate the force current (2 points).
In FI mode, write zero scale to the FIN DAC. Connect
SYS_FORCE to an external ammeter and to the FOHx pin.
Measure the error between the ammeter reading and the
MEASOUTx reading. Repeat this step with full scale
loaded to the FIN DAC. Calculate the M and C values.
4.
Calibrate the measure current (2 points).
In FI mode, write zero scale to the FIN DAC. Connect
SYS_FORCE to an external ammeter and to the FOHx pin.
Measure the error between the ammeter reading and the
MEASOUTx reading. Repeat this step with full scale
loaded to the FIN DAC.
SYSTEM LEVEL CALIBRATION
5.
Repeat this procedure for all four channels.
There are many ways to calibrate the device on power-on.
Following is an example of how to calibrate the FIN DAC of the
device without a DUT or DUT board connected.
Similarly, calibrate the comparator and clamp DACs, and load
the appropriate gain and offset registers. Calibrating these
DACs requires some successive approximation to find where
the comparator trips or the clamps engage.
Additional Calibration
The calibration procedure for the force and measure circuitry is
as follows:
1.
Calibrate the force voltage (2 points).
In FV mode, write zero scale to the FIN DAC. Connect
SYS_FORCE to FOHx and SYS_SENSE to MEASVHx,
and close the internal force/sense switch (SW7).
Using the system PMU, measure the error between the
voltage at FOHx/MEASVHx and the desired value.
Similarly, load full scale to the FIN DAC and measure the
error between the voltage at FOHx/MEASVHx and the
desired value. Calculate the M and C values. Load these
values to the appropriate M and C registers of the FIN DAC.
Rev. A | Page 37 of 60
AD5522
CIRCUIT OPERATION
The forced voltage can be calculated as follows:
FORCE VOLTAGE (FV) MODE
Forced Voltage at DUT = VOUT
Most PMU measurements are performed in force voltage/measure
current (FVMI) mode, for example, when the device is used as a
device power supply, or in continuity or leakage testing. In force
voltage (FV) mode, the voltage forced is mapped directly to the
DUT. The measure voltage amplifier completes the loop, giving
negative feedback to the forcing amplifier (see Figure 51).
VOUT = 4.5 × VREF × (DAC_CODE/216) − (3.5 × VREF ×
(OFFSET_DAC_CODE/216)) + DUTGND
where:
VOUT is the voltage of the FIN DAC (see the DAC Levels
section).
EXTFOHx
CFFx
FORCE
AMPLIFIER
DAC
FIN
INTERNAL RANGE SELECT
(±5µA, ±20µA, ±200µA, ±2mA)
+
FOHx
RSENSE
–
VMID TO
CENTER
I RANGE
4kΩ
×5 or ×10
–
EXTMEASILx
+
–
4kΩ
MEASVHx
AGND
+
–
+
×1
–
DUT
DUTGND
+
–
MEASURE VOLTAGE AMPLIFIER
Figure 51. Forcing Voltage, Measuring Current
Rev. A | Page 38 of 60
06197-033
×1 OR
×0.2
RSENSE
(UP TO
±80mA)
2kΩ
+
MEASOUTx
EXTMEASIHx
+
–
AD5522
FORCE CURRENT (FI) MODE
where:
FI is the forced current.
RSENSE is the selected sense resistor.
MI_Amplifier_Gain is the gain of the measure current
instrumentation amplifier. This gain can be set to 5 or
10 via the serial interface.
In force current (FI) mode, the voltage at the FIN DAC is
converted to a current and is applied to the DUT. The feedback
path is the measure current amplifier, feeding back the voltage
measured across the sense resistor. MEASOUTx reflects the
voltage measured across the DUT (see Figure 52).
For the suggested current ranges, the maximum voltage drop
across the sense resistors is ±1 V. However, to allow for error
correction, there is some overrange available in the current
ranges. The maximum full-scale voltage range that can be
loaded to the FIN DAC is ±11.5 V. The forced current can be
calculated as follows:
The ISENSE amplifier is biased by the offset DAC output voltage in
such a way as to center the measure current output regardless of
the voltage span used.
In the ±200 μA range with the 5 kΩ sense resistor and an ISENSE
gain of 10, the maximum current range possible is ±225 μA.
Similarly, for the other current ranges, there is an overrange of
12.5% to allow for error correction.
FI = 4.5 × VREF × ((DAC_CODE − 32,768)/216)/(RSENSE ×
MI_Amplifier_Gain)
EXTFOHx
CFFx
FORCE
AMPLIFIER
DAC
FIN
INTERNAL RANGE SELECT
(±5µA, ±20µA, ±200µA, ±2mA)
+
FOHx
RSENSE
–
MEASURE CURRENT
AMPLIFIER
VMID TO
CENTER
I RANGE
4kΩ
×5 or ×10
–
EXTMEASILx
+
–
4kΩ
MEASVHx
AGND
+
–
+
×1
–
DUT
DUTGND
+
–
Figure 52. Forcing Current, Measuring Voltage
Rev. A | Page 39 of 60
06197-034
×1 OR
×0.2
RSENSE
(UP TO
±80mA)
2kΩ
+
MEASOUTx
EXTMEASIHx
+
–
AD5522
SERIAL INTERFACE
The AD5522 provides two high speed serial interfaces: an SPIcompatible interface operating at clock frequencies up to 50 MHz
and an EIA-644-compliant LVDS interface. To minimize both
the power consumption of the device and the on-chip digital
noise, the serial interface powers up fully only when the device
is being written to, that is, on the falling edge of SYNC.
SPI INTERFACE
The serial interface operates from a 2.3 V to 5.25 V DVCC supply
range. The SPI interface is selected when the SPI/LVDS pin is
held low. It is controlled by four pins, as described in Table 15.
Table 15. Pins That Control the SPI Interface
Pin
SYNC
SDI
SCLK
SDO
Description
Frame synchronization input
Serial data input pin
Clocks data in and out of the device
Serial data output pin for data readback (weak
SDO output driver, may require reduction in SCLK
frequency to correctly readback, see Table 2)
LVDS INTERFACE
The LVDS interface uses the same input pins, with the same
designations, as the SPI interface. In addition, four other pins
are provided for the complementary signals needed for differential operation, as described in Table 16.
Table 16. Pins That Control the LVDS Interface
Pin
SYNC
SYNC
SDI
SDI
SCLK
SCLK
SDO
SDO
Description
Differential frame synchronization signal
Differential frame synchronization signal
(complement)
Differential serial data input
Differential serial data input (complement)
Differential serial clock input
Differential serial clock input (complement)
Differential serial data output for data readback
Differential serial data output for data readback
(complement)
SERIAL INTERFACE WRITE MODE
The AD5522 allows writing of data via the serial interface to
every register directly accessible to the serial interface, that is,
all registers except the DAC registers.
The serial word is 29 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5522 by clock pulses
applied to SCLK. The first falling edge of SYNC starts the write
cycle. At least 29 falling clock edges must be applied to SCLK to
clock in 29 bits of data before SYNC is taken high again.
The input register addressed is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
taken low again.
RESET FUNCTION
Bringing the level-sensitive RESET line low resets the contents
of all internal registers to their power-on reset state (see the
Power-On Default section). This sequence takes approximately
600 μs. BUSY goes low for the duration, returning high when
RESET is brought high again and the initialization is complete.
While BUSY is low, all interfaces are disabled. When BUSY
returns high, normal operation resumes, and the status of the
RESET pin is ignored until it goes low again. The SDO output is
high impedance during a power-on reset or a RESET. Power-on
reset functions the same way as RESET.
BUSY AND LOAD FUNCTIONS
The BUSY pin is an open-drain output that indicates the status
of the AD5522 interface. When writing to any register, BUSY
goes low and stays low until the command completes.
A write operation to a DAC register drives the BUSY signal low
for longer than a write to a PMU or system control register. For
DACs, the value of the internal cached (X2) data is calculated and
stored each time that the user writes new data to the corresponding
X1 register. During the calculation and writing of X2, the BUSY
output is driven low. While BUSY is low, the user can continue
writing new data to the X1, M, or C register, but no DAC output
updates can take place (applies to single channel writes).
X2 values are stored and held until a PMU word is written that
calls the appropriate cached X2 register. Only then is a DAC
output updated.
The DAC outputs and PMU modes are updated by taking the
LOAD input low. If LOAD goes low while BUSY is active, the
LOAD event is stored and the DAC outputs or PMU modes are
updated immediately after BUSY goes high. A user can also hold
the LOAD input permanently low. In this case, the DAC outputs
or PMU modes are updated immediately after BUSY goes high.
The BUSY pin is bidirectional and has a 50 kΩ internal pull-up
resistor. When multiple AD5522 devices are used in one system,
the BUSY pins can be tied together. This is useful when it is
required that no DAC or PMU in any device be updated until
all others are ready to be updated. When each device finishes
updating its X2 registers, it releases the BUSY pin. If another
device has not finished updating its X2 registers, it holds BUSY
low, thus delaying the effect of LOAD going low.
Because there is only one calibration engine shared among four
channels, the task of calculating X2 values must be done
sequentially, so that the length of the BUSY pulse varies according
to the number of channels being updated. Following multiple
channel updates, subsequent writes to single or multiple X1
registers should either be timed or should wait until BUSY
returns high (see Figure 53). If subsequent X1 writes are
Rev. A | Page 40 of 60
AD5522
For other writes, (PMU, system control registers, and so forth),
the write command should not be completed (SYNC returning
high) until BUSY returns high. This is necessary to ensure that
calibration data is not lost and that the calibration data is not
corrupted.
600ns
600ns
300ns
WRITE 1
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
WRITE 2
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
WRITE 3
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
Figure 54. Multiple Single Channel Writes Engaging the Calibration Engine
Table 17. BUSY Pulse Widths
Action
Loading Data to PMU, System Control
Register, or Readback
Loading X1 to 1 PMU DAC Channel
Loading X1 to 2 PMU DAC Channels
Loading X1 to 3 PMU DAC Channels
Loading X1 to 4 PMU DAC Channels
1
~600ns
06197-036
CALIBRATION ENGINE TIME
presented before the calibration engine completes the first stage of
the last Channel X2 calculation, data may be lost.
BUSY Pulse Width1
REGISTER SELECTION
0.27 μs maximum
The serial word assignment consists of 29 bits. Bit 28 to Bit 22
are common to all registers, whether writing to or reading from
the device. The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address
each PMU channel (or associated DAC register). When the
PMU3 to PMU0 bits are all zeros, the system control register
is addressed.
1.5 μs maximum
2.1 μs maximum
2.7 μs maximum
3.3 μs maximum
The mode bits, MODE0 and MODE1, address the different sets
of DAC registers and the PMU register.
BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns.
Table 18. Mode Bits
BUSY also goes low during a power-on reset and when a falling
edge is detected on the RESET pin.
CALIBRATION ENGINE TIME
~600ns
600ns
600ns
300ns
WRITE 1
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
WRITE 2
FIRST
STAGE
SECOND
STAGE
FOR EXAMPLE,
WRITE TO 3 FIN
DAC REGISTERS
B23
MODE1
0
B22
MODE0
0
0
1
1
1
0
1
Action
Write to the system control register or
the PMU register
Write to the DAC gain (M) register
Write to the DAC offset (C) register
Write to the DAC input data (X1) register
06197-035
Readback Control, RD/WR
THIRD
STAGE
Figure 53. Multiple Writes to DAC X1 Registers
Writing data to the system control register, the PMU control
register, the M register, or the C register does not involve the
digital calibration engine, thus speeding up configuration of the
device on power-on, but care should be taken not to issue these
commands while BUSY is low as previously described.
REGISTER UPDATE RATES
The value of the X2 register is calculated each time the user
writes new data to the corresponding X1 register. The calculation
is performed in a three-stage process. The first two stages take
approximately 600 ns each, and the third stage takes approximately 300 ns. When the write to the X1 register is complete,
the calculation process begins. If the write operation involves
the update of a single DAC channel, the user is free to write to
another X1 register, provided that the write operation does not
finish (SYNC returns high) until after the first-stage calculation
is complete, that is, 600 ns after the completion of the first write
operation.
Setting the RD/WR bit (Bit 28) high initiates a readback
sequence of the PMU, alarm status, comparator status, system
control, or DAC register, as determined by the address bits.
PMU Address Bits: PMU3, PMU2, PMU1, PMU0
The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address each
PMU channel on chip. These bits allow individual control of
each PMU channel or any combination of channels, in addition
to multichannel programming. PMU bits also allow access to
write registers such as the system control register and the DAC
registers, in addition to reading from all the registers (see Table 19).
NOP (No Operation)
If an NOP (no operation) command is loaded, no change is
made to DAC or PMU registers. This code is useful when
performing a readback of a register within the device (via the
SDO pin) where a change of DAC code or PMU function may
not be required.
Reserved Commands
Any bit combination that is not described in the register address
tables for the PMU, DAC, and system control registers indicates
a reserved command. These commands are unassigned and are
reserved for factory use. To ensure correct operation of the
device, do not use reserved commands.
Rev. A | Page 41 of 60
AD5522
All codes not explicitly referenced in this table are reserved and should not be used (see Table 28).
Table 19. Read and Write Functions of the AD5522
B28
RD/WR
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21 to B0
Data bits
Selected Channel
CH3 CH2 CH1
0
0
0
0
0
Data bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write Addressed DAC or PMU Register
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
Read Functions
1
0
0
0
0
0
1
1
1
1
0
1
1
Data bits
Data bits
All ones
Data bits other than all ones
Write to system control
register (see Table 22)
Reserved
Reserved
NOP (no operation)
Reserved
0
0
All zeros
1
0
0
0
0
0
1
All zeros
1
1
0
0
0
0
0
0
0
0
1
1
0
1
X
All zeros
Write Functions
0
0
Select DAC or
PMU register
(see Table 18)
Address and data bits
CH0
CH1
CH1
CH2
CH2
CH2
CH2
CH3
CH3
CH3
CH3
CH3
CH3
CH3
CH3
Read Addressed DAC or PMU Register (Only One PMU or DAC Register Can Be Read at One Time)
1
0
0
0
1
Select PMU or
All zeros if reading PMU registers;
DAC register
DAC address plus all zeros if reading a
1
0
0
1
0
(see
Table
18)
DAC register DAC address (see Table 28)
1
0
1
0
0
1
1
0
0
0
Rev. A | Page 42 of 60
CH0
CH0
CH0
CH1
CH1
CH0
CH0
CH1
CH1
CH2
CH2
CH2
CH2
CH0
CH0
CH1
CH1
CH0
Read from system control
register
Read from comparator
status register
Reserved
Read from alarm status
register
CH0
CH1
CH2
CH3
AD5522
WRITE SYSTEM CONTROL REGISTER
The system control register is accessed when the PMU channel address bits (PMU3 to PMU0) and the mode bits (MODE1 and MODE0)
are all zeros. This register allows quick setup of various functions in the device. The system control register operates on a per-device basis.
Table 20. System Control Register Bits—Bit B28 to Bit B15
B28
RD/WR
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21
CL3
B20
CL2
B19
CL1
B18
CL0
B17
CPOLH3
B16
CPOLH2
B15
CPOLH1
Table 21. System Control Register Bits—Bit B14 to Bit B0
B14
CPOLH0
1
B13
CPBIASEN
B12
DUTGND/CH
B11
GUARD
ALM
B10
CLAMP
ALM
B9
INT10K
B8
GUARD
EN
B7
GAIN1
B6
GAIN0
B5
TMP
ENABLE
B4
TMP1
B3
TMP0
B2
LATCHED
B11
0
B01
0
Bit B1 and Bit B0 are unused data bits.
Table 22. System Control Register Functions
Bit
28 (MSB)
Bit Name
RD/WR
Description
When low, a write function takes place to the selected register; setting the RD/WR bit high initiates a readback
sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the
address bits.
Set Bit PMU3 to Bit PMU0 to 0 to address the system control register.
27
PMU3
26
PMU2
25
PMU1
24
PMU0
23
MODE1
Set the MODE1 and MODE0 bits to 0 to address the system control register.
22
MODE0
System Control Register Specific Bits
21
CL3
Current clamp enable. Bit CL3 to Bit CL0 enable and disable the current clamp function per channel (0 = disable;
1 = enable). The clamp enable function is also available in the PMU register on a per-channel basis. This dual
20
CL2
functionality allows flexible enabling or disabling of this function. When reading back information about the
19
CL1
status of the current clamp enable function, the data that was most recently written to the current clamp
18
CL0
register is available in the readback word from either the PMU register or the system control register.
17
16
15
14
CPOLH3
CPOLH2
CPOLH1
CPOLH0
13
CPBIASEN
12
DUTGND/CH
11
10
GUARD ALM
CLAMP ALM
9
INT10K
8
GUARD EN
Comparator output enable. By default, the comparator outputs are high-Z on power-on. A 1 in each bit position
enables the comparator output for the selected channel. Bit 13 (CPBIASEN) must be enabled to power on the
comparator functions. The comparator enable function is also available in the PMU register on a per-channel
basis. This dual functionality allows flexible enabling or disabling of this function. When reading back information
about the status of the comparator enable function, the data that was most recently written to the comparator
status register is available in the readback word from either the PMU register or the system control register.
Comparator enable. By default, the comparators are powered down when the device is powered on. To enable
the comparator function for all channels, write a 1 to this bit. A 0 disables the comparators and shuts them
down. The comparator output enable bits (CPOLHx, Bit 17 to Bit 14) allow the user to turn on each comparator
output individually, enabling busing of comparator outputs.
DUTGND per channel enable. The GUARDINx/DUTGNDx pins are shared pins that can be configured to enable a
DUTGND per PMU channel or a guard input per PMU channel. Setting this bit to 1 enables DUTGND per
channel. In this mode, the pin functions as a DUTGND pin on a per-channel basis. The guard inputs are
disconnected from this pin and instead are connected directly to the MEASVHx line by an internal connection.
The default power-on condition is GUARDINx.
Clamp and guard alarm functions share one open-drain alarm pin (CGALM). By default, the CGALM pin is
disabled. The GUARD ALM and CLAMP ALM bits allow the user to choose whether clamp alarm information,
guard alarm information, or both sets of alarm information are flagged by the CGALM pin. Set high to enable
either alarm function.
Internal sense short. Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ
(4 kΩ + 2 kΩ switch + 4 kΩ) between the FOHx and the MEASVHx lines (SW7 is closed). Setting this bit high also
closes SW15, allowing the user to connect another 10 kΩ resistor between DUTGND and AGND.
Guard enable. The guard amplifier is disabled on power-on; to enable the guard amplifier, set this bit to 1. If the
guard function is not in use, disabling it saves power (typically 400 μA per channel).
Rev. A | Page 43 of 60
AD5522
Bit
7
6
Bit Name
GAIN1
GAIN0
5
TMP ENABLE
4
3
TMP1
TMP0
2
LATCHED
1
0 (LSB)
0
0
Description
MEASOUT output range. The MEASOUT range defaults to the force voltage span for voltage and current measurements, which includes some overrange to allow for offset correction. The nominal output voltage range is ±11.25 V
with the default offset DAC setting, but changes for other offset DAC settings when GAIN1 = 0. Therefore, the
MEASOUT range can be an asymmetrical bipolar voltage range. GAIN1 = 1 enables a unipolar output voltage
range, which allows the use of asymmetrical supplies or a smaller input range ADC. See Table 10 and Table 11
for more details.
Output Voltage Range for VREF = 5 V, Offset DAC = 0xA492
MEASOUT
Measure
GAIN1 = 0, MEASOUT Gain = 1
GAIN1 = 1, MEASOUT Gain = 0.2
Function
Current Gain
MV
5 or 10
±VDUT (up to 11.25 V)
0 V to (4.5 × VREF)/5
MI
GAIN0 = 0
10
±VRSENSE × 10 = up to ±11.25 V
0 V to 4.5 V
GAIN0 = 1
5
±VRSENSE × 5 = up to ±5.625 V
0 V to 2.25 V
Thermal shutdown feature. To disable the thermal shutdown feature, set the TMP ENABLE bit to 0 (thermal
shutdown is enabled by default).
The TMP1 and TMP0 bits allow the user to program the temperature that triggers thermal shutdown.
TMP
ENABLE
TMP1
TMP0
Action
0
X
X
Thermal shutdown disabled
1
X
X
Thermal shutdown enabled
1
0
0
Shutdown at junction temperature of 130°C (power-on default)
1
0
1
Shutdown at junction temperature of 120°C
1
1
0
Shutdown at junction temperature of 110°C
1
1
1
Shutdown at junction temperature of 100°C
Configure the open-drain pin (CGALM) as a latched or unlatched output pin. When high, this bit configures the
CGALM alarm output as a latched output, allowing it to drive a controller I/O without needing to poll the line
constantly. The power-on default for this pin is unlatched.
Unused bits. Set to 0.
Rev. A | Page 44 of 60
AD5522
WRITE PMU REGISTER
combination of PMU channels, or all PMU channels. This
functionality enables multipin broadcasting to similar pins on
a DUT. Bit 27 to Bit 24 select the PMU or group of PMUs that
is addressed.
To address PMU functions, set the MODE1 and MODE0 bits
to 0. This setting selects the PMU register (see Table 18 and
Table 19). The AD5522 has very flexible addressing, which
allows writing of data to a single PMU channel, any
Table 23. PMU Register Bits—Bit B28 to Bit B15
B28
RD/WR
1
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21
CH EN
B20
FORCE1
B8
CPOLH
B7
COMPAREV/I
B19
FORCE0
B181
0
B17
C2
B16
C1
B15
C0
Bit B18 is reserved.
Table 24. PMU Register Bits—Bit B14 to Bit B0
B14
MEAS1
1
B13
MEAS0
B12
FIN
B11
SF0
B10
SS0
B9
CL
B6
CLEAR
B51
0
B41
0
B31
0
B21
0
B11
0
B01
0
Bit B5 to Bit B0 are unused data bits.
Table 25. PMU Register Functions
Bit
28 (MSB)
Bit Name
RD/WR
Description
When low, a write function takes place to the selected register; setting the RD/WR bit high initiates a readback
sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the
address bits.
Bit PMU3 to Bit PMU0 address each PMU channel in the device. These bits allow control of an individual PMU
channel or any combination of channels, in addition to multichannel programming. See Table 19.
27
PMU3
26
PMU2
25
PMU1
24
PMU0
23
MODE1
Set the MODE1 and MODE0 bits to 0 to access the PMU register selected by the PMU3 to PMU0 bits (Bit 27 to
Bit 24).
22
MODE0
PMU Register Specific Bits
21
CH EN
Channel enable. Set high to enable the selected channel or group of channels; set low to disable the selected
channel or channels. When disabled, SW2 is closed and SW5 is open (outputs are high-Z). The measure mode is
determined by the MEAS1 and MEAS0 bits at all times and is not affected by the CH EN bit. The guard amplifier
and the comparators are not affected by this bit.
20
FORCE1
The FORCE1 and FORCE0 bits set the force function for each PMU channel (in association with the PMUx bits).
All combinations of forcing and measuring (using the MEAS1 and MEAS0 bits) are available. The high-Z (voltage
19
FORCE0
and current) modes allow the user to optimize glitch response during mode changes. While in high-Z voltage or
current mode, with the PMU high-Z, new X1 codes loaded to the FIN DAC register and to the clamp DAC register
are calibrated, stored in the X2 register, and loaded directly to the DAC outputs.
FORCE1
FORCE0
Action
0
0
FV and current clamp (if clamp is enabled)
0
1
FI and voltage clamp (if clamp is enabled)
1
0
High-Z FOHx voltage (preload FIN DAC and clamp DAC)
1
1
High-Z FOHx current (preload FIN DAC and clamp DAC)
18
Reserved
0
17
C2
Bit C2 to Bit C0 specify the required current range. High-Z FV/FI commands ignore the current range address
bits (C2, C1, and C0); therefore, these bit combinations cannot be used to enable or disable the force function
16
C1
for a PMU channel.
15
C0
C2
C1
C0
Selected Current Range
0
0
0
±5 μA current range
0
0
1
±20 μA current range
0
1
0
±200 μA current range
0
1
1
±2 mA current range (default)
1
0
0
± external current range
1
0
1
Disable the always on mode for the external current range buffer1
1
1
0
Enable the always on mode for the external current range buffer2
1
1
1
Reserved
Rev. A | Page 45 of 60
AD5522
Bit
14
13
Bit Name
MEAS1
MEAS0
12
FIN
11
10
SF0
SS0
9
CL
8
CPOLH
7
COMPARE
V/I
CLEAR
6
5
4
3
2
1
0 (LSB)
Unused
Description
The MEAS1 and MEAS0 bits specify the required measure mode, allowing the MEASOUTx line to be disabled,
connected to the temperature sensor, or enabled for measurement of current or voltage.
MEAS1
MEAS0
Action
0
0
MEASOUTx is connected to ISENSE
0
1
MEASOUTx is connected to VSENSE
1
0
MEASOUTx is connected to the temperature sensor
1
1
MEASOUTx is high-Z (SW12 open)
This bit sets the status of the force input (FIN) amplifier.
0 = input of the force amplifier switched to GND.
1 = input of the force amplifier connected to the FIN DAC output.
The SF0 and SS0 bits specify the switching of system force and sense lines to the force and sense paths at the
DUT. The channel to which the system force and system sense lines are connected is set by the PMU3 to PMU0
bits. For correct operation, only one PMU channel should be connected to the SYS_FORCE and SYS_SENSE
paths at any one time.
SF0
SS0
Action
0
0
SYS_FORCE and SYS_SENSE are high-Z for the selected channel
0
1
SYS_FORCE is high-Z and SYS_SENSE is connected to MEASVHx for the selected channels
1
0
SYS_FORCE is connected to FOHx and SYS_SENSE is high-Z for the selected channel
1
1
SYS_FORCE is connected to FOHx and SYS_SENSE is connected to MEASVHx for the selected
channel
Per-PMU current clamp enable bit. A logic high enables the clamp function for the selected PMU. The current
clamp enable function is also available in the system control register. This dual functionality allows flexible
enabling or disabling of this function. When reading back information about the status of the current clamp
enable function on a per-channel basis, the data that was most recently written to the current clamp register is
available in the readback word from either the PMU register or the system control register.
Comparator output enable bit. By default, the comparator outputs are high-Z on power-on. A logic high enables
the comparator output for the selected PMU. The comparator function CPBIASEN (Bit 13 in the system control
register) must be enabled. The comparator output enable function is also available in the system control register.
This dual functionality allows flexible enabling or disabling of this function. When reading back information about
the status of the comparator enable function, the data that was most recently written to the comparator status
register is available in the readback word from either the PMU register or the system control register.
A logic high selects the compare voltage function; a logic low selects the compare current function.
To clear or reset a latched alarm bit and pin (temperature, guard, or clamp), write a 1 to this bit. This bit applies
to latched alarm conditions (clamp and guard) on all four PMU channels.
Unused bits. Set to 0.
1
Writing 101 in Bit 17 to Bit 15 disables the always on mode for the external current range buffer. Use with FV mode (FORCE1 = FORCE0 = 0) only. To complete the
disabling of the always on mode, the PMU channel is placed into high-Z mode and the external current range buffer is returned to its default operation (off).
2
Writing 110 in Bit 17 to Bit 15 places the external current range buffer into always on mode. In this mode, the buffer is always active with no regard to the selected current
range. The always on mode is intended for use where an external high current stage is being used for a current drive in excess of ±80 mA; having the internal stage
always on should help to eliminate timing concerns when transitioning between this current range and other ranges. When first enabling the always on mode, use it in
conjunction with FV mode (FORCE1 = FORCE0 = 0); the device now enables the external current range buffer. The 110 code also places the device into high-Z mode
(necessary to complete the enabling function). To return to an FV or FI operating mode, select the appropriate mode and current range. The external range sense
resistor is connected to an MI circuit only when the external current range address is selected (C2 to C0 are set to 100). The default operation at power-on is disabled
(or off).
Rev. A | Page 46 of 60
AD5522
WRITE DAC REGISTER
The DAC input, gain, and offset registers are addressed through a combination of PMU bits (Bit 27 to Bit 24) and mode bits (Bit 23 and
Bit 22). Bit A5 to Bit A0 address each DAC level on chip. Bit D15 to Bit D0 are the DAC data bits used when writing to these registers. The
PMU address bits allow addressing of a particular DAC for any combination of PMU channels.
Table 26. DAC Register Bits
B28
RD/WR
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21
A5
B20
A4
B19
A3
B18
A2
B17
A1
B16
A0
B15 to B0
Data Bits[D15 (MSB):D0 (LSB)]
Table 27. DAC Register Functions
Bit
28 (MSB)
Bit Name
RD/WR
27
26
25
24
23
22
PMU3
PMU2
PMU1
PMU0
MODE1
MODE0
DAC Register Specific Bits
21
A5
20
A4
19
A3
18
A2
17
A1
16
A0
15 to 0
D15 (MSB) to D0 (LSB)
Description
When this bit is low, a write function takes place to the selected register; setting the RD/WR bit high
initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC
register, as determined by the address bits.
Bit PMU3 to Bit PMU0 address each PMU and DAC channel in the device. These bits allow control of
each individual DAC channel or any combination of channels, in addition to multichannel programming.
The MODE1 and MODE0 bits allow addressing of the DAC gain (M), offset (C), or input (X1) register.
MODE1
MODE0
Action
0
0
Write to the system control register or the PMU register
0
1
Write to the DAC gain (M) register
1
0
Write to the DAC offset (C) register
1
1
Write to the DAC input data (X1) register
DAC address bits. The A5 to A3 bits select the register set that is addressed. See the DAC Addressing
section.
DAC address bits. The A2 to A0 bits select the DAC that is addressed. See the DAC Addressing section.
16 DAC data bits.
Rev. A | Page 47 of 60
AD5522
DAC Addressing
For the FIN and comparator (CPH and CPL) DACs, there is a
set of X1, M, and C registers for each current range, and one set
for the voltage range; for the clamp DACs (CLL and CLH),
there are only two sets of X1, M, and C registers.
When calibrating the device, the M and C registers allow volatile
storage of gain and offset coefficients. Calculation of the corresponding DAC X2 register occurs only when the X1 data is loaded
(no internal calculation occurs on M or C updates).
There is one offset DAC for all four channels in the device that
is addressed using the PMUx bits. The offset DAC has only an
input register associated with it; no M or C registers are associated with this DAC. When writing to the offset DAC, set the
MODE1 and MODE0 bits high to address the DAC input
register (X1).
The same address table is also used for readback of a particular
DAC address.
Note that CLL is clamp level low and CLH is clamp level high.
•
•
When forcing a voltage, the current clamps are engaged;
therefore, both the CLL current ranges register set and the
CLH current ranges register set are loaded to the clamp DACs.
When forcing a current, the voltage clamps are engaged;
therefore, both the CLL voltage range register set and the
CLH voltage range register set are loaded to the clamp DACs.
All codes not explicitly referenced in this table are reserved and
should not be used.
Table 28. DAC Register Addressing
A5
0
0
A4
0
0
A3
0
1
A2
0
0
A1
0
0
A0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
MODE1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
MODE0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
Rev. A | Page 48 of 60
Register Set
±5 μA current range
±20 μA current range
±200 μA current range
±2 mA current range
±external current range
Voltage range
Current ranges
Voltage range
Current ranges
Voltage range
±5 μA current range
Addressed Register
Offset DAC X
FIN M
FIN C
FIN X1
FIN M
FIN C
FIN X1
FIN M
FIN C
FIN X1
FIN M
FIN C
FIN X1
FIN M
FIN C
FIN X1
FIN M
FIN C
FIN X1
CLL M
CLL C
CLL X1 1
CLL M
CLL C
CLL X11
CLH M
CLH C
CLH X1 2
CLH M
CLH C
CLH X12
CPL M
CPL C
CPL X1
AD5522
A5
1
A4
0
A3
0
A2
0
A1
0
A0
1
1
0
0
0
1
0
1
0
0
0
1
1
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
1
0
1
1
2
MODE1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
MODE0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
CLL should be within the range of 0x0 to 0x7FFF.
CLH should be within the range of 0x8000 to 0xFFFF.
Rev. A | Page 49 of 60
Register Set
±20 μA current range
±200 μA current range
±2 mA current range
± external current range
Voltage range
±5 μA current range
±20 μA current range
±200 μA current range
±2 mA current range
±external current range
Voltage range
Addressed Register
CPL M
CPL C
CPL X1
CPL M
CPL C
CPL X1
CPL M
CPL C
CPL X1
CPL M
CPL C
CPL X1
CPL M
CPL C
CPL X1
CPH M
CPH C
CPH X1
CPH M
CPH C
CPH X1
CPH M
CPH C
CPH X1
CPH M
CPH C
CPH X1
CPH M
CPH C
CPH X1
CPH M
CPH C
CPH X1
AD5522
A minimum of 24 clock rising edges is required to shift the
readback data out of the shift register. If writing a 24-bit word to
shift data out of the device, the user must ensure that the 24-bit
write is effectively an NOP (no operation) command. The last
five bits in the shift register are always 00000: these five bits
become the MSBs of the shift register when the 24-bit write is
loaded. To ensure that the device receives an NOP command as
described in Table 19, the recommended flush command is
0xFFFFFF; thus, no change is made to any register in the device.
READ REGISTERS
Readback of all the registers in the device is possible via the SPI
and the LVDS interfaces. To read data from a register, it is first
necessary to write a readback command to tell the device which
register is required for readback. See Table 29 to address the
appropriate channel.
When the required channel is addressed, the device loads
the 24-bit readback data into the MSB positions of the 29-bit
serial shift register (the 5 LSBs are filled with zeros). SCLK
rising edges clock this readback data out on SDO (framed
by the SYNC signal).
Readback data can also be shifted out by writing another 29-bit
write or read command. If writing a 29-bit command, the readback data is MSB data available on SDO, followed by 00000.
Table 29. Read Functions of the AD5522
B28
RD/WR
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21 to B0
Data bits
Read Functions
1
0
0
0
0
0
0
All zeros
1
0
0
0
0
0
1
All zeros
1
0
0
0
0
1
0
X
1
0
0
0
0
1
1
All zeros
Read Addressed PMU Register (Only One PMU Register Can Be Read at One Time)
1
0
0
0
1
0
0
All zeros
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
Read Addressed DAC M Register (Only One DAC Register Can Be Read at One Time)
1
0
0
0
1
0
1
DAC address
(see Table 28)
1
0
0
1
0
0
1
1
0
1
0
0
0
1
1
1
0
0
0
0
1
Read Addressed DAC C Register (Only One DAC Register Can Be Read at One Time)
1
0
0
0
1
1
0
DAC address
(see Table 28)
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
0
0
1
0
Read Addressed DAC X1 Register (Only One DAC Register Can Be Read at One Time)
1
0
0
0
1
1
1
DAC address
(see Table 28)
1
0
0
1
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
Rev. A | Page 50 of 60
CH3
Selected Channel
CH2
CH1
CH0
Read from system control register
Read from comparator status register
Reserved
Read from alarm status register
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
CH0
CH1
CH2
CH3
AD5522
READBACK OF SYSTEM CONTROL REGISTER
The system control register readback function is a 24-bit word. Mode and system control register data bits are shown in Table 30.
Table 30. System Control Register Readback
Bit
Bit Name
Description
23 (MSB)
MODE1
Set the MODE1 and MODE0 bits to 0 to address the system control register.
22
MODE0
System Control Register Specific Readback Bits
21
CL3
Read back the status of the individual current clamp enable bits.
0 = clamp is disabled.
20
CL2
1 = clamp is enabled.
19
CL1
When reading back information about the status of the clamp enable function, the data that was most
18
CL0
recently written to the current clamp register from either the system control register or the PMU register
is available in the readback word.
17
CPOLH3
Read back information about the status of the comparator output enable bits.
1 = PMU comparator output is enabled.
16
CPOLH2
0 = PMU comparator output is disabled.
15
CPOLH1
When reading back information about the status of the comparator output enable function, the data that
14
CPOLH0
was most recently written to the comparator status register from either the system control register or the
PMU register is available in the readback word.
13
CPBIASEN
This readback bit indicates the status of the comparator enable function.
1 = comparator function is enabled.
0 = comparator function is disabled.
12
DUTGND/CH
DUTGND per channel enable.
1 = DUTGND per channel is enabled.
0 = individual guard inputs are available per channel.
11
GUARD ALM
These bits provide information about which of these alarm bits trigger the CGALM pin.
1 = guard/clamp alarm is enabled.
10
CLAMP ALM
0 = guard/clamp alarm is disabled.
9
INT10K
If this bit is high, the internal 10 kΩ resistor (SW7) is connected between FOHx and MEASVHx, and
between DUTGND and AGND. If this bit is low, SW7 is open.
8
GUARD EN
Read back the status of the guard amplifiers. If this bit is high, the amplifiers are enabled.
7
GAIN1
Status of the selected MEASOUTx output range. See Table 10 and Table 11.
6
GAIN0
5
TMP ENABLE
Read back the status of the thermal shutdown function.
0XX = thermal shutdown disabled.
4
TMP1
100 = thermal shutdown enabled at junction temperature of 130°C (power-on default).
3
TMP0
101 = thermal shutdown enabled at junction temperature of 120°C.
110 = thermal shutdown enabled at junction temperature of 110°C.
111 = thermal shutdown enabled at junction temperature of 100°C.
2
LATCHED
This bit indicates the status of the open-drain alarm outputs, TMPALM and CGALM.
1 = open-drain alarm outputs are latched.
0 = open-drain alarm outputs are unlatched.
1
Loads with zeros.
Unused
readback bits
0 (LSB)
Rev. A | Page 51 of 60
AD5522
READBACK OF PMU REGISTER
The PMU register readback function is a 24-bit word that includes the mode and PMU data bits. Only one PMU register can be read back
at any one time.
Table 31. PMU Register Readback
Bit
Bit Name
23 (MSB)
MODE1
22
MODE0
PMU Register Specific Bits
21
CH EN
20
FORCE1
19
FORCE0
18
17
16
15
14
13
Reserved
C2
C1
C0
MEAS1
MEAS0
12
FIN
11
10
9
SF0
SS0
CL
8
CPOLH
7
COMPARE V/I
6
5
LTMPALM
TMPALM
4 to 0 (LSB)
Unused
readback bits
Description
Set the MODE1 and MODE0 bits to 0 to access the selected PMU register.
Channel enable. If this bit is high, the selected channel is enabled; if this bit is low, the channel is disabled.
These bits indicate which force mode the selected channel is in.
00 = FV and current clamp (if clamp is enabled).
01 = FI and voltage clamp (if clamp is enabled).
10 = high-Z FOHx voltage.
11 = high-Z FOHx current.
0
These three bits indicate which forced or measured current range is set for the selected channel. See
Table 25.
These bits indicate which measure mode is selected: voltage, current, temperature sensor, or high-Z.
00 = MEASOUTx is connected to ISENSE.
01 = MEASOUTx is connected to VSENSE.
10 = MEASOUTx is connected to the temperature sensor.
11 = MEASOUTx is high-Z (SW12 open).
This bit shows the status of the force input (FIN) amplifier.
0 = input of the force amplifier switched to GND.
1 = input of the force amplifier connected to the FIN DAC output.
The system force and sense lines can be connected to any of the four PMU channels. These bits indicate
whether the system force and sense lines are switched in. See Table 25.
Read back the status of the individual current clamp enable bits.
1 = clamp is enabled on this channel.
0 = clamp is disabled on this channel.
When reading back information about the status of the current clamp enable function, the data that
was most recently written to the current clamp register from either the system control register or the
PMU register is available in the readback word.
Read back the status of the comparator output enable bit.
1 = PMU comparator output is enabled.
0 = PMU comparator output is disabled.
When reading back information about the status of the comparator output enable function, the data
that was most recently written to the comparator register from either the system control register or the
PMU register is available in the readback word.
1 = compare voltage function is enabled on the selected channel.
0 = compare current function is enabled on the selected channel.
TMPALM corresponds to the open-drain TMPALM output pin that flags a temperature event exceeding
the default or user programmed level. The temperature alarm is a per-device alarm; the latched
(LTMPALM) and unlatched (TMPALM) bits indicate whether a temperature event occurred and whether
the alarm still exists (that is, whether the junction temperature still exceeds the programmed alarm
level). To reset an alarm event, the user must write a 1 to the clear bit (Bit 6) in the PMU register.
Loads with zeros.
Rev. A | Page 52 of 60
AD5522
READBACK OF COMPARATOR STATUS REGISTER
The comparator status register is a read-only register that provides access to the output status of each comparator pin on the chip. Table 32
shows the format of the comparator register readback word.
Table 32. Comparator Status Register (Read-Only)
Bit
Bit Name
Description
23 (MSB)
MODE1
0
22
MODE0
1
Comparator Status Register Specific Bits
21
CPOL0
Comparator output conditions per channel corresponding to the comparator output pins.
1 = PMU comparator output is high.
20
CPOH0
0 = PMU comparator output is low.
19
CPOL1
18
17
16
15
14
13 to 0 (LSB)
CPOH1
CPOL2
CPOH2
CPOL3
CPOH3
Unused
readback bits
Loads with zeros.
READBACK OF ALARM STATUS REGISTER
The alarm status register is a read-only register that provides information about temperature, clamp, and guard alarm events.
Temperature alarm status is also available in any of the four PMU readback registers.
Table 33. Alarm Status Register Readback
Bit
Bit Name
Description
23 (MSB)
MODE1
1
22
MODE0
1
Alarm Status Register Specific Bits
21
TMPALM corresponds to the open-drain TMPALM output pin that flags a temperature event
LTMPALM
exceeding the default or user programmed level. The temperature alarm is a per-device alarm; the
20
TMPALM
latched (LTMPALM) and unlatched (TMPALM) bits indicate whether a temperature event occurred
and whether the alarm still exists (that is, whether the junction temperature still exceeds the
programmed alarm level). To reset an alarm event, the user must write a 1 to the clear bit (Bit 6)
in the PMU register.
19
LGx is the per-channel latched guard alarm bit, and Gx is the unlatched guard alarm bit. These bits
LG0
indicate
which channel flagged the alarm on the open-drain alarm pin CGALM and whether the
18
G0
alarm
condition
still exists.
17
LG1
16
G1
15
LG2
14
G2
13
LG3
12
G3
11
10
9
8
7
6
5
4
LC0
C0
LC1
C1
LC2
C2
LC3
C3
LCx is the per-channel latched clamp alarm bit, and Cx is the unlatched clamp alarm bit. These bits
indicate which channel flagged the alarm on the open-drain alarm pin CGALM and whether the
alarm condition still exists.
3 to 0 (LSB)
Unused
readback bits
Loads with zeros.
Rev. A | Page 53 of 60
AD5522
READBACK OF DAC REGISTER
The DAC register readback function is a 24-bit word that includes the mode, address, and DAC data bits.
Table 34. DAC Register Readback
Bit
23 (MSB)
22
Bit Name
MODE1
MODE0
DAC Register Specific Bits
21 to 16
A5 to A0
15 to 0 (LSB)
D15 to D0
Description
The MODE1 and MODE0 bits indicate the type of DAC register (X1, M, or C) that is read.
01 = DAC gain (M) register.
10 = DAC offset (C) register.
11 = DAC input data (X1) register.
Address bits indicating the DAC register that is read. See Table 28.
Contents of the addressed DAC register (X1, M, or C).
Rev. A | Page 54 of 60
AD5522
APPLICATIONS INFORMATION
POWER-ON DEFAULT
Table 36. Power-On Default for System Control Register
The power-on default for all DAC channels is that the contents
of each M register are set to full scale (0xFFFF), and the contents
of each C register are set to midscale (0x8000). The contents of
the DAC X1 registers at power-on are listed in Table 35.
The power-on default for the alarm status register is 0xFFFFF0,
and the power-on default for the comparator status register is
0x400000. The power-on default values of the PMU register and
the system control register are shown in Table 36 and Table 37.
SETTING UP THE DEVICE ON POWER-ON
On power-on, default conditions are recalled from the poweron reset register to ensure that each PMU and DAC channel is
powered up in a known condition. To operate the device, the
user must follow these steps:
1.
2.
3.
4.
Configure the device by writing to the system control
register to set up different functions as required.
Calibrate the device to trim out errors, and load the
required calibration values to the gain (M) and offset (C)
registers. Load codes to each DAC input (X1) register.
When X1 values are loaded to the individual DACs, the
calibration engine calculates the appropriate X2 value and
stores it, ready for the PMU address to call it.
Load the required PMU channel with the required force
mode, current range, and so on. Loading the PMU channel
configures the switches around the force amplifier,
measure function, clamps, and comparators, and also acts
as a load signal for the DACs, loading the DAC register
with the appropriate stored X2 value.
Because the voltage and current ranges have individual
DAC registers associated with them, each PMU register
mode of operation calls a particular X2 register. Therefore,
only updates (that is, changes to the X1 register) to DACs
associated with the selected mode of operation are reflected
in the output of the PMU. If there is a change to the X1
value associated with a different PMU mode of operation,
this X1 value and its M and C coefficients are used to
calculate a corresponding X2 value, which is stored in the
correct X2 register, but this value is not loaded to the DAC.
Table 35. Default Contents of DAC Registers at Power-On
DAC Register
Offset DAC
FIN DAC
CLL DAC
CLH DAC
CPL DAC
CPH DAC
Default Value
0xA492
0x8000
0x0000
0xFFFF
0x0000
0xFFFF
Bit
21 (MSB)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (LSB)
Bit Name
CL3
CL2
CL1
CL0
CPOLH3
CPOLH2
CPOLH1
CPOLH0
CPBIASEN
DUTGND/CH
GUARD ALM
CLAMP ALM
INT10K
GUARD EN
GAIN1
GAIN0
TMP ENABLE
TMP1
TMP0
LATCHED
Unused data bit
Unused data bit
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Table 37. Power-On Default for PMU Register
Bit
21 (MSB)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (LSB)
Rev. A | Page 55 of 60
Bit Name
CH EN
FORCE1
FORCE0
Reserved
C2
C1
C0
MEAS1
MEAS0
FIN
SF0
SS0
CL
CPOLH
COMPARE V/I
LTMPALM
TMPALM
Unused data bit
Unused data bit
Unused data bit
Unused data bit
Unused data bit
Default Value
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
AD5522
3.
CHANGING MODES
There are different ways of handling a mode change.
2.
Load any DAC X1 values that require changes. Remember
that for force amplifier and comparator DACs, X1 registers
are available per voltage and current range, so the user can
preload new DAC values to make DAC updates ahead of
time; the calibration engine calculates the X2 values and
stores them.
Change to the new PMU mode (FI or FV). This action
loads the new switch conditions to the PMU circuitry and
loads the DAC register with the stored X2 data.
4.
The following steps describe another method for changing modes:
1.
2.
REQUIRED EXTERNAL COMPONENTS
In the PMU register (Bit 20 and Bit 19), enable the high-Z
voltage or high-Z current mode to make the amplifier high
impedance (SW5 open).
Load any DAC X1 values that require changes. Remember
that for force amplifier and comparator DACs, X1 registers
are available per voltage and current range, so the user can
preload new DAC values to make DAC updates ahead of
time; the calibration engine calculates the X2 values and
stores them.
AVSS
The minimum required external components for use with
the AD5522 are shown in Figure 55. Decoupling is greatly
dependent on the type of supplies used, other decoupling
on the board, and the noise in the system. It is possible that
more or less decoupling may be required.
AVDD DVCC
10µF
10µF
10µF
0.1µF
0.1µF
0.1µF
REF
0.1µF
AVSS
VREF
AVDD DVCC
CCOMP[0:3]
EXTFOH3
EXTFOH0
CFF0
CFF3
FOH3
FOH0
MEASVH3
MEASVH0
EXTMEASIH3
EXTMEASIH0
RSENSE
(UP TO
±80mA)
RSENSE
(UP TO
±80mA)
EXTMEASIL0
EXTMEASIL3
DUT
DUT
EXTFOH2
EXTFOH1
CFF1
CFF2
FOH2
FOH1
MEASVH2
MEASVH1
EXTMEASIH2
EXTMEASIH1
RSENSE
(UP TO
±80mA)
RSENSE
(UP TO
±80mA)
EXTMEASIL1
DUTGND
EXTMEASIL2
DUT
DUT
Figure 55. External Components Required for Use with the AD5522
Rev. A | Page 56 of 60
06197-037
1.
When the high-Z (voltage or current) mode is used, the
relevant DAC outputs are automatically updated (FIN,
CLL, and CLH DACs). For example, in high-Z voltage
mode, when new X1 writes occur, the FIN voltage X2 result
is calculated, cached, and loaded to the FIN DAC. When
forcing a voltage, current clamps are engaged, so the CLL
current register can be loaded, and the gain and offset
corrected and loaded to the DAC register. (The CLH
current register works the same way.)
Change to the new PMU mode (FI or FV). This action
loads the new switch conditions to the PMU circuitry.
Because the DAC outputs are already loaded, transients are
minimized when changing current or voltage mode.
AD5522
Table 38. ADCs and ADC Drivers Suggested For Use with AD5522 1
Part No.
AD7685
Resolution
16
Sample
Rate
250 kSPS
Ch.
No.
1
AIN Range
0 to VREF
Interface
Serial, SPI
ADC Driver
ADA4841-x
Multiplexer 2
ADG704, ADG708
AD7686
16
500 kSPS
1
0 to VREF
Serial, SPI
ADA4841-x
ADG704, ADG708
AD7693
16
500 kSPS
1
−VREF to +VREF
Serial, SPI
AD7610 3
16
250 kSPS
1
Serial/Parallel
ADG1404, ADG1408,
ADG1204
ADG1404, ADG1408,
ADG1204
AD7655
16
1 MSPS
4
Bipolar 10 V, Bipolar
5 V, Unipolar 10 V,
Unipolar 5 V
0 V to 5 V
ADA4841-x,
ADA4941-1
AD8021
Serial/Parallel
Package
MSOP,
LFCSP
MSOP,
LFCSP
MSOP,
LFCSP
LFCSP,
LQFP
ADA4841-x/
AD8021
1
Subset of the possible ADCs suitable for use with the AD5522. Visit www.analog.com for more options
For purposes of sharing an ADC among multiple PMU channels. Note, that the multiplexer is not absolutely necessary as the AD5522 MEASOUTx path has a tri-state
mode per channel.
3
Do not allow the MEASOUT output range to exceed the AIN range of the ADC.
2
POWER SUPPLY DECOUPLING
Careful consideration of the power supply and ground return
layout helps to ensure the rated performance. Design the
printed circuit board (PCB) on which the AD5522 is mounted
so that the analog and digital sections are separated and
confined to certain areas of the board. If the AD5522 is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
Establish the star ground point as close as possible to the device.
For supplies with multiple pins (AVSS and AVDD), it is
recommended that these pins be tied together and that each
supply be decoupled only once.
shielded with digital ground to avoid radiating noise to other
parts of the board, and they should never be run near the reference inputs. It is essential to minimize noise on all VREF lines.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other to
reduce the effects of feedthrough through the board. As is the
case for all thin packages, care must be taken to avoid flexing
the package and to avoid a point load on the surface of this
package during the assembly process.
Also, note that the exposed paddle of the AD5522 is connected
to the negative supply, AVSS.
The AD5522 should have ample supply decoupling of 10 μF
in parallel with 0.1 μF on each supply located as close to the
package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capacitors should have low effective series resistance (ESR) and low
effective series inductance (ESL)—typical of the common
ceramic types that provide a low impedance path to ground at
high frequencies—to handle transient currents due to internal
logic switching.
Avoid running digital lines under the device because they can
couple noise onto the device. However, allow the analog ground
plane to run under the AD5522 to avoid noise coupling (applies
only to the package with paddle up). The power supply lines of
the AD5522 should use as large a trace as possible to provide
low impedance paths and reduce the effects of glitches on the
power supply line. Fast switching digital signals should be
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5522, it is important
that the AGND and DGND pins be connected to the relevant
ground planes before the positive or negative supplies are applied.
This is the only power sequencing requirement for this device.
TYPICAL APPLICATION FOR THE AD5522
Figure 56 shows the AD5522 used in an ATE system. The device
can be used as a per-pin parametric unit to speed up the rate at
which testing can be done.
The central PMU (shown in the block diagram) is usually a
highly accurate PMU and is shared among a number of pins
in the tester. In general, many discrete levels are required in an
ATE system for the pin drivers, comparators, clamps, and active
loads. DAC devices such as the AD537x family offer a highly
integrated solution for a number of these levels.
Rev. A | Page 57 of 60
AD5522
DRIVEN
SHIELD
DAC
ADC
CENTRAL
PMU
GUARD AMP
AD5522
VCH
DAC
DAC
TIMING DATA
MEMORY
TIMING
GENERATOR
DLL, LOGIC
DAC
ADC
VTERM
DAC
DAC
PMU
PMU
DAC
DAC
PMU
PMU
VH
DUT
RELAYS
FORMATTER
DESKEW
50Ω
COAX
DRIVER
VL
DAC
DAC
VCL
GND
SENSE
DAC
COMPARE
MEMORY
FORMATTER
DESKEW
VTH
COMP
DAC
VTL
DAC
GUARD
AMP
ADC
ACTIVE LOAD
VCOM
06197-038
DAC
DAC
DEVICE POWER
SUPPLY
IOL
DAC
IOH
Figure 56. Typical Applications Circuit Using the AD5522 as a Per-Pin Parametric Unit
Rev. A | Page 58 of 60
AD5522
OUTLINE DIMENSIONS
14.20
14.00 SQ
13.80
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.20
MAX
80
61
61
1
80
1
60
60
PIN 1
EXPOSED
PAD
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
0° MIN
0.15
0.05
SEATING
PLANE
(PINS UP)
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
20
41
41
40
21
20
21
40
VIEW A
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 57. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
SV-80-3
Dimensions shown in millimeters
14.20
14.00 SQ
13.80
0.75
0.60
0.45
1.20
MAX
12.20
12.00 SQ
11.80
80
61
61
1
80
1
60
60
PIN 1
EXPOSED
PAD
0° MIN
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
(PINS UP)
TOP VIEW
(PINS DOWN)
20
41
40
21
VIEW A
6.50
BSC
41
0.50 BSC
LEAD PITCH
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HU
Figure 58. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
SV-80-2
Dimensions shown in millimeters
Rev. A | Page 59 of 60
20
21
40
0.27
0.22
0.17
071808-A
1.05
1.00
0.95
BOTTOM VIEW
9.50
BSC
071808-A
1.05
1.00
0.95
9.50
BSC SQ
AD5522
ORDERING GUIDE
Model
AD5522JSVDZ 2
AD5522JSVUZ2
EVAL-AD5522EBDZ2
EVAL-AD5522EBUZ2
1
2
Temperature Range (TJ)
25°C to 90°C
25°C to 90°C
Package Description 1
80-Lead TQFP_EP with exposed pad on bottom
80-Lead TQFP_EP with exposed pad on top
Evaluation Board with exposed pad on bottom
Evaluation Board with exposed pad on top
Exposed pad is electrically connected internally to AVSS.
Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06197-0-10/08(A)
Rev. A | Page 60 of 60
Package Option
SV-80-3
SV-80-2