Serial Input 16-Bit 4 mA–20 mA, 0 mA–20 mA DAC AD420 FEATURES FUNCTIONAL BLOCK DIAGRAM VCC VLL REFERENCE 4kΩ REF OUT 40Ω BOOST AD420 REF IN DATA OUT CLEAR LATCH CLOCK DATA IN CLOCK DATA I/P REGISTER IOUT 16-BIT DAC RANGE SELECT 1 SWITCHED CURRENT SOURCES AND FILTERING VOUT 1.25kΩ FAULT DETECT RANGE SELECT 2 OFFSET TRIM CAP 1 CAP 2 GND 00494-001 4 mA–20 mA, 0 mA–20 mA or 0 mA–24 mA current output 16-bit resolution and monotonicity ±0.012% max integral nonlinearity ±0.05% max offset (trimmable) ±0.15% max total output error (trimmable) Flexible serial digital interface (3.3 MBPS) On-Chip loop fault detection On-chip 5 V reference (25 ppm/°C max) Asynchronous CLEAR function Maximum power supply range of 32 V Output loop compliance of 0 V to VCC − 2.75 V 24-Lead SOIC and PDIP packages Figure 1. GENERAL DESCRIPTION The AD420 is a complete digital to current loop output converter, designed to meet the needs of the industrial control market. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop signals in a compact 24-lead SOIC or PDIP package. user desires temperature stability exceeding 25 ppm/°C, an external precision reference such as the AD586 can be used as the reference. The AD420 is available in a 24-lead SOIC and PDIP over the industrial temperature range of −40°C to +85°C. The output current range can be programmed to 4 mA to 20 mA, 0 mA to 20 mA or to an overrange function of 0 mA to 24 mA. The AD420 can alternatively provide a voltage output from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V with the addition of a single external buffer amplifier. 1. The AD420 is a single chip solution for generating 4 mA to 20 mA or 0 mA to 20 mA signals at the controller end of the current loop. 2. The AD420 is specified with a power supply range from 12 V to 32 V. Output loop compliance is 0 V to VCC − 2.75 V. The 3.3 M Baud serial input logic design minimizes the cost of galvanic isolation and allows for simple connection to commonly used microprocessors. It can be used in 3-wire or asynchronous mode and a serial-out pin is provided to allow daisy chaining of multiple DACs on the current loop side of the isolation barrier. 3. The flexible serial input can be used in 3-wire mode with SPI® or MICROWIRE® microcontrollers, or in asynchronous mode, which minimizes the number of control signals required. 4. The serial data out pin can be used to daisy chain any number of AD420s together in 3-wire mode. 5. At power-up, the AD420 initializes its output to the low end of the selected range. 6. The AD420 has an asynchronous CLEAR pin, which sends the output to the low end of the selected range (0 mA, 4 mA, or 0 V). 7. The AD420 BOOST pin accommodates an external transistor to off-load power dissipation from the chip. 8. The offset of ±0.05% and total output error of ±0.15% can be trimmed if desired, using two external potentiometers. The AD420 uses sigma-delta (Σ-Δ) DAC technology to achieve 16-bit monotonicity at very low cost. Full-scale settling to 0.1% occurs within 3 ms. The only external components that are required (in addition to normal transient protection circuitry) are two low cost capacitors which are used in the DAC output filter. If the AD420 is used at extreme temperatures and supply voltages, an external output transistor can be used to minimize power dissipation on the chip via the BOOST pin. The FAULT DETECT pin signals when an open circuit occurs in the loop. The on-chip voltage reference can be used to supply a precision +5 V to external components in addition to the AD420 or, if the PRODUCT HIGHLIGHTS Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999–2011 Analog Devices, Inc. All rights reserved. AD420 TABLE OF CONTENTS Features .............................................................................................. 1 Driving Inductive Loads............................................................ 10 Functional Block Diagram .............................................................. 1 Voltage-Mode Output................................................................ 10 General Description ......................................................................... 1 Optional Span and Zero Trim .................................................. 10 Product Highlights ........................................................................... 1 Three-Wire Interface ................................................................. 11 Revision History ............................................................................... 2 Using Multiple DACS with Fault Detect ................................. 11 Specifications..................................................................................... 3 Asynchronous Interface Using Optocouplers ........................ 11 Absolute Maximum Ratings............................................................ 5 Microprocessor Interface............................................................... 12 ESD Caution.................................................................................. 5 AD420-To-MC68HC11 (SPI Bus) Interface........................... 12 Pin Configuration and Function Descriptions............................. 6 AD420 to Microwire Interface ................................................. 12 Timing Requirements ...................................................................... 7 External Boost Function ........................................................... 13 Three-Wire Interface ................................................................... 7 AD420 Protection........................................................................... 14 Three-Wire Interface Fast Edges on Digital Input................... 7 Transient Voltage Protection .................................................... 14 Asynchronous Interface............................................................... 7 Board Layout And Grounding ................................................. 14 Terminology ...................................................................................... 8 Power Supplies and Decoupling............................................... 14 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 15 Applications Information .............................................................. 10 Ordering Guide .......................................................................... 15 Current Output ........................................................................... 10 REVISION HISTORY 1/11—Rev. G to Rev. H Changes to Figure 13...................................................................... 13 Changes to Ordering Guide .......................................................... 15 11/09—Rev. F to Rev. G Updated Format..................................................................Universal Changes to Table 2............................................................................ 5 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 9/99—Rev. E to Rev. F Rev. H | Page 2 of 16 AD420 SPECIFICATIONS TA = TMIN − TMAX, VCC = +24 V, unless otherwise noted. Table 1. Parameter RESOLUTION IOUT CHARACTERISTICS Operating Current Ranges Current Loop Voltage Compliance Settling Time (to 0.1% of FS) 1 Output Impedance (Current Mode) Accuracy 2 Monotonicity Integral Nonlinearity Offset (0 mA or 4 mA) (TA = +25°C) Offset Drift Total Output Error (20 mA or 24 mA) (TA = +25°C) Total Output Error Drift PSRR 3 VOUT CHARACTERISTICS FS Output Voltage Range (Pin 17) VOLTAGE REFERENCE REF OUT Output Voltage (TA = +25° C) Drift Externally Available Current Short Circuit Current REF IN Resistance VLL Output Voltage Externally Available Current Short Circuit Current DIGITAL INPUTS VIH (Logic 1) VIL (Logic 0) IIH (VIN = 5.0 V) IIL (VIN = 0 V) Data Input Rate (3-Wire Mode) Data Input Rate (Asynchronous Mode) DIGITAL OUTPUTS FAULT DEFECT VOH (10 kΩ Pull-Up Resistor to VLL) VOL (10 kΩ Pull-Up Resistor to VLL) VOL @ 2.5 mA DATA OUT VOH (IOH = −0.8 mA) VOL (IOL = 1.6 mA) Min 16 AD420-32 Version Typ Max Units Bits Comments RL = 500 Ω 4 0 0 0 2.5 25 20 20 24 VCC − 2.75 V 3 16 ±0.012 ±0.05 50 ±0.15 50 10 Bits % % ppm/° C % ppm/° C μA/V 5 V 5.005 ±25 5 7 V ppm/° C mA mA 30 kΩ 4.5 5 20 V mA mA ±0.002 20 20 5 0 4.995 5.0 2.4 0.8 ±10 ±10 3.3 150 No Minimum No Minimum 3.6 3.6 Rev. H | Page 3 of 16 mA mA mA V ms MΩ 4.5 0.2 0.6 4.3 0.3 0.4 0.4 V V μA μA MBPS kBPS V V V V V AD420 Parameter POWER SUPPLY Operating Range VCC Quiescent Current Quiescent Current (External VLL) TEMPERATURE RANGE Specified Performance Min AD420-32 Version Typ Max 12 4.2 3 −40 1 Units 32 5.5 V mA mA +85 °C Comments External capacitor selection must be as described in Figure 6. Total Output Error includes Offset and Gain Error. Total Output Error and Offset Error are with respect to the Full-Scale Output and are measured with an ideal +5 V reference. If the internal reference is used, the reference errors must be added to the Offset and Total Output Errors. 3 PSRR is measured by varying VCC from 12 V to its maximum 32 V. 2 Rev. H | Page 4 of 16 AD420 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC to GND IOUT to GND Digital Inputs to GND Digital Output to GND VLL and REF OUT: Outputs Safe for Indefinite Short to Ground Storage Temperature Lead Temperature (Soldering, 10 sec) Lead Temperature, Soldering Reflow Thermal Impedance: SOIC (R) Package PDIP (N) Package Rating 32 V VCC −0.5 V to +7 V −0.5 V to VLL + 0.3 V Table 3. Truth Table −65°C to +150°C +300°C +260°C θJA = 75°C/W θJA = 50°C/W CLEAR 0 1 Inputs Range Select 2 X X Range Select 1 X X X X X X 0 0 1 1 0 1 0 1 ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. H | Page 5 of 16 Operation Normal operation Output at bottom of span 0 V–5 V range 4 mA–20 mA range 0 mA–20 mA range 0 mA–24 mA range AD420 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 24 NC 23 VCC VLL 2 FAULT DETECT 3 22 NC RANGE SELECT 2 4 RANGE SELECT 1 5 21 CAP 2 AD420 20 CAP 1 TOP VIEW 19 BOOST (Not to Scale) LATCH 7 18 IOUT CLEAR 6 DATA OUT 10 GND 11 NC 12 17 VOUT 16 OFFSET TRIM 15 REF IN 14 REF OUT 13 NC NC = NO CONNECT 00494-002 CLOCK 8 DATA IN 9 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 12, 13, 24 2 Mnemonic NC Function No Connection. No internal connections inside device. VLL 3 FAULT DETECT 4 5 6 RANGE SELECT 2 RANGE SELECT 1 CLEAR 7 LATCH 8 CLOCK 9 10 DATA IN DATA OUT 11 14 15 16 17 18 19 GND REF OUT REF IN OFFSET TRIM VOUT IOUT BOOST 20 21 22 23 CAP 1 CAP 2 NC VCC Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage for the digital circuitry and can be used as a termination for pull-up resistors. An external +5 V power supply can be connected to VLL. It will override this buffered voltage, thus reducing the internal power dissipation. The VLL pin should be decoupled to GND with a 0.1 μF capacitor. See the Power Supplies and Decoupling section. FAULT DETECT, connected to a pull-up resistor, is asserted low when the output current does not match the DAC’s programmed value, for example, in case the current loop is broken. Selects the converter’s output operating range. One output voltage range and three output current ranges are available. Valid VIH unconditionally forces the output to go to the minimum of its programmed range. After CLEAR is removed the DAC output will remain at this value. The data in the input register is unaffected. In the 3-wire interface mode a rising edge parallel loads the serial input register data into the DAC. To use the asynchronous mode connect LATCH through a current limiting resistor to VCC. Data Clock Input. The clock period is equal to the input data bit rate in the 3-wire interface mode and is 16 times the bit rate in asynchronous mode. Serial Data Input. Serial Data Output. In the 3-wire interface mode, this output can be used for daisy-chaining multiple AD420s. In the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is received. Ground (Common). +5 V Reference Output. Reference Input. Offset Adjust. Voltage Output. Current Output. Connect to an external transistor to reduce the power dissipated in the AD420 output transistor, if desired. These pins are used for internal filtering. Connect capacitors between each of these pins and VCC. Refer to the description of current output operation. No Connection. Do not connect anything to this pin. Power Supply Input. The VCC pin should always be decoupled to GND with a 0.1 μF capacitor. See the Power Supplies and Decoupling section. Rev. H | Page 6 of 16 AD420 TIMING REQUIREMENTS TA = −40°C to +85°C, VCC = +12 V to +32 V. CLOCK 0 1 BIT0 STOP BIT B13 B12 (INTERNALLY GENERATED LATCH) EXPANDED TIME VIEW BELOW LATCH CLOCK COUNTER STARTS HERE CONFIRM START BIT WORD “N” DATA OUT tCK B14 B15 1 0 1 1 SAMPLE BIT 15 CLOCK B13 B12 WORD “N – 1” 0 1 2 tCL DATA IN 8 16 START BIT 24 DATA BIT 15 BIT 14 tCH tDH tDS EXPANDED TIME VIEW BELOW tACK DATA IN tACL CLOCK tDW tLD LATCH tADS tLL tLH DATA IN 00494-003 tSD DATA OUT Figure 3. Timing Diagram for 3-Wire Interface Label tCK tCL tCH tDW tDS tDH tLD tLL tLH tSD tCLR Limit 300 80 80 125 40 5 80 80 80 225 50 Figure 4. Timing Diagram for Asynchronous Interface Table 6. Timing Specifications for Asynchronous Interface Table 5. Timing Specification for 3-Wire Interface Parameter Data Clock Period Data Clock Low Time Data Clock High Time Data Stable Width Data Setup Time Data Hold Time Latch Delay Time Latch Low Time Latch High Time Serial Output Delay Time Clear Pulse Width tADW tACH tADH 00494-004 CLOCK 0 NEXT START BIT 1 0 0 1 (LSB) B15 B14 0 1 1 1 BIT13 TO BIT1 START BIT WORD “N + 1” 0 0 1 1 1 0 B2 B1 B0 B10 B9 B14 B13 B12 B11 (MSB) B15 1 0 1 1 0 0 1 B8 B7 B6 B5 B4 B3 WORD “N” DATA IN 0 BIT14 DATA IN CLOCK BIT15 THREE-WIRE INTERFACE Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min THREE-WIRE INTERFACE FAST EDGES ON DIGITAL INPUT With a fast rising edge (<10 ns) on one of the serial inputs (CLOCK, DATA IN, LATCH) while another input is logic high, the part may be triggered into a test mode and the contents of the data register may become corrupted, which may result in the output being loaded with an incorrect value. If fast edges are expected on the digital input lines, it is recommended that the latch line remain at Logic 0 during serial loading of the DAC. Similarly, the clock line should remain low during updates of the DAC via the latch pin. Alternatively, the addition of small value capacitors on the digital lines will slow down the edge. Parameter Asynchronous Clock Period Asynchronous Clock Low Time Asynchronous Clock High Time Data Stable Width (Critical Clock Edge) Data Setup Time (Critical Clock Edge) Data Hold Time (Critical Clock Edge) Clear Pulse Width Label tACK tACL tACH tADW tADS tADH tCLR Limit 400 50 150 300 60 20 50 Units ns min ns min ns min ns min ns min ns min ns min ASYNCHRONOUS INTERFACE Note that in the timing diagram for asynchronous mode operation each data word is framed by a START (0) bit and a STOP (1) bit. The data timing is with respect to the rising edge of the CLOCK at the center of each bit cell. Bit cells are 16 clocks long, and the first cell (the START bit) begins at the first clock following the leading (falling) edge of the START bit. Thus, the MSB (D15) is sampled 24 clock cycles after the beginning of the START bit, D14 is sampled at clock number 40, and so on. During any dead time before writing the next word the DATA IN pin must remain at Logic 1. The DAC output updates when the STOP bit is received. In the case of a framing error (the STOP bit sampled as a 0) the AD420 will output a pulse at the DATA OUT pin one clock period wide during the clock period subsequent to sampling the STOP bit. The DAC output will not update if a framing error is detected. Rev. H | Page 7 of 16 AD420 TERMINOLOGY Resolution For 16-bit resolution, 1 LSB = 0.0015% of the FSR. In the 4 mA–20 mA range 1 LSB = 244 nA. Integral Nonlinearity Analog Devices defines integral nonlinearity as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from 0 to FS – 1 LSB) for any bit combination. This is also referred to as relative accuracy. Gain Error Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Offset Error Offset error is the deviation of the output current from its ideal value expressed as a percentage of the fullscale output with all 0s loaded in the DAC. Differential Nonlinearity Differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with an LSB change in the digital input code. Monotonic behavior requires that the differential linearity error be greater than –1 LSB over the temperature range of interest. Drift Drift is the change in a parameter (such as gain and offset) over a specified temperature range. The drift temperature coefficient, specified in ppm/°C, is calculated by measuring the parameter at TMIN, 25°C, and TMAX and dividing the change in the parameter by the corresponding temperature change. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. Current Loop Voltage Compliance The voltage compliance is the maximum voltage at the IOUT pin for which the output current will be equal to the programmed value. Rev. H | Page 8 of 16 AD420 THEORY OF OPERATION In the AD420 a second order modulator is used to keep complexity and die size to a minimum. The single bit stream from the modulator controls a switched current source that is then filtered by two, continuous time resistor-capacitor sections. The capacitors are the only external components that have to be added for standard current-out operation. The filtered current is amplified and mirrored to the supply rail so that the application simply sees a 4 mA–20 mA, 0 mA–20 mA, or 0 mA–24 mA current source output with respect to ground. The AD420 is manufactured on a BiCMOS process that is well suited to implementing low voltage digital logic with high performance and high voltage analog circuitry. The AD420 can also provide a voltage output instead of a current loop output if desired. The addition of a single external amplifier allows the user to obtain 0 V–5 V, 0 V–10 V, ±5 V, or ±10 V. The AD420 has a loop fault detection circuit that warns if the voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The FAULT DETECT is an active low open drain signal so that one can connect several AD420s together to one pull-up resistor for global error detection. The pull-up resistor can be tied to the VLL pin, or an external +5 V logic supply. The IOUT current is controlled by a PMOS transistor and an internal amplifier as shown in the functional block diagram. The internal circuitry that develops the fault output avoids using a comparator with window limits since this would require an actual output error before the FAULT DETECT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage of the AD420 has less than approximately one volt remaining of drive capability (when the gate of the output PMOS transistor nearly reaches ground). Thus the FAULT DETECT output activates slightly before the compliance limit is reached. Since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and no output error occurs before the fault detect output becomes active. The 3-wire digital interface, comprising DATA IN, CLOCK, and LATCH, interfaces to all commonly used serial microprocessors without the addition of any external glue logic. Data is loaded into an input register under control of CLOCK and is loaded to the DAC when LATCH is strobed. If a user wants to minimize the number of galvanic isolators in an intrinsically safe application, the AD420 can be configured to run in asynchronous mode. This mode is selected by connecting the LATCH pin to VCC through a current limiting resistor. The data must then be combined with a start and stop bit to frame the information and trigger the internal LATCH signal. VCC 23 VLL 2 REFERENCE 4kΩ REF OUT 14 40Ω AD420 19 BOOST 18 IOUT 17 VOUT 3 FAULT DETECT REF IN 15 CLOCK DATA OUT 10 CLEAR 6 LATCH 7 CLOCK 8 DATA I/P REGISTER 16-BIT DAC DATA IN 9 RANGE SELECT 1 5 RANGE 4 SELECT 2 Rev. H | Page 9 of 16 16 SWITCHED CURRENT SOURCES AND FILTERING 20 21 OFFSET CAP 1 CAP 2 TRIM 1.25kΩ 11 GND Figure 5. Functional Block Diagram 00494-005 The AD420 uses a sigma-delta (Σ-Δ) architecture to carry out the digital-to-analog conversion. This architecture is particularly well suited for the relatively low bandwidth requirements of the industrial control environment because of its inherent monotonicity at high resolution. AD420 APPLICATIONS INFORMATION CURRENT OUTPUT Table 7. Buffer Amplifier Configuration The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA– 24 mA output without any active external components. Filter capacitors C1 and C2 can be any type of low cost ceramic capacitors. To meet the specified full-scale settling time of 3 ms, low dielectric absorption capacitors (NPO) are required. Suitable values are C1 = 0.01 μF and C2 = 0.01 μF. R1 Open Open R R 0.1µF C1 2 RANGE SELECT 1 RANGE SELECT 2 21 23 5 4 CLEAR 6 LATCH 7 CLOCK 8 18 AD420 IOUT (4mA TO 20mA) RLOAD 14 15 REF IN 11 00494-006 REF OUT Suitable R = 5 kΩ. The adjustment algorithm is iterative. The procedure for trimming the AD420 in the 4 mA–20 mA mode can be accomplished as follows: 9 DATA IN GND 1. Offset adjust. Load all zeros. Adjust RZERO for 4.00000 mA of output current. Gain adjust. Load all ones. Adjust RSPAN for 19.99976 mA (FS − 1 LSB) of output current. Figure 6. Standard Configuration 2. DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads ,connect a 0.01 μF capacitor between IOUT (Pin 18) and GND (Pin 11). This ensures stability of the AD420 with loads beyond 50 mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling, though this may be masked by the settling time of the AD420. A programmed change in the current may cause a back EMF voltage on the output that may exceed the compliance of the AD420. To prevent this voltage from exceeding the supply rails connect protective diodes between IOUT and each of VCC and GND. VOLTAGE-MODE OUTPUT Return to Step I and iterate until convergence is obtained. VCC VLL 0.1µF RANGE SELECT 1 RANGE SELECT 2 0.1µF 2 C2 20 21 4 LATCH 7 CLOCK 8 DATA IN 9 REF OUT 23 7 CLOCK 8 BOOST 19 AD420 18 IOUT (4mA TO 20mA) RLOAD 9 REF OUT 14 15 16 11 500Ω RSPAN 10kΩ GND RZERO Variation of RZERO between REF OUT (5 V) and GND leads to an offset adjust range from −1.5 mA to 6 mA, (1.5 mA/V centered at 1 V). 23 5 6 21 5kΩ RSPAN2 Figure 8. Offset and Gain Adjust C1 CLEAR 20 4 6 0.1µF 17 AD420 VOUT The 5 kΩ RSPAN2 resistor is connected in parallel with the internal 40 W sense resistor, which leads to a gain increase of +0.8%. VOUT R3 R1 14 15 REF IN 11 Figure 7. GND R2 00494-007 RANGE SELECT 1 RANGE SELECT 2 2 0.1µF C2 5 LATCH DATA IN VCC C1 CLEAR Since the AD420 is a single supply device, it is necessary to add an external buffer amplifier to the VOUT pin to obtain a selection of bipolar output voltage ranges as shown in Figure 7. VLL ±5 V ±10 V For users who would like lower than the specified values of offset and gain error, Figure 8 shows a simple way to trim these parameters. Care should be taken to select low drift resistors because they affect the temperature drift performance of the DAC. C2 20 VOUT 0V−5V OPTIONAL SPAN AND ZERO TRIM 0.1µF VLL R3 0 R R 2R 00494-008 VCC R2 Open R Open 2R As RSPAN is changed to 500 Ω, the voltage on REF IN is attenuated by the combination of RSPAN and the 30 kΩ REF IN input resistance. When added together with RSPAN2 this results in an adjustment range of −0.8% to +0.8%. Rev. H | Page 10 of 16 AD420 Figure 9 shows the AD420 connected in the 3-wire interface mode. The AD420 data input block contains a serial input shift register and a parallel latch. The contents of the shift register are controlled by the DATA IN signal and the rising edges of the CLOCK. Upon request of the LATCH pin the DAC and internal latch are updated from the shift register parallel outputs. The CLOCK should remain inactive while the DAC is updated. Refer to the timing requirements for 3-wire interface. FAULT DETECT DAC1 FAULT DETECT LATCH CLOCK DATA IN VCC VLL 10kΩ VCC AD420 DAC2 FAULT DETECT LATCH LATCH CLOCK CLOCK DATA IN DATA OUT GND IOUT VCC VCC DATA IN DATA OUT GND IOUT RLOAD RLOAD 00494-009 AD420 ASYNCHRONOUS INTERFACE USING OPTOCOUPLERS The AD420 connected in asynchronous interface mode with optocouplers is shown in Figure 10. Asynchronous operation minimizes the number of control signals required for isolation of the digital system from the control loop. The resistor connected between the LATCH pin and VCC is required to activate this mode. For operation with VCC below 18 V use a 50 kΩ pull-up resistor; from 18 V to 32 V, use 100 kΩ. Asynchronous mode requires that the clock run at 16 times the data bit rate, therefore, to operate at the maximum input data rate of 150 kBPS, an input clock of 2.4 MHz is required. The actual data rate achieved may be limited by the type of optocouplers chosen. The number of control signals can be further reduced by creating the appropriate clock signal on the current loop side of the isolation barrier. If optocouplers with relatively slow rise and fall times are used, Schmitt triggers may be required on the digital inputs to prevent erroneous data being presented to the DAC. +24V Figure 9. Three-Wire Interface Using Multiple DACs with Joint Fault Detect USING MULTIPLE DACS WITH FAULT DETECT 23 VCC 7 LATCH 2 VLL 8 CLOCK 9 DATA IN 11 GND 100kΩ The 3-wire interface mode can utilize the serial DATA OUT for easy interface to multiple DACs. To program the two AD420s in Figure 9, 32 data bits are required. The first 16 bits are clocked into the input shift register of DAC1. The next 16 bits transmitted pass the first 16 bits from the DATA OUT pin of DAC1 to the input register of DAC2. The input shift registers of the two DACs operate as a single 32-bit shift register, with the leading 16 bits representing information for DAC2 and the trailing 16 bits serving for DAC1. Each DAC is then updated upon request of the LATCH pin. The daisy-chain can be extended to as many DACs as required. Rev. H | Page 11 of 16 +5V AD420 CLOCK DATA GALVANIC BARRIER ISOLATION Figure 10. Asynchronous Interface Using Optocouplers 00494-010 THREE-WIRE INTERFACE AD420 MICROPROCESSOR INTERFACE INIT NEXTPT SENDAT WAIT1 WAIT2 LDAA #$2F STAA LDAA PORTD #$38 STAA DDRD LDAA #$50 STAA SPCR LDAA MSBY BSR SENDAT JMP NEXTPT LDY #$1000 BCLR $08,Y,$20 STAA SPDR LDAA SPSR BPL WAIT1 LDAA LSBY STAA SPDR LDAA SPSR BPL WAIT2; BSET $08,Y,$20 ; SS = 1; SCK = 0; MOSI = 1 ;SEND TO SPI OUTPUTS ; SS, SCK, MOSI = OUTPUTS ;SEND DATA DIRECTION INFO ;DABL INTRPTS, SPI IS MASTER & ON ;CPOL = 0, CPHA = 0, 1MHZ BAUDRATE ;LOAD ACCUM W/UPPER 8 BITS ;JUMP TO DAC OUTPUT ROUTINE ;INFINITE LOOP ;POINT AT ON-CHIP REGISTERS ;DRIVE SS (LATCH) LOW ;SEND MS-BYTE TO SPI DATA REG ;CHECK STATUS OF SPIE ;POLL FOR END OF XMISSION ;GET LOW 8 BITS FROM MEMORY ;SEND LS-BYTE TO SPI DATA REG ;CHECK STATUS OF SPIE ;POLL FOR END OF XMISSION ;DRIVE SS HIGH TO LATCH DATA 68HC11 MOSI DATA IN SCK CLOCK SS LATCH AD420 00494-011 The AD420 interface to the Motorola serial peripheral interface (SPI) is shown in Figure 11. The MOSI, SCK, and SS pins of the HC11 are respectively connected to the DATA IN, CLOCK, and LATCH pins of the AD420. The majority of the interfacing issues are done in the software initialization. A typical routine, such as the one shown below, begins by initializing the state of the various SPI data and control registers. The SPI data port is configured to process data in 8-bit bytes. The most significant data byte (MSBY) is retrieved from memory and processed by the SENDAT routine. The SS pin is driven low by indexing into the PORTD data register and clear Bit 5. The MSBY is then sent to the SPI data register where it is automatically transferred to the AD420 internal shift resister. The HC11 generates the requisite eight clock pulses with data valid on the rising edges. After the MSBY is transmitted, the least significant byte (LSBY) is loaded from memory and transmitted in a similar fashion. To complete the transfer, the LATCH pin is driven high when loading the complete 16-bit word into the AD420. Figure 11. AD420-to-68HC11 (SPI) Interface AD420 TO MICROWIRE INTERFACE The flexible serial interface of the AD420 is also compatible with the National Semiconductor MICROWIRE interface. The MICROWIRE interface is used in microcontrollers such as the COP400 and COP800 series of processors. A generic interface to use the MICROWIRE interface is shown in Figure 12. The G1, SK, and SO pins of the MICROWIRE interface are respectively connected to the LATCH, CLOCK, and DATA IN pins of the AD420. RTS Rev. H | Page 12 of 16 MICROWIRE SO DATA IN SK CLOCK G1 LATCH AD420 Figure 12. AD420-to-MICROWIRE Interface 00494-012 AD420-TO-MC68HC11 (SPI BUS) INTERFACE AD420 EXTERNAL BOOST FUNCTION The external boost transistor reduces the power dissipated in the AD420 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN transistor with a breakdown voltage, BVCEO, greater than 32 V can be used as shown in Figure 13. WHEN USING SOIC PACKAGED DEVICES, AN EXTERNAL BOOST TRANSISTOR IS REQUIRED FOR OPERATION IN THIS AREA. VCC MJD31C OR 2N3053 BOOST 19 32V AD420 28V IOUT 18 25V 20V AD420 OR AD420-32 Figure 13. External Boost Configuration 12V The external boost capability has been developed for those users who may wish to use the AD420, in the SOIC package, at the extremes of the supply voltage, load current, and temperature range. The PDIP package (because of its lower thermal resistance) will operate safely over the entire specified voltage, temperature, and load current ranges without the boost 4V –60 Rev. H | Page 13 of 16 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 14. Safe Operating Region 100 00494-014 1kΩ RLOAD 00494-013 0.022µF transistor. The plot in Figure 14 shows the safe operating region for both package types. The boost transistor can also be used to reduce the amount of temperature induced drift in the part. This will minimize the temperature induced drift of the on-chip voltage reference, which improves drift and linearity. AD420 BOARD LAYOUT AND GROUNDING AD420 PROTECTION TRANSIENT VOLTAGE PROTECTION The AD420 contains ESD protection diodes, which prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD420 from excessively high voltage transients, such as those specified in IEC 801, external power diodes and a surge current limiting resistor may be required, as shown in Figure 15. The constraint on the resistor is that during normal operation the output voltage level at IOUT must remain within its voltage compliance limit (IOUT × (Rp + RLOAD) ≤ VCC − 2.75 V) and the two protection diodes and resistor must have appropriate power ratings. VCC VCC IOUT GND RP POWER SUPPLIES AND DECOUPLING The AD420 supply pins, VCC (Pin 23) and VLL (Pin 2), should be decoupled to GND with 0.1 μF capacitors to eliminate high frequency noise that may otherwise get coupled into the analog system. High frequency ceramic capacitors are recommended. The decoupling capacitors should be located in close proximity to the pins and the ground line to have maximum effect. Further reductions in noise, and improvements in performance, may be achieved by using a larger value capacitor on the VLL pin. RLOAD 00494-015 AD420 The AD420 ground pin, designated GND, is the high quality ground reference point for the device. Any external loads on the REF OUT and VOUT pins of the AD420 should be returned to this reference point. Analog and digital ground currents should not share a common path. Each signal should have an appropriate analog or digital signal return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. Figure 15. Output Transient Voltage Protection Rev. H | Page 14 of 16 AD420 OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 12 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 071006-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 16. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 15.60 (0.6142) 15.20 (0.5984) 13 24 7.60 (0.2992) 7.40 (0.2913) 12 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 06-07-2006-A 1 Figure 17. 24-Lead Standard Small Outline [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 AD420AN-32 AD420ANZ-32 AD420AR-32 AD420AR-32-REEL AD420ARZ-32 AD420ARZ-32-REEL 1 Temperature Range −40°C to +85° C −40°C to +85° C −40°C to +85° C −40°C to +85° C −40°C to +85° C −40°C to +85° C Max Operating Voltage 32 V 32 V 32 V 32 V 32 V 32 V Z = RoHS Compliant Part. Rev. H | Page 15 of 16 Package Description 24-Lead PDIP 24-Lead PDIP 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W Package Option N-24-1 N-24-1 RW-24 RW-24 RW-24 RW-24 AD420 NOTES ©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00494-0-1/11(H) Rev. H | Page 16 of 16