AD AD5554

a
FEATURES
AD5544 16-Bit Resolution
AD5554 14-Bit Resolution
2 mA Full-Scale Current 20%, with VREF = 10 V
2 s Settling Time
V SS BIAS for Zero-Scale Error Reduction @ Temp
Midscale or Zero-Scale Reset
Four Separate 4Q Multiplying Reference Inputs
SPI-Compatible 3-Wire Interface
Double Buffered Registers Enable
Simultaneous Multichannel Change
Internal Power ON Reset
Compact SSOP-28 Package
Quad, Current-Output
Serial-Input, 16-Bit/14-Bit DACs
AD5544/AD5554
FUNCTIONAL BLOCK DIAGRAM
VREF A B C D
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
SDO
SDI
APPLICATIONS
Automatic Test Equipment
Instrumentation
Digitally-Controlled Calibration
VDD
RFBA
INPUT
REGISTER R
DAC A
REGISTER R
DAC A
IOUTA
AGNDA
RFBB
16
INPUT
REGISTER R
DAC B
REGISTER R
DAC B
IOUTB
AGNDB
RFBC
INPUT
REGISTER R
DAC C
REGISTER R
DAC C
IOUTC
AGNDC
CS
RFBD
EN
CLK
INPUT
REGISTER R
DAC A
B
C
D
2:4
DECODE
DAC D
REGISTER R
DAC D
IOUTD
AGNDD
POWERON
RESET
RS
DGND
MSB
AD5544
LDAC
AGNDF
VSS
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current-output, digitalto-analog converters are designed to operate from a single 5 V
supply.
1.0
The applied external reference input voltage (VREF) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
0.0
–0.5
–1.0
1.0
DAC B
0.5
0.0
INL – LSB
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI- and microcontroller-compatible inputs using
serial-data-in (SDI), clock (CLK), and a chip-select (CS). In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common level-sensitive
load-DAC strobe (LDAC) input allows simultaneous update of
all DAC outputs from previously loaded input registers. Additionally, an internal power ON reset forces the output voltage to
zero at system turn ON. An MSB pin allows system reset assertion (RS) to force all registers to zero code when MSB = 0, or
to half-scale code when MSB = 1.
DAC A
0.5
–0.5
–1.0
1.0
DAC C
0.5
0.0
–0.5
–1.0
1.0
DAC D
0.5
0.0
AD5544/AD5554 are packaged in the compact SSOP-28.
–0.5
–1.0
0
8192
16384 24576 32768 40960 49152 57344 65536
CODE – Decimal
Figure 1. AD5544 INL vs. Code Plot (TA = 25 °C)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
I X = Virtual GND, A X = 0 V,
AD5544/AD5554–SPECIFICATIONS (@V VA, B,=C,5 VD = 1010%,V, TV ==Full0 V,Operating
Temperature Range,
DD
REF
AD5544 ELECTRICAL CHARACTERISTICS
Parameter
SS
OUT
GND
A
unless otherwise noted.)
Symbol
Condition
Min
1 LSB = VREF/216 = 153 µV when VREF = 10 V
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
N
INL
DNL
IOUTX
IOUTX
GFSE
TCVFS
RFBX
REFERENCE INPUT
VREFX Range
Input Resistance
Input Resistance Match
Input Capacitance2
VREFX
RREFX
RREFX
CREFX
ANALOG OUTPUT
Output Current
Output Capacitance2
IOUTX
COUTX
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
VIL
VIH
IIL
CIL
VOL
VOH
Typ
Max
Unit
16
±4
± 1.5
10
20
±3
Bits
LSB
LSB
nA
nA
mV
ppm/°C
kΩ
1
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA Max
Data = FFFFH
VDD = 5 V
4
–15
4
8
+15
8
V
kΩ
%
pF
2.5
mA
pF
0.8
4
V
V
µA
pF
V
V
25
25
0
25
2
25
20
20
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Channel-to-Channel
Data = FFFFH
Code-Dependent
± 0.75
1
6
6
1
5
1.25
80
2.4
1
10
0.4
IOL = 1.6 mA
IOH = 100 µA
2, 3
INTERFACE TIMING
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Clock to SDO Prop Delay
Load DAC Pulsewidth
Data Setup
Data Hold
Load Setup
Load Hold
tCH
tCL
tCSS
tCSH
tPD
tLDAC
tDS
tDH
tLDS
tLDH
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
ISS
PDISS
PSS
20
4.5
Logic Inputs = 0 V
Logic Inputs = 0 V, VSS = –5 V
Logic Inputs = 0 V
∆VDD = ± 5%
50
0.001
5.5
250
1
1.25
0.006
V
µA
µA
mW
%/%
NOTES
1
All static performance tests (except I OUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544
RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25 °C.
2
These parameters are guaranteed by design and not subject to production testing.
3
All input control signals are specified with t R = t F = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
–2–
REV. 0
AD5544/AD5554
AD5544 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
(@ VDD = 5 V 10%, VSS = –300 mV, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = full operating temperature range, unless
otherwise noted.)
Condition
Min
Typ Max Unit
1
AC CHARACTERISTICS
Output Voltage Settling Time tS
To ± 0.1% of Full Scale, Data = 0000H
to FFFFH to 0000H
Output Voltage Settling Time tS
To ± 0.0015% of Full Scale, Data = 0000H
to FFFFH to 0000H
Reference Multiplying BW
BW –3 dB
VREFX = 100 mV rms, Data = FFFFH,
CFB = 15 pF
DAC Glitch Impulse
Q
VREFX = 10 V, Data 0000H to 8000H to 0000H
Feedthrough Error
VOUTX/VREFX Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
Crosstalk Error
VOUTA/VREFB Data = 0000H, VREFB = 100 mV rms,
Adjacent Channel, f = 100 kHz
Digital Feedthrough
Q
CS = 1, and fCLK = 1 MHz
Total Harmonic Distortion
THD
VREF = 5 V p-p, Data = FFFFH, f = 1 kHz
Output Spot Noise Voltage
eN
f = 1 kHz, BW = 1 Hz
NOTES
1
All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
Specifications subject to change without notice.
REV. 0
–3–
1
µs
2
µs
2
MHz
1.2
–65
–90
nV-s
dB
dB
5
–90
7
nV-s
dB
nV/√Hz
AD5544/AD5554–SPECIFICATIONS
AD5554 ELECTRICAL CHARACTERISTICS
Parameter
(@ VDD = 5 V 10%, VSS = 0 V, IOUTX = Virtual GND, AGNDX = 0 V,
VREFA, B, C, D = 10 V, TA = full operating temperature range,
unless otherwise noted.)
Symbol
Condition
Min
1 LSB = VREF/214 = 610 µV when VREF = 10 V
Full-Scale Gain Error
Full-Scale Tempco2
Feedback Resistor
N
INL
DNL
IOUTX
IOUTX
GFSE
TCVFS
RFBX
REFERENCE INPUT
VREFX Range
Input Resistance
Input Resistance Match
Input Capacitance2
VREFX
RREFX
RREFX
CREFX
ANALOG OUTPUT
Output Current
Output Capacitance2
IOUTX
COUTX
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance2
Logic Output Low Voltage
Logic Output High Voltage
VIL
VIH
IIL
CIL
VOL
VOH
Typ
Max
Unit
14
±1
±1
10
20
± 10
Bits
LSB
LSB
nA
nA
mV
ppm/°C
kΩ
1
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Output Leakage Current
Data = 0000H, TA = 25°C
Data = 0000H, TA = TA Max
Data = 3FFFH
VDD = 5 V
4
–15
4
8
+15
8
V
kΩ
%
pF
2.5
mA
pF
0.8
4
V
V
µA
pF
V
V
25
25
0
25
2
25
20
20
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Channel-to-Channel
Data = 3FFFH
Code-Dependent
±2
1
6
6
1
5
1.25
80
2.4
1
10
0.4
IOL = 1.6 mA
IOH = 100 µA
2, 3
INTERFACE TIMING
Clock Width High
Clock Width Low
CS to Clock Setup
Clock to CS Hold
Clock to SDO Prop Delay
Load DAC Pulsewidth
Data Setup
Data Hold
Load Setup
Load Hold
tCH
tCL
tCSS
tCSH
tPD
tLDAC
tDS
tDH
tLDS
tLDH
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
ISS
PDISS
PSS
20
4.5
Logic Inputs = 0 V
Logic Inputs = 0 V, VSS = –5 V
Logic Inputs = 0 V
∆VDD = ± 5%
50
0.001
5.5
250
1
1.25
0.006
V
µA
µA
mW
%/%
NOTES:
1
All static performance tests (except I OUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554
RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25 °C.
2
These parameters are guaranteed by design and not subject to production testing.
3
All input control signals are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
–4–
REV. 0
AD5544/AD5554
AD5554 ELECTRICAL CHARACTERISTICS
Parameter
Symbol
(@ VDD = 5 V 10%, VSS = –300 mV, IOUTX = Virtual GND, AGNDX = 0 V, VREFA,
B, C, D = 10 V, TA = full operating temperature range, unless otherwise
noted.)
Condition
Min Typ Max Unit
1
AC CHARACTERISTICS
Output Voltage Settling Time tS
To ± 0.1% of Full Scale, Data = 0000H
to 3FFFH to 0000H
Output Voltage Settling Time tS
To ± 0.0015% of Full Scale, Data = 0000H
to 3FFFH to 0000H
Reference Multiplying BW
BW –3 dB
VREFX = 100 mV rms, Data = 3FFFH, CFB = 15 pF
DAC Glitch Impulse
Q
VREFX = 10 V, Data 0000H to 2000H to 0000H
Feedthrough Error
VOUTX/VREFX Data = 0000H, VREFX = 100 mV rms, f = 100 kHz
Crosstalk Error
VOUTA/VREFB Data = 0000H, VREFB = 100 mV rms,
Adjacent Channel, f = 100 kHz
Digital Feedthrough
Q
CS = 1, and fCLK = 1 MHz
Total Harmonic Distortion
THD
VREF = 5 V p-p, Data = 3FFFH, f = 1 kHz
Output Spot Noise Voltage
eN
f = 1 kHz, BW = 1 Hz
1
µs
2
µs
2
1.2
–65
MHz
nV-s
dB
–90
5
–90
7
dB
nV-s
dB
nV/√Hz
NOTES:
1
All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V, +18 V
Logic Inputs and Output to GND . . . . . . . . . . . . –0.3 V, +8 V
V(IOUT) to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
AGNDX to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, + 0.3 V
Input Current to Any Pin Except Supplies . . . . . . . . . ± 50 mA
Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance θJA
28-Lead Shrink Surface-Mount (RS-28) . . . . . . . . 100°C/W
Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150°C
Operating Temperature Range
Model A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature:
RS-28 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C
RS-28 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
RES
Bit
INL
LSB
DNL
LSB
Temperature
Range
Package
Description
Package
Option
AD5544ARS
AD5554BRS
16
14
±4
±1
± 1.5
±1
–40/+85°C
–40/+85°C
SSOP-28
SSOP-28
RS-28
RS-28
The AD5544/AD5554 contain 4196 transistors. The die size is 122 mil × 204 mil.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5544/AD5554 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
AD5544/AD5554
SDI
A1
A0
D15
D14
D13
D12
D11
D10
D1
D0
INPUT
REG
LD
CLK
CS
tDS
tCSS
tDH
tCH
tCL
tCSH
tLDS
LDAC
tLDH
tLDAC
tPD
SDO
Figure 2. AD5544 Timing Diagram
SDI
A1
A0
D13
D12
D11
D10
D09
D08
D1
D0
INPUT
REG
LD
CLK
CS
tDS
tCSS
tDH
tCH
tCL
tCSH
tLDS
LDAC
tLDH
tLDAC
tPD
SDO
Figure 3. AD5554 Timing Diagram
Table I. AD5544 Control-Logic Truth Table
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function DAC Register
H
L
L
L
↑+
X
L
↑+
H
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
H
H
H
H
H
X
X
X
X
X
L
H
↑+
H
H
H
H
H
L
L
X
X
X
0
H
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Latched
Selected DAC Updated
with Current SR Contents
Latched
Latched
Latched
Latched Data = 0000H
Latched Data = 8000H
–6–
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched Data = 0000H
Latched Data = 8000H
REV. 0
AD5544/AD5554
Table II. AD5554 Control-Logic Truth Table
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function DAC Register
H
L
L
L
↑+
X
L
↑+
H
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
H
H
H
H
H
X
X
X
X
X
L
H
↑+
H
H
H
H
H
L
L
X
X
X
0
H
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Latched
Selected DAC Updated
with Current SR Contents
Latched
Latched
Latched
Latched Data = 0000H
Latched Data = 2000H
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched Data = 0000H
Latched Data = 2000H
NOTES
1. SR = Shift Register.
2. ↑+ positive logic transition; X = Don’t Care.
3. At power ON both the Input Register and the DAC Register are loaded with all zeros.
4. For AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.
5. For AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.
Table III. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
Bit Position B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
Data Word A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1 D0
NOTE
Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored, only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.
Table IV. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
Bit Position B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A1
NOTE
Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5554 shift register are ignored, only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.
Table V. Address Decode
A1
A0
DAC Decoded
0
0
1
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
REV. 0
–7–
AD5544/AD5554
AD5544/AD5554 PIN FUNCTION DESCRIPTIONS
Pin # Name
1
2
3
4
5
6
AGNDA
IOUTA
VREFA
RFBA
MSB
RS
7
8
VDD
CS
9
10
11
12
13
14
15
16
17
18
19
20
CLK
SDI
RFBB
VREFB
IOUTB
AGNDB
AGNDC
IOUTC
VREFC
RFBC
NC
SDO
21
LDAC
22
23
24
25
26
27
28
AGNDF
VSS
DGND
RFBD
VREFD
IOUTD
AGNDD
Function
DAC A Analog Ground.
DAC A Current Output.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.
Establish Voltage Output for DAC A by Connecting to External Amplifier Output.
MSB Bit Set Pin During a Reset Pulse (RS) or at System Power ON if Tied to Ground or VDD.
Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for
AD5544 and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB
= 0. Register Data = 8000H for AD5544 and 2000H for AD5554 when MSB = 1.
Positive Power Supply Input. Specified range of operation 5 V ± 10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the Input
Register when CS/LDAC returns High. Does not effect LDAC operation.
Clock Input, Positive Edge Clocks Data into Shift Register.
Serial Data Input, Input Data Loads Directly into the Shift Register.
Establish Voltage Output for DAC B by Connecting to External Amplifier Output.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.
DAC B Current Output.
DAC B Analog Ground.
DAC C Analog Ground.
DAC C Current Output.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC C by connecting to external amplifier output.
No Connect. Leave pin unconnected.
Serial Data Output, input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for
AD5544 and 17 clock pulses for AD5554 after input at the SDI pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to DAC registers. Asynchronous active low input. See Control Logic Truth Table for operation.
High Current Analog Force Ground.
Negative Bias Power Supply Input. Specified range of operation –0.3 V to –5.5 V.
Digital Ground Pin.
Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.
DAC D Current Output.
DAC D Analog Ground.
AD5544/AD5554 PIN CONFIGURATION
AGNDA 1
28
AGNDD
IOUTA 2
27
IOUTD
VREFA 3
26
VREFD
RFBA 4
25
RFBD
MSB 5
RS 6
AD5544/
AD5554
24
DGND
23
VSS
VDD 7
TOP VIEW 22 AGNDF
CS 8 (Not to Scale) 21 LDAC
CLK 9
20
SDI 10
19
SDO
NC
RFBB 11
18
RFBC
VREFB 12
17
VREFC
IOUTB 13
16
IOUTC
AGNDB 14
15
AGNDC
NC = NO CONNECT
–8–
REV. 0
Typical Performance Characteristics–AD5544/AD5554
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.50
0.25
0.00
–0.25
DAC A
–0.50
0.50
0.25
DNL – LSB
DNL – LSB
0.00
–0.25
DAC B
–0.50
0.50
0.25
0.00
–0.25
DAC C
–0.50
0.25
0.00
–0.25
DAC D
–0.50
0
8192
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
16384 24576 32768 40960 49152 57344 65536
CODE – Decimal
TPC 1. AD5544 DNL vs. Code (TA = 25 °C)
1.0
0
2048
4096
6144
8192
10240 12288 14336 16384
CODE – Decimal
2.0
INTEGRAL NONLINEARITY ERROR – LSB
0.0
–1.0
1.0
DAC B
0.5
0.0
INL – LSB
DAC D
TPC 3. AD5554 DNL vs. Code (TA = 25 °C)
–0.5
–0.5
–1.0
1.0
DAC C
0.5
0.0
–0.5
–1.0
1.5
DAC D
0.5
VDD = 5V
VREF = 10V
TA = 25C
F000H
1.0
8000H
0.5
0
7FFFH
–0.5
0FFFH
–1.0
–1.5
–2.0
–1500
1.0
–1000
0
–500
500
1000
OP AMP OFFSET VOLTAGE – V
1500
TPC 4. AD5544 Integral Nonlinearity Error vs.
Op Amp Offset
0.0
–0.5
0
2048
4096
6144
8192
10240 12288 14336 16384
CODE – Decimal
TPC 2. AD5554 INL vs. Code (TA = 25 °C)
REV. 0
DAC C
DAC A
0.5
–1.0
DAC B
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.75
0.50
0.25
0.00
–0.25
–0.50
–0.75
0.50
DAC A
–9–
AD5544/AD5554
10.0
VDD = 5V
VREF = 10V
TA = 25C
0.50
VDD = 5V
VREF = 10V
TA = 25C
7.5
3000H
5.0
GAIN ERROR – LSB
INTEGRAL NONLINEARITY ERROR – LSB
0.75
0.25
2000H
0.00
1FFFH
–0.25
0FFFH
2.5
0.0
–2.5
–5.0
–0.50
–7.5
–0.75
0
500
1000
–2000 –1500 –1000 –500
OP AMP OFFSET VOLTAGE – V
1500
–10.0
–1500
2000
TPC 5. AD5554 Integral Nonlinearity Error vs.
Op Amp Offset
GAIN ERROR – LSB
DIFFERENTIAL NONLINEARITY ERROR – LSB
2
F000H
0.00
0FFFH
–0.25
–0.50
1
0
–1
–2
–3
–0.75
–4
–1.00
–1000
–750
0
–500 –250
250
500
OP AMP OFFSET VOLTAGE – V
750
–5
–1500
1000
TPC 6. AD5544 Differential Nonlinearity Error vs.
Op Amp Offset
–1000
0
–500
500
OP AMP OFFSET VOLTAGE – V
1000
1500
TPC 9. AD5554 Gain Error vs. Op Amp Offset
0.3
30
VDD = 5V
VREF = 10V
TA = 25C
SS = 120 UNITS
VDD = 5V
VREF = 10V
TA = –40C TO +85C
2000H
3000H
0.1
20
FREQUENCY
DIFFERENTIAL NONLINEARITY ERROR – LSB
1500
VDD = 5V
VREF = 10V
TA = 25C
3
8000H
0.25
0.0
0FFFH
–0.1
10
ACCURACY DEGRADATION
DUE TO EXTERNAL OP AMP
INPUT OFFSET VOLTAGE
SPECIFICATION.
–0.2
–0.3
–1500
1000
4
VDD = 5V
VREF = 10V
TA = 25C
0.50
0.2
0
–500
500
OP AMP OFFSET VOLTAGE – V
TPC 8. AD5544 Gain Error vs. Op Amp Offset
1.00
0.75
–1000
–1000
0
–500
500
1000
OP AMP OFFSET VOLTAGE – V
0
1500
0
0.5
1.0
FULL-SCALE TEMPCO – ppm/C
1.5
TPC 10. AD5544 Full-Scale Tempco (ppm/C)
TPC 7. AD5554 Differential Nonlinearity Error vs.
Op Amp Offset
–10–
REV. 0
AD5544/AD5554
60
SS = 180 UNITS
VDD = 5V
VREF = 10V
TA = –40C TO +85C
FREQUENCY
40
VDD = 5V
VREF = 10V
TA = 25C
AV = –343
1LSB = 52mV
30
VOUT
(10V/DIV)
VOUT
(50mV/DIV)
20
10
1s/DIV
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
FULL-SCALE ERROR TEMPCO – ppm/C
1.8
TPC 11. AD5554 Full-Scale Tempco (ppm/C)
TPC 14. AD5544 Small Signal Settling Time
10000
7FFFH ➔ 8000H
VDD = 5V
VREF = 10V
TA = 25C
VDD = 5V
VREF = 10V
TA = 25C
CS
(5V/DIV)
5555H
FFFFH
8000H
IDD – A
1000
VOUT
(50mV/DIV)
0000H
100
100ns/DIV
10
1k
TPC 12. AD5544 Midscale Transition
10k
100k
1M
CLOCK FREQUENCY – Hz
10M
100M
TPC 15. AD5544 Power Supply Current vs.
Clock Frequency
10000
0000H ➔ FFFFH
VDD = 5V
VREF = 10V
TA = 25C
VDD = 5V
VREF = 10V
TA = 25C
CS
(5V/DIV)
1555H
3FFFH
2000H
IDD – A
1000
VOUT
(5V/DIV)
0000H
100
2s/DIV
10
1k
100k
1M
CLOCK FREQUENCY – Hz
10M
100M
TPC 16. AD5554 Power Supply Current vs.
Clock Frequency
TPC 13. AD5544 Large Signal Settling Time
REV. 0
10k
–11–
AD5544/AD5554
100
90
600
VDD = 5V 10%
TA = 25C
VDD = 5V
VREF = 10V
TA = 25C
500
80
IDD – A
PSRR – dB
400
70
60
50
300
200
40
100
30
0
20
100
1k
10k
100k
CLOCK FREQUENCY – Hz
1M
0
TPC 17. AD5544/AD5554 Power Supply Rejection
vs. Frequency
1
2
3
LOGIC INPUT VOLTAGE – Volts
4
5
TPC 19. AD5544/AD5554 Power Supply Current
vs. Logic Input Voltage
55
54
SUPPLY CURRENT – A
53
VDD = 5V
VREF = 10V
LOGIC = VDD
52
51
50
49
48
47
46
–50
–25
0
25
50
75
TEMPERATURE – C
100
125
150
TPC 18. AD5544/AD5554 Power Supply Current
vs. Temperature
CIRCUIT OPERATION
The AD5544 and AD5554 contain four, 16-bit and 14-bit,
current-output, digital-to-analog converters respectively. Each
DAC has its own independent multiplying reference input. Both
AD5544/AD5554 use 3-wire SPI compatible serial data interface, with a configurable asynchronous RS pin for half-scale
(MSB = 1) or zero-scale (MSB = 0) preset. In addition, an
LDAC strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.
with both negative or positive reference voltages. The VDD power
pin is only used by the logic to drive the DAC switches ON and
OFF. Note that a matching switch is used in series with the
internal 5 kΩ feedback resistor. If users are attempting to measure the value of RFB, power must be applied to VDD in order to
achieve continuity. An additional VSS bias pin is used to guard
the substrate during high temperature applications to minimize
zero-scale leakage currents that double every 10°C. The DAC
output voltage is determined by VREF and the digital data (D) as:
D/A Converter Section
Each part contains four current-steering R-2R ladder DACs.
Figure 4 shows a typical equivalent DAC. Each DAC contains
a matching feedback resistor for use with an external I-to-V
converter amplifier. The RFBX pin is connected to the output of
the external amplifier. The IOUTX terminal is connected to the
inverting input of the external amplifier. The AGNDX pin should
be Kelvin-connected to the load point in the circuit requiring
the full 16-bit accuracy. These DACs are designed to operate
VOUT = −VREF ×
VOUT = −VREF ×
D
65536
D
16384
(For AD5544)
(Equation 1)
(For AD5554)
(Equation 2)
Note that the output polarity is opposite to the VREF polarity for
dc reference voltages.
–12–
REV. 0
AD5544/AD5554
FFFFH
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
ZS
VDD
VREFX
2R
R
2R
R
RFBX
2R
R
5k
S2
S1
GAIN – 12dB/DIV
R
IOUTX
AGNDF
AGNDX
FROM OTHER DACS AGND
VSS
DGND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED.
VDD = 5V
VREF = 100mV rms
TA = 25C
Figure 4. Typical Equivalent DAC Channel
100
These DACs are also designed to accommodate ac reference
input signals. Both AD5544/AD5554 will accommodate input
reference voltages in the range of –12 V to +12 V. The reference
voltage inputs exhibit a constant nominal input resistance of
5 kΩ, ± 30%. On the other hand, the DAC outputs IOUTA, B,
C, D are code-dependent and produce various output resistances and capacitances. The choice of external amplifier
should take into account the variation in impedance generated
by the AD5544/AD5554 on the amplifiers’ inverting input
node. The feedback resistance, in parallel with the DAC ladder
resistance, dominates output voltage noise. For multiplying
mode applications, an external feedback compensation capacitor
(CFB) may be needed to provide a critically damped output
response for step changes in reference input voltages. Figures 5
and 6 show the gain vs. frequency performance at various
attenuation settings using a 23 pF external feedback capacitor
connected across the IOUTX and RFBX terminals for AD5544
and AD5554 respectively. In order to maintain good analog
performance, power supply bypassing of 0.01 µF, in parallel
with 1 µF, is recommended. Under these conditions, clean
power supply with low ripple voltage capability should be used.
Switching power supplies is usually not suitable for this application
due to the higher ripple voltage and PSS frequency-dependent
characteristics. It is best to derive the AD5544/AD5554’s 5 V
supply from the systems’ analog supply voltages. (Do not use
the digital 5 V supply.) See Figure 7.
10k
100k
FREQUENCY – Hz
1k
1M
Figure 5. AD5554 Reference Multiplying Bandwidth
vs. Code
GAIN – 12dB/DIV
3FFFH
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
VDD = 5V
VREF = 100mV rms
TA = 25C
CF = 23pF
ZS
100
10k
100k
FREQUENCY – Hz
1k
2R
5V
+
ANALOG
POWER
SUPPLY
R
VDD
AD5544
R
2R
R
2R
RFBX
R
2R
R
5k
15V
S2
S1
VCC
IOUTX
AGNDF
AGNDX
VOUT
A1
+
VEE
FROM OTHER DACS AGND
DGND
VSS
DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
VDD MUST BE POWERED.
Figure 7. Recommended Kelvin-Sensed Hookup
REV. 0
1M
10M
Figure 6. AD5554 Reference Multiplying Bandwidth
vs. Code
15V
VREFX
10M
–13–
LOAD
AD5544/AD5554
VREF A B C D
CS
EN
AD5544
VDD
CLK
SDI
SDO
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
RFBA
16
INPUT
REGISTER R
DAC A
REGISTER R
DAC A
IOUTA
AGNDA
RFBB
INPUT
REGISTER R
DAC B
REGISTER R
DAC B
IOUTB
AGNDB
DAC A
B
C
D
2:4
DECODE
RFBC
INPUT
REGISTER R
DAC C
REGISTER R
DAC C
IOUTC
AGNDC
RFBD
INPUT
REGISTER R
DAC D
REGISTER R
SET
MSB
SET
MSB
DAC D
IOUTD
AGNDD
AGNDF
POWERON
RESET
DGND
LDAC
MSB
RS
VSS
Figure 8. System Level Digital Interfacing
SERIAL DATA INTERFACE
The AD5544/AD5554 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. Serial data of AD5544 and AD5554
is clocked into the serial input register in an 18-bit and 16-bit
data-word format respectively. MSB bits are loaded first. Table
II defines the 18 data-word bits for AD5544. Table III defines
the 16 data-word bits for AD5554. Data is placed on the SDI
pin, and clocked into the register on the positive clock edge of
CLK subject to the data setup and data hold time requirements
specified in the Interface Timing Specifications. Data can only
be clocked in while the CS chip select pin is active low. For
AD5544, only the last 18 bits clocked into the serial register will
be interrogated when the CS pin returns to the logic high state,
extra data bits are ignored. For AD5554, only the last 16 bits
clocked into the serial register will be interrogated when the CS
pin returns to the logic high state. Since most microcontrollers
output serial data in 8-bit bytes, three right-justified data bytes
can be written to the AD5544. Keeping the CS line low between
the first, second, and third byte transfers will result in a successful serial register update. Similarly, two right-justified data bytes
can be written to the AD5554. Keeping the CS line low between
the first and second byte transfer will result in a successful serial
register update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target
DAC register, determined by the decoding of address bits A1
and A0. For AD5544, Tables I, III, V, and Figure 2 define the
characteristics of the software serial interface. For AD5554,
Tables II, IV, V, and Figure 3 define the characteristics of the
software serial interface. Figures 8 and 9 show the equivalent
logic interface for the key digital control pins for AD5544.
AD5554 has similar configuration, except with 14 data bits.
Two additional pins RS and MSB provide hardware control
over the preset function and DAC Register loading. If these
functions are not needed, the RS pin can be tied to logic high.
The asynchronous input RS pin forces all input and DAC registers to either the zero-code state (MSB = 0), or the half-scale
state (MSB = 1)
–14–
REV. 0
AD5544/AD5554
APPLICATIONS
TO INPUT REGISTER
ADDRESS
DECODER
CS
A
B
C
D
The AD5544/AD5554 are inherently 2-quadrant multiplying
D/A converters. That is, they can be easily set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference-input voltage.
EN
SHIFT REGISTER
CLK
SDI
19TH/17TH
CLOCK
SDO
Figure 9. AD5544/AD5554 Equivalent Logic Interface
POWER-ON RESET
When the VDD power supply is turned ON, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state or half-scale, depending on the MSB pin voltage. The VDD
power supply should have a smooth positive ramp without
drooping in order to have consistent results, especially in the
region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect on
the power-ON reset performance. The DAC register data will
stay at zero or half-scale setting until a valid serial register data
load takes place.
In some applications it may be necessary to generate the full 4quadrant multiplying capability or a bipolar output swing. This
is easily accomplished using an additional external amplifier
(A2) configured as a summing amplifier (see Figure 11). In this
circuit the first and second amplifiers (A1 and A2) provide a
total gain-of-2 which increases the output voltage span to 20 V.
Biasing the external amplifier with a 10 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The
transfer equation of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = –10 V) to midscale (VOUT
= 0 V) to full-scale (VOUT = 10 V).
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zeners
connected to ground (DGND) and VDD as shown in Figure 9.

 D
VOUT = 
− 1 × VREF (For AD5544)
 32768 
(Equation 3)

 D
VOUT = 
− 1 × VREF (For AD5554)
 8192 
(Equation 4)
10k
10k
VDD
10V
5k
VREF
DIGITAL
INPUTS
5k
A2
VOUT
AD588
–10V < VOUT < +10V
VDD
VREFX
DGND
ONE CHANNEL
AD5544
Figure 10. Equivalent ESD Protection Circuits
VSS
AGNDF
RFBX
IOUTX
A1
AGNDX
PCB LAYOUT
In PCB layout, all analog ground, AGNDX, should be tied together.
Amplifiers suitable for I-to-V conversion include:
• High Accuracy: OP97, OP297
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
Figure 11. Four-Quadrant Multiplying Application Circuit
• Speed and Accuracy: OP42
• ± 5 V Applications: OP162/OP262/OP462, OP184/OP284/
OP484
REV. 0
–15–
AD5544/AD5554
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3563–8–4/00 (rev. 0) 00943
28-Lead SSOP
(RS-28)
0.407 (10.34)
0.397 (10.08)
15
1
14
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
28
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
0.07 (1.79)
0.066 (1.67)
8°
0.015 (0.38)
0°
SEATING 0.009 (0.229)
0.010 (0.25)
PLANE
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
PRINTED IN U.S.A.
0.078 (1.98) PIN 1
0.068 (1.73)
–16–
REV. 0