8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter (ADC) AD9286 FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 49.3 dBFS at 200 MHz input at 500 MSPS SFDR: 65 dBc at 200 MHz input at 500 MSPS Low power: 315 mW at 500 MSPS On-chip interleaved clocking On-chip reference and track-and-hold 1.2 V p-p analog input range for each channel Differential input with 500 MHz bandwidth LVDS-compliant digital output On-chip voltage reference and sample-and-hold circuit DNL: ±0.2 LSB Serial port control options Interleaved clock timing adjustment Offset binary, Gray code, or twos complement data format Optional clock duty cycle stabilizer Built-in selectable digital test pattern generation Pin-programmable power-down function Available in 48-lead LFCSP The AD9286 is an 8-bit, monolithic sampling, analog-to-digital converter (ADC) that supports interleaved operation and is optimized for low cost, low power, and ease of use. Each ADC operates at up to a 500 MSPS conversion rate with outstanding dynamic performance. The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. By using the SPI, the user can accurately adjust the timing of the sampling edge per ADC to minimize the image spur energy. The ADC requires a single 1.8 V supply and an encode clock for full performance operation. No external reference components are required for many applications. The digital outputs are LVDS compatible. The AD9286 is available in a Pb-free, 48-lead LFCSP that is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS APPLICATIONS 1. 2. 3. Battery-powered instruments Handheld scope meters Low cost digital oscilloscopes OTS: video over fiber Integrated 8-Bit, 500 MSPS ADC. Single 1.8 V Supply Operation with LVDS Outputs. Power-Down Option Controlled via a Pin-Programmable Setting. FUNCTIONAL BLOCK DIAGRAM SDIO/ PWDN CSB SCLK CLK+ OE SPI CLK– VIN1+ VIN2– VIN2+ ×1.5 CLOCK MANAGEMENT DCO GENERATION ADC AUXCLK– D7+ (MSB), D7– (MSB) D0+ (LSB), D0– (LSB) DCO+ DCO– AD9286 AUXCLK+ RBIAS AUXCLKEN AGND AVDD DRVDD DRGND 09338-001 1.0V VREF REF SELECT LVDS OUTPUT BUFFER VCM VREF OUTPUT INTERLEAVE ADC VIN1– Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 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AD9286 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 15 Applications....................................................................................... 1 RBIAS........................................................................................... 15 General Description ......................................................................... 1 Clock Input Considerations...................................................... 16 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 18 Functional Block Diagram .............................................................. 1 Built-In Self-Test (BIST) and Output Test .................................. 19 Revision History ............................................................................... 2 Built-In Self-Test (BIST)............................................................ 19 Specifications..................................................................................... 3 Output Test Modes..................................................................... 19 DC Specifications ......................................................................... 3 Serial Port Interface (SPI).............................................................. 20 AC Specifications.......................................................................... 4 Configuration Using the SPI..................................................... 20 Digital Specifications ................................................................... 5 Hardware Interface..................................................................... 21 Switching Specifications .............................................................. 6 Configuration Without the SPI ................................................ 21 SPI Timing Specifications ........................................................... 6 SPI Accessible Features.............................................................. 21 Absolute Maximum Ratings............................................................ 9 Memory Map .................................................................................. 22 Thermal Resistance ...................................................................... 9 Reading the Memory Map Register Table............................... 22 ESD Caution.................................................................................. 9 Memory Map Register Table..................................................... 23 Pin Configuration and Function Descriptions........................... 10 Memory Map Register Descriptions........................................ 25 Typical Performance Characteristics ........................................... 12 Applications Information .............................................................. 26 Equivalent Circuits ......................................................................... 14 Design Guidelines ...................................................................... 26 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 27 ADC Architecture ...................................................................... 15 Ordering Guide .......................................................................... 27 Analog Input Considerations.................................................... 15 REVISION HISTORY 1/11—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9286 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, unless otherwise noted. Table 1. Parameter 1 RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTICS Offset Error 2 Gain Error TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUT Input Span Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) Full Power Bandwidth VOLTAGE REFERENCE Internal Reference Input Resistance POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD IDRVDD POWER CONSUMPTION Sine Wave Input 3 Power-Down Power Temperature Full Min 8 Typ Max Unit Bits ±0.4 ±0.3 LSB LSB ±2.1 ±2.8 % FS % FS ±2.1 ±0.2 % FS % FS Full Full Full Full Full 0 0 ±0.2 ±0.1 Guaranteed ±0.4 ±2 Full Full 0 0 ±0.4 ±0.05 Full Full ±2 ±20 ppm/°C ppm/°C Full Full Full Full Full 1.2 1.4 16 250 700 V p-p V kΩ fF MHz Full Full 0.97 1 3 1.03 V kΩ Full Full 1.7 1.7 1.8 1.8 1.9 1.9 V V Full Full 125 51 130 54 mA mA Full Full 315 0.3 330 1.7 mW mW 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. See the Interleave Performance section. 3 Measured with a low frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Rev. 0 | Page 3 of 28 AD9286 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, VIN = −1.0 dBFS differential input, optimum timing value set, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) 1 fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz WORST OTHER HARMONIC OR SPUR fIN = 10.3 MHz fIN = 70 MHz fIN = 96.6 MHz fIN = 220 MHz CROSSTALK 1 Temperature 25°C 25°C Full 25°C Min Typ Max Unit 49.3 49.3 49.3 49.3 dBFS dBFS dBFS dBFS 49.2 49.2 49.2 49.2 dBFS dBFS dBFS dBFS 7.9 7.9 7.9 7.9 Bits Bits Bits Bits 25°C 25°C Full 25°C −70 −70 −69 −65 dBc dBc dBc dBc 25°C 25°C Full 25°C 70 70 68 65 dBc dBc dBc dBc −71 −71 −71 −67 −80 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C 25°C Full 25°C 48.8 48.7 7.8 61 25°C 25°C Full 25°C Full Excludes offset and alias spur (see the Interleave Performance section). Rev. 0 | Page 4 of 28 −61 −64 AD9286 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, AIN = 5 MHz, full temperature, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−, AUXCLK+, AUXCLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage 2 Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance (Differential) Input Capacitance LOGIC INPUTS CSB High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance SCLK, SDIO/PWDN, AUXCLKEN, OE High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS (D7+, D7− to D0+, D0−), LVDS DRVDD = 1.8 V Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 Temperature Full Full Full Full Full Full Full 25°C 25°C Min Typ Max LVDS/PECL 1.2 0.2 AVDD − 0.3 1.2 0 −10 −10 6 AVDD + 1.6 3.6 0.8 +10 +10 20 4 Full Full Full Full 25°C 25°C 1.2 0 −5 −80 Full Full Full Full 25°C 25°C 1.2 0 50 −5 Full Full 290 1.15 −0.4 −63 57 V V μA μA kΩ pF DRVDD + 0.3 0.8 70 +5 V V μA μA kΩ pF 400 1.35 mV V 30 2 345 1.25 Offset binary V V p-p V V V μA μA kΩ pF DRVDD + 0.3 0.8 +5 −50 30 2 −0.4 Unit See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. Specified for LVDS and LVPECL only. Rev. 0 | Page 5 of 28 AD9286 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate CLK Period (tCLK) CLK Pulse Width High (tCH) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)1 DCO Propagation Delay (tDCO) DCO to Data Skew (tSKEW) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time 1 OUT-OF-RANGE RECOVERY TIME 1 Temperature Min Full Full Full 60 4 Full Full Full Full Full Full Full Typ −280 Max Unit 500 2 MHz ns ns 3.7 3.7 −60 11 1.0 0.1 500 4 ns ns ps Cycles ns ps rms μs Cycles 100 Wake-up time is dependent on the value of the decoupling capacitors. SPI TIMING SPECIFICATIONS Table 5. Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Min Typ Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Timing Diagrams M–1 M+4 M VIN1+, VIN1– tA N–2 M+1 N tCH N+4 N+3 N+2 N+1 tA CLK– M+2 N–1 VIN2+, VIN2– CLK+ M+5 M+3 tCLK tDCO DCO+, DCO– M – 11 N – 11 M – 10 N – 10 M – 9 N–9 M–8 N–8 tPD Figure 2. Output Timing Diagram, Sample Mode = Interleaved (Default) Rev. 0 | Page 6 of 28 M–7 09338-002 tSKEW DATA Max Unit AD9286 M–1 M+4 M+5 M VIN1+, VIN1– M+3 N–1 tA N+4 M+1 N+5 M+2 N N+3 VIN2+, VIN2– N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCO+, DCO– tSKEW N – 11 M – 10 N – 10 M–9 N–9 M–8 N–8 M–7 N–7 09338-005 DATA tPD Figure 3. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 0 M–1 M+4 M+5 M VIN1+, VIN1– M+3 N–1 tA N+4 M+1 N+5 M+2 N N+3 VIN2+, VIN2– N+1 CLK+ tCH N+2 tCLK CLK– AUXCLK+ AUXCLK– tDCO DCO+, DCO– DATA M – 11 N – 11 M – 10 N – 10 M–9 N–9 M–8 N–8 M–7 tPD Figure 4. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK in Phase Rev. 0 | Page 7 of 28 09338-006 tSKEW AD9286 M–1 M+4 M+5 M VIN1+, VIN1– M+3 tA M+1 N–1 N–2 VIN2+, VIN2– N tCH N+4 N+3 N+2 N+1 tA CLK+ M+2 tCLK CLK– AUXCLK– AUXCLK+ tDCO DCO+, DCO– M – 11 DATA N – 11 M – 10 N – 10 M–9 N–9 M–8 N–8 M–7 tPD Figure 5. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK Out of Phase Rev. 0 | Page 8 of 28 09338-007 tSKEW AD9286 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0− through D7+/D7− to DRGND DCO+, DCO− to DRGND CLK+, CLK− to AGND AUXCLK+, AUXCLK− to AGND VIN1±, VIN2± to AGND SDIO/PWDN to DRGND CSB to AGND SCLK to AGND Environmental Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.0 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 48-Lead LFCSP (CP-48-12) ESD CAUTION −65°C to +125°C −40°C to +85°C 300°C 150°C Rev. 0 | Page 9 of 28 θJA 30.4 θJC 2.9 Unit °C/W AD9286 48 47 46 45 44 43 42 41 40 39 38 37 AVDD VIN2– VIN2+ AVDD AVDD VREF AVDD VCM AVDD VIN1+ VIN1– AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD AVDD 1 2 PIN 1 INDICATOR AUXCLK+ 3 AUXCLK– 4 RBIAS 5 AUXCLKEN 6 DRGND 7 DRVDD 8 D0– (LSB) 9 D0+ (LSB) 10 D1– 11 D1+ 12 AD9286 AVDD AVDD CLK+ CLK– CSB SDIO/PWDN SCLK OE DRGND DRVDD D7+ (MSB) D7– (MSB) NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 09338-003 D2– D2+ D3– D3+ DCO– DCO+ D4– D4+ D5– D5+ D6– D6+ 13 14 15 16 17 18 19 20 21 22 23 24 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 Figure 6. Pin Configuration Table 8. Pin Function Descriptions Pin No. ADC Power Pins 1, 2, 35, 36, 37, 40, 42, 44, 45, 48 8, 27 7, 28 0 ADC Analog Pins 39 38 46 47 43 5 41 34 33 3 4 Digital Inputs 6 29 Digital Outputs 26 25 24 23 Mnemonic Type Description AVDD Supply Analog Power Supply (1.8 V Nominal). DRVDD DRGND AGND Supply Ground Ground Digital Output Driver Supply (1.8 V Nominal). Digital Output Ground. Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package. This is the only ground connection, and it must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. VIN1+ VIN1− VIN2+ VIN2− VREF RBIAS VCM CLK+ CLK− AUXCLK+ AUXCLK− Input Input Input Input Input/output Input/output Output Input Input Input Input Differential Analog Input Pin (+) for Channel 1. Differential Analog Input Pin (−) for Channel 1. Differential Analog Input Pin (+) for Channel 2. Differential Analog Input Pin (−) for Channel 2. Voltage Reference Input/Output. External Reference Bias Resistor. Connect 10 kΩ from RBIAS to AGND. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Auxiliary ADC Clock Input—True. Auxiliary ADC Clock Input—Complement. AUXCLKEN OE Input Input Auxiliary Clock Input Enable. Digital Enable (Active Low) to Tristate Output Data Pins. D7+ (MSB) D7− (MSB) D6+ D6− Output Output Output Output Output Data 7—True. Output Data 7—Complement. Output Data 6—True. Output Data 6—Complement. Rev. 0 | Page 10 of 28 AD9286 Pin No. 22 21 20 19 16 15 14 13 12 11 10 9 18 17 SPI Control Pins 30 31 32 Mnemonic D5+ D5− D4+ D4− D3+ D3− D2+ D2− D1+ D1− D0+ (LSB) D0− (LSB) DCO+ DCO− Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Description Output Data 5—True. Output Data 5—Complement. Output Data 4—True. Output Data 4—Complement. Output Data 3—True. Output Data 3—Complement. Output Data 2—True. Output Data 2—Complement. Output Data 1—True. Output Data 1—Complement. Output Data 0—True. Output Data 0—Complement. Data Clock Output—True. Data Clock Output—Complement. SCLK SDIO/PWDN CSB Input Input/output Input SPI Serial Clock. SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). SPI Chip Select (Active Low). Rev. 0 | Page 11 of 28 AD9286 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 500 MSPS, DCS enable, 1.2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, TA = 25°C, unless otherwise noted. 0 –40 SECOND HARMONIC –60 500MSPS 96.6MHz @ –1dBFS SNR = 48.2dB (49.2dBFS) ENOB = 7.7 SFDR = 68.4dBc –20 AMPLITUDE (dBFS) –20 THIRD HARMONIC –80 THIRD HARMONIC SECOND HARMONIC –60 –80 –100 0 50 100 150 200 250 FREQUENCY (MHz) –120 09338-107 –120 0 150 0 500MSPS 220.3MHz @ –1dBFS SNR = 48.2dB (49.2dBFS) –20 ENOB = 7.7 SFDR = 66.4dBc 250 500MSPS 29.1MHz @ –7dBFS 32.1MHz @ –7dBFS SFDR = 70.3dBc (77.3dBFS) AMPLITUDE (dBFS) –20 –40 SECOND HARMONIC 200 Figure 10. Single-Tone FFT with fIN = 96.6 MHz 0 AMPLITUDE (dBFS) 100 FREQUENCY (MHz) Figure 7. Single-Tone FFT with fIN = 4.3 MHz –60 50 09338-110 –100 –40 THIRD HARMONIC –80 –100 –40 –60 –80 –100 0 50 100 150 200 250 FREQUENCY (MHz) –120 09338-108 –120 0 50 100 150 200 250 FREQUENCY (MHz) Figure 8. Single-Tone FFT with fIN = 220.3 MHz 09338-111 AMPLITUDE (dBFS) 0 500MSPS 4.3MHz @ –1dBFS SNR = 48.4dB (49.4dBFS) ENOB = 7.7 SFDR = 70.0dBc Figure 11. Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz 100 80 IMD3 (dBFS) 90 70 SFDR (dBFS) 80 REFERENCE LINE SFDR/IMD3 (dB) 40 70 SNR (dBFS) 50 SFDR (dBc) 30 SNR (dBc) 60 SFDR (dBFS) IMD3 (dBc) 50 SFDR (dBc) 40 30 20 20 10 –40 –35 –30 –25 –20 –15 –10 –5 0 AIN POWER (dBFS) Figure 9. SFDR/SNR vs. Input Amplitude (AIN) with fIN = 2.2 MHz 0 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 AIN POWER (dBFS) Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz Rev. 0 | Page 12 of 28 09338-112 0 –45 10 09338-109 SFDR/SNR (dB) 60 AD9286 100 75 95 SFDR +25°C SFDR –40°C SFDR +85°C 65 60 55 SNRFS –40°C SNRFS +25°C SNRFS +85°C 50 +85°C 90 ALIAS SPUR (dBFS) SNRFS/SFDR (dBFS/dBc) 70 85 80 75 +25°C 70 65 –40°C 60 0 50 100 150 200 250 300 350 400 450 500 INPUT FREQUENCY (MHz) 50 –3 09338-113 45 3 0.10 0.075 0.15 0.050 0.10 I_DVDD INL ERROR (LSB) 0.20 I_AVDD TOTAL POWER (W) 0.25 0.100 2 0.30 0.125 0.05 0 –0.05 –0.10 0.025 200 250 300 350 400 –0.15 0 500 450 09338-114 150 ENCODE FREQUENCY (MHz) Figure 14. Supply Current and Power vs. Encode 0.10 0.05 0 –0.05 –0.15 64 96 128 160 192 OUTPUT CODE 224 256 09338-115 –0.10 32 32 64 96 128 160 192 OUTPUT CODE Figure 17. INL Error with fIN = 4.3 MHz 0.15 0 0 Figure 15. DNL Error with fIN = 4.3 MHz Rev. 0 | Page 13 of 28 224 256 09338-118 0.05 0 100 DNL ERROR (LSB) SUPPLY CURRENT (A) 0.150 1 0.15 0.35 TOTAL POWER 0 Figure 16. Alias Spur vs. Coarse Timing Adjustment and Temperature 0.40 0.175 –1 COARSE TIMING ADJUSTMENT (Bits) Figure 13. SNRFS/SFDR vs. Input Frequency (fIN) and Temperature 0.200 –2 09338-116 55 AD9286 EQUIVALENT CIRCUITS DRVDD AVDD AVDD 1.2V 10kΩ 10kΩ CLK– 350Ω SCLK, OE, AUXCLKEN 30kΩ 09338-019 CLK+ DRVDD 09338-022 AVDD Figure 18. Clock Inputs Figure 21. SCLK, OE, AUXCLKEN AVDD BUF AVDD DRVDD 350Ω 8kΩ AVDD BUF VCML ~1.4V 30kΩ 8kΩ SDIO 09338-020 BUF VIN– CTRL Figure 19. Analog Inputs (VCML = ~1.4 V) Figure 22. SDIO DRVDD DRVDD DRVDD 350Ω V+ DRVDD D7– TO D0– V– V– D7+ TO D0+ V+ 09338-024 09338-021 CSB 30kΩ Figure 20. CSB Figure 23. LVDS Output Driver Rev. 0 | Page 14 of 28 09338-023 VIN+ AD9286 THEORY OF OPERATION The AD9286 is a pipeline-type converter. The input buffers are differential, and both sets of inputs are internally biased. This allows the use of ac or dc input modes. A sample-and-hold amplifier is incorporated into the first stage of the multistage pipeline converter core. The output staging block aligns the data, carries out error correction for the pipeline stages, and feeds that data to the output interleave block and, finally, to the output buffers. All user-selected options are programmed through dedicated digital input pins or a serial port interface (SPI). Differential Input Configurations ADC ARCHITECTURE 1.2V p-p Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. 200Ω ANALOG INPUT CONSIDERATIONS The analog inputs of the AD9286 are differentially buffered. For best dynamic performance, the source impedances driving VIN1+, VIN1−, VIN2+, and VIN2− should be matched such that common-mode settling errors are symmetrical. Because the AD9286 interleaves two ADC cores, special attention should be given, during board layout, to the symmetry of the two analog paths. Mismatch introduces undesired distortion. The analog inputs are optimized to provide superior wideband performance and must be driven differentially. SNR and SINAD performance degrades significantly if the analog inputs are driven with a single-ended signal. A wideband transformer, such as Mini-Circuits® ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.4 V. 33Ω – + – 4.7pF ADA4937-1 227.4Ω 0.1µF + VIN1 AD9286 33Ω + 200Ω – VIN2 VCM Figure 24. Differential Input Configuration Using the ADA4937-1 The AD9286 can also be driven passively with a differential transformer-coupled input (see Figure 25). To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. 33Ω 1.2V p-p The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended mode. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. The outputs from both interleaving channels are time interleaved to achieve an effective 500 MSPS. 200Ω 09338-025 61.9Ω + – 49.9Ω 4.7pF 33Ω VIN1 AD9286 + – VIN2 VCM 0.1µF 09338-026 Each interleaving channel of the AD9286 consists of a differential input buffer followed by a sample-and-hold amplifier (SHA). This SHA is followed by a pipeline switched-capacitor ADC. The quantized outputs from each stage are combined into a final 8-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, whereas the remaining stages operate on preceding samples. Optimum performance is achieved when driving the AD9286 in a differential input configuration. For baseband applications, the ADA4937-1 differential driver provides excellent performance and a flexible interface to the ADC (see Figure 24). The output common-mode voltage of the AD9286 is easily set to 1.4 V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Figure 25. Differential Transformer-Coupled Configuration The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. VOLTAGE REFERENCE An internal differential voltage reference creates positive and negative reference voltages that define the 1.2 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of SPI control. It can also be driven externally with an off-chip stable reference. See the Memory Map Register Descriptions section for more details. RBIAS The AD9286 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor, which is used to set the master current reference of the ADC core, should have a 1% tolerance. Rev. 0 | Page 15 of 28 AD9286 CLOCK INPUT 0.1µF 0.1µF CLK+ AD951x CLOCK INPUT 50kΩ 0.1µF PECL DRIVER 100Ω 0.1µF ADC CLK– 50kΩ 240Ω 240Ω Clock Input Options The AD9286 has a very flexible clock input structure. The clock input can be an LVDS, LVPECL, or sine wave signal. Each configuration that is described in this section applies to both CLK+ and CLK− and AUXCLK+ and AUXCLK−, when necessary. Figure 26 and Figure 27 show two preferred methods for clocking the AD9286. A low jitter clock source is converted from a singleended signal to a differential signal using either an RF transformer or an RF balun. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9286 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9286, while preserving the fast rise and fall times of the signal that are critical to low jitter performance. 0.1µF 50Ω XFMR 100Ω ADC CLK– 0.1µF SCHOTTKY DIODES: HSM2822 09338-027 0.1µF Figure 26. Transformer-Coupled Differential Clock 1nF CLOCK INPUT CLK+ 50Ω 0.1µF ADC 1nF SCHOTTKY DIODES: HSM2822 09338-028 CLK– 0.1µF CLOCK INPUT 0.1µF 0.1µF CLK+ AD951x CLOCK INPUT 50kΩ 0.1µF LVDS DRIVER 100Ω 0.1µF ADC CLK– 50kΩ Clocking Modes CLK+ 0.1µF A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 29. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. Figure 29. Differential LVDS Sample Clock Mini-Circuits® ADT1-1WT, 1:1 Z CLOCK INPUT Figure 28. Differential PECL Sample Clock 09338-030 For optimum performance, clock the AD9286 sample clock inputs, CLK+ and CLK− (and, optionally, AUXCLK+ and AUXCLK−), with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. 09338-029 CLOCK INPUT CONSIDERATIONS Figure 27. Balun-Coupled Differential Clock If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 28. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. The AD9286 powers up as a single-channel converter with interleaving enabled. In this mode, a single high speed clock, driving CLK+ and CLK−, is divided down into two half-speed clocks running 180° out of phase with each other, each driving their respective ADC core. By strapping the two analog inputs together externally, the AD9286 operates as a single 500 MSPS ADC. Because the high sample rate is achieved by interleaving two ADC cores, mismatch between the cores, board layout, and clock timing can cause unwanted distortion. The AD9286 has been designed with two well-matched ADC cores to minimize mismatch. To aid the user in removing timing errors, the AD9286 provides both fine and coarse timing adjustments, per channel, through SPI. These features are available at Register 0x37 (fine) and Register 0x38 (coarse). The AD9286 supports a mode that allows the user to provide two separate half-speed clocks, bypassing the internal clock timing circuits and permitting external control of the clock timing relationship for each interleave channel. When the sample mode is set to simultaneous (Address 0x09, Bit 3 = 0) and the AUXCLKEN pin is tied to DRVDD, the AD9286 expects a second clock on its auxiliary clock input (AUXCLK+, AUXCLK−). Rev. 0 | Page 16 of 28 AD9286 Interleave Performance The AD9286 achieves 500 MSPS conversion by time interleaving two 250 MSPS ADC channels. Although this technique is sufficient in achieving 8-bit performance, quantifiable errors are introduced. These errors come from three sources: gain mismatch, imperfect out-of-phase sampling, and offset mismatch between the two channels. Distortion appears spectrally in two distinct ways: gain and timing mismatch appear as an alias spur (see Equation 1), and offset mismatch appears as a spur located at the Nyquist rate of the converter (see Equation 2). fALIAS_SPUR = fS/2 − fIN (1) 80 75 70 65 60 55 50 45 0 0.1 0.2 0.3 0.4 0.5 GAIN MISMATCH (% FS) 09338-032 The AD9286 supports the clocking of each internal ADC with separate clocks. By setting AUXCLKEN to DRVDD, the user can supply a differential auxiliary clock to AUXCLK+ and AUXCLK−. In this mode, each internal ADC core has a maximum sample rate of 250 MSPS. This mode bypasses the internal timing adjustment blocks. 85 ALIAS SPUR (dBc) If the user desires to operate the AD9286 as a dual 8-bit, 250 MSPS converter and supply only a single clock, this is achieved by setting sample mode to simultaneous, with the AUXCLKEN pin tied to AGND. In this mode, the two ADC cores sample simultaneously. For a summary of all supported clocking modes, see Table 9. ASGAIN, as a function of gain mismatch, is shown in Figure 30. Figure 30. ASGAIN as a Function of Gain Mismatch The magnitude of the alias spur (AS) contributed by a timing error is shown in Equation 4. ASTIMING (dBc) = 20 × log(ASTIMING) = 20 × log(θEP/2) (4) where θEP = ωA × ΔtE(Radians), with ωA as the analog input frequency and ΔtE as the clock skew error. ASTIMING, as a function of timing error, is shown in Figure 31. 85 80 75 ALIAS SPUR (dBc) In this mode, the AD9286 can also function as a dual 8-bit, 250 MSPS converter. This may be useful in applications where both a single 8-bit, 500 MSPS and a dual 8-bit, 250 MSPS converter are needed. The clock management block requires that CLK± and AUXCLK± be either 0° or 180°, relative to each other. If this requirement is satisfied, the circuit correctly time aligns the data coming out of each ADC core. where: fS is the interleaved sample rate. fIN is the analog input frequency. 70 65 60 55 fOFFSET_SPUR = fS/2 45 (2) 0 2 4 6 8 10 TIMING ERROR (ps) where fS is the interleaved sample rate. The magnitude of the alias spur (AS) contributed by a gain error is shown in Equation 3. ASGAIN (dBc) = 20 × log(ASGAIN) = 20 × log(GE/2) 12 09338-033 50 Figure 31. ASTIMING as a Function of Timing Error The total magnitude of the alias spur (AS) is shown in Equation 5. ASTOTAL (dB) = 20 × log√((ASGAIN)2 + (ASTIMING)2) (3) (5) where: GE = Gain_Error_Ratio = 1 − VFS1/VFS2. VFSn is the full-scale voltage of Core n. Table 9. Supported Clocking Modes Effective Number of Channels One Two Two One Maximum CLK Frequency 500 MSPS 250 MSPS 250 MSPS 250 MSPS AUXCLK Frequency N/A N/A CLK CLK AUXCLK Phase Relative to CLK N/A N/A 0° 180° AUXCLKEN Low Low High High Rev. 0 | Page 17 of 28 SPI Register, Address 0x09, Bit 3 1 0 0 0 Clock Timing Adjust Internal N/A N/A External AD9286 The magnitude of the offset spur (OS) is shown in Equation 6. 60 Due to the orthogonal relationship between the gain and timing errors, it is impossible to correct for one with the other. To minimize channel-to-channel gain error, the AD9286 is designed to have very close gain matching between the two channels. Address 0x37 and Address 0x38 of the SPI provide the ability to add delay to either clock path to realize a minimum clock skew error. Also provided via the SPI, in Address 0x10, is the ability to minimize the channel-to-channel offset error. 55 DIGITAL OUTPUTS 50 Digital Output Enable Function (OE) OSOFFSET (dBFS) = 20 × log(OFFSET × 2/2RESOLUTION) (6) where: OFFSET is the channel-to-channel offset in codes. RESOLUTION is the resolution of the converter (eight bits). The AD9286 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OE pin. When OE is set to logic level high, the output drivers for both data buses are placed into a high impedance state. 45 40 35 30 25 20 0 0.5 1.0 1.5 2.0 OFFSET MISMATCH (% FS) 2.5 09338-034 OFFSET SPUR (dBFS) OSOFFSET, as a function of offset mismatch, is shown in Figure 32. Figure 32. OSOFFSET as a Function of Offset Mismatch Rev. 0 | Page 18 of 28 AD9286 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9286 includes a built-in self-test feature that is designed to enable verification of the integrity of each channel, as well as facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9286 is included. Various output test options are also provided to place predictable values on the outputs of the AD9286. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9286 signal path. Perform the BIST test after a reset to ensure that the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. When the test is completed, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 of Register 0x0E, signifying that the test passed. If the BIST test fails, Bit 0 of Register 0x0E is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs. Writing a value of 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (BIST init) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x0E is automatically cleared. The PN sequence can be continued from its last value by writing a 0 to Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user must rely on verifying the output data. OUTPUT TEST MODES The output test options are described in Table 13 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 19 of 28 AD9286 SERIAL PORT INTERFACE (SPI) The AD9286 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 33. Other modes involving CSB are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. CSB can stall high between bytes to allow for additional external timing. When the CSB pin is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. During the instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits, as shown in Figure 33. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: SCLK, SDIO, and CSB (see Table 10). SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. CSB (chip select bar) is an active low control that enables or disables the read and write cycles. All data is composed of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction, from an input to an output, at the appropriate point in the serial frame. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, the serial data input/output (SDIO) pin changes direction, from an input to an output, at the appropriate point in the serial frame. Table 10. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. A serial shift clock input that is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. tHIGH tDS tS tDH Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tCLK tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 33. Serial Port Interface Timing Diagram Rev. 0 | Page 20 of 28 D4 D3 D2 D1 D0 DON’T CARE 09338-004 SCLK DON’T CARE AD9286 HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI The pins described in Table 10 constitute the physical interface between the programming device of the user and the serial port of the AD9286. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. In applications that do not interface to the SPI control registers, the SDIO/PWDN pin serves as a standalone, CMOS-compatible control pin. When the device is powered up, it is assumed that the user intends to use the SDIO, SCLK, and CSB pins as static control lines for the output enable and power-down feature control. In this mode, connecting the CSB chip select to AVDD disables the serial port interface. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9286 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SDIO/PWDN serves a dual function when the SPI interface is not being used. When the pin is strapped to AVDD or ground during device power-on, it is associated with a specific function. The mode selection table (see Table 11) describes the strappable functions that are supported on the AD9286. Table 11. Mode Selection Pin SDIO/PWDN OE External Voltage AVDD (default) AGND AVDD AGND (default) Configuration Chip in full power-down Normal operation Outputs in high impedance Outputs enabled SPI ACCESSIBLE FEATURES Table 12 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9286 part-specific features are described in detail in Table 13. Table 12. Features Accessible Using the SPI Feature Mode Clock Offset Test I/O Output Mode Output Phase Output Delay Voltage Reference Rev. 0 | Page 21 of 28 Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the voltage reference AD9286 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Logic Levels Each row in the memory map register table (see Table 13) has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02), the device index and transfer registers (Address 0x05 and Address 0xFF), and the program registers (Address 0x08 to Address 0x38). An explanation of logic level terminology follows: Table 13 documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0xFF. • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Bit is cleared” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x08 to Address 0x38 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. Setting the transfer bit allows these registers to be updated internally and simultaneously. The internal update takes place when the transfer bit is set, and then the bit autoclears. Open Locations Channel-Specific Registers All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open. If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in the memory map register table as local. These local registers and bits can be accessed by setting the appropriate Channel 1 (Bit 0) or Channel 2 (Bit 1) bits in Register 0x05. Default Values If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel 1 or Channel 2 to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel 1. Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. After the AD9286 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 13). Rev. 0 | Page 22 of 28 AD9286 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers Addr Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 0 SPI port configuration 0x01 Chip ID (global) 0x02 Chip grade (global) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) LSB first Soft reset 1 1 Soft reset LSB first 0 8-bit chip ID Open 0xFF Open Open Transfer ADC 2 default Open Program Registers (May or may not be indexed by device index) 0x08 Open Modes (global) 0x09 Clock (global) 0x0D Test mode (local) 0x0E BIST (local) Open Reset PN23 gen Reset PN9 gen Sample mode 0: simultaneous 1: interleaved Open Open Rev. 0 | Page 23 of 28 0x18 Nibbles are mirrored so that LSBfirst or MSBfirst mode registers correctly, regardless of shift mode Unique chip ID used to differentiate devices; read only Unique speed grade ID used to differentiate devices; read only 0x40 ADC 1 default 0xFF Transfer 0xFF Internal power-down mode 00: chip run 01: full power-down 10: reserved 11: reserved Open Default Notes/ Comments 0x0A Speed grade ID 100 = 500 MSPS Device Index and Transfer Registers 0x05 Device Index A Default Value (Hex) Open 0x00 Bits are set to determine which onchip device receives the next write command; default is all devices on the chip Synchronous transfer of data from the master shift register to the slave Determines various generic modes of chip operation Duty cycle stabilizer 0x09 Output test mode 000: off 001: midscale short 010: +FS short 011: −FS short 100: checkerboard output 101: PN23 sequence 110: PN9 sequence 111: one-/zero-word toggle BIST init Open BIST enable 0x00 When test mode is set, test data is placed on the output pins in place of normal data 0x00 BIST mode config Clock boost AD9286 Addr (Hex) 0x0F Register Name ADC input (global/local) 0x10 Offset (local) 0x14 Output mode (local) 0x16 Output phase (global) Voltage reference (global) MISR LSB (local) 0x18 0x24 0x25 MISR MSB (local) 0x37 Timing adjust (local) 0x38 Bit 7 (MSB) Bit 6 Bit 5 Open Bit 4 Open DCO invert Open Default Notes/ Comments 0x00 Device offset trim 0x00 Configures the outputs and the format of the data 0x00 Voltage reference and input full-scale adjustment (see Table 14) 0x00 Selects/ adjusts VREF LSBs of multiple input shift register (MISR) 0x00 MSBs of multiple input shift register (MISR) 0x00 MISR least significant byte; read only MISR most significant byte; read only Determines the clock delay that is introduced into the sampling path Determines the clock delay that is introduced into the sampling path Output enable Bit 2 Analog disconnect (local) Default Value (Hex) 0x00 Bit 1 Commonmode input enable (global) Offset adjust (twos complement format) 0111: +7 0110: +6 … 0001: +1 0000: 0 1111: −1 … 1001: −7 1000: −8 Open Data format select Output invert 00: offset binary 01: twos complement 10: Gray code 11: reserved Open Open Bit 3 Bit 0 (LSB) Open Open Fine timing skew 0000: 0.0 ps 0001: 0.075 ps … 1111: 1.125 ps 0x00 Open Coarse timing skew 0000: 0.0 ps 0001: 1.2 ps … 1111: 18 ps 0x00 Rev. 0 | Page 24 of 28 AD9286 MEMORY MAP REGISTER DESCRIPTIONS For more information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference Bits[4:0] scale the internally generated voltage reference and, consequently, the full scale of the analog input. Within this register, the reference driver can be configured to be more easily driven externally by reducing the capacitive loading. The relationship between the VREF voltage and the input full scale is described by Equation 7. See Table 14 for a complete list of register settings. Input_Full_Scale = VREF × 1.2 (7) Table 14. VREF and Input Full Scale (Register 0x18) VREF (V) Full Scale (V) Value 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 Rev. 0 | Page 25 of 28 0.844 0.857 0.87 0.883 0.896 0.909 0.922 0.935 0.948 0.961 0.974 0.987 1 1.013 1.026 1.039 1.052 1.065 1.078 1.091 1.104 1.117 1.13 1.143 1.156 1.169 1.182 1.195 1.208 1.221 1.234 External 1.013 1.028 1.044 1.060 1.075 1.091 1.106 1.122 1.138 1.153 1.169 1.184 1.200 1.216 1.231 1.247 1.262 1.278 1.294 1.309 1.325 1.340 1.356 1.372 1.387 1.403 1.418 1.434 1.450 1.465 1.481 External × 1.2 AD9286 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9286 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. Power and Ground Recommendations When connecting power to the AD9286, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and DRVDD supply must be used, the AVDD and DRVDD domains must be isolated with a ferrite bead or filter choke and separate decoupling capacitors. Several different decoupling capacitors can be used to cover both high and low frequencies. Locate these capacitors close to the point of entry at the printed circuit board (PCB) level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9286. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Sink Recommendations The exposed paddle (Pin 0) is the only ground connection for the AD9286; therefore, it must be connected to analog ground (AGND) on the customer PCB. To achieve the best electrical and thermal performance, mate an exposed (no solder mask), continuous copper plane on the PCB to the AD9286 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor. RBIAS The AD9286 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor, which sets the master current reference of the ADC core, should have at least a 1% tolerance. Reference Decoupling Decouple the VREF pin externally to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9286 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Rev. 0 | Page 26 of 28 AD9286 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR 25 24 13 12 0.25 MIN 5.50 REF 0.05 MAX 0.02 NOM 0.50 BSC 4.25 4.10 SQ 3.95 (BOTTOM VIEW) 0.80 MAX 0.65 TYP SEATING PLANE PIN 1 INDICATOR 1 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 12° MAX 48 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 042809-A TOP VIEW 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-12) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9286BCPZ-500 AD9286BCPZRL7-500 AD9286-500EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 Package Option CP-48-12 CP-48-12 AD9286 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09338-0-1/11(0) Rev. 0 | Page 28 of 28