Octal, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter AD9252 8 ADCs integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) Excellent linearity DNL = ±0.4 LSB (typical) INL = ±1.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 325 MHz, full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9252 is an octal, 14-bit, 50 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD PDWN AD9252 DRGND 14 VIN+A VIN–A ADC VIN+B VIN–B ADC VIN+C VIN–C ADC VIN+D VIN–D ADC VIN+E VIN–E ADC VIN+F VIN–F ADC VIN+G VIN–G ADC VIN+H VIN–H ADC SERIAL LVDS D+A D–A SERIAL LVDS D+B D–B SERIAL LVDS D+C D–C SERIAL LVDS D+D D–D SERIAL LVDS D+E D–E SERIAL LVDS D+F D–F SERIAL LVDS D+G D–G SERIAL LVDS D+H D–H 14 14 14 14 14 14 14 VREF SENSE FCO+ 0.5V REFT REFB REF SELECT RBIAS SERIAL PORT INTERFACE AGND CSB SDIO/ ODM SCLK/ DTP DATA RATE MULTIPLIER CLK+ CLK– FCO– DCO+ DCO– 06296-001 FEATURES Figure 1. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI®). The AD9252 is available in a Pb-free, 64-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Small Footprint. Eight ADCs are contained in a small, spacesaving package; low power of 93.5 mW/channel at 50 MSPS. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate operation (DDR). User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9212 (10-bit), and AD9222 (12-bit). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD9252 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 17 Applications....................................................................................... 1 Clock Input Considerations...................................................... 19 General Description ......................................................................... 1 Serial Port Interface (SPI).............................................................. 27 Functional Block Diagram .............................................................. 1 Hardware Interface..................................................................... 27 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 29 Revision History ............................................................................... 2 Reading the Memory Map Table.............................................. 29 Specifications..................................................................................... 3 Reserved Locations .................................................................... 29 AC Specifications.......................................................................... 4 Default Values ............................................................................. 29 Digital Specifications ................................................................... 5 Logic Levels................................................................................. 29 Switching Specifications .............................................................. 6 Evaluation Board ............................................................................ 33 Timing Diagrams.............................................................................. 7 Power Supplies............................................................................ 33 Absolute Maximum Ratings............................................................ 9 Input Signals................................................................................ 33 Thermal Impedance ..................................................................... 9 Output Signals ............................................................................ 33 ESD Caution.................................................................................. 9 Default Operation and Jumper Selection Settings................. 34 Pin Configuration and Function Descriptions........................... 10 Alternative Analog Input Drive Configuration...................... 35 Equivalent Circuits ......................................................................... 12 Outline Dimensions ....................................................................... 52 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 52 Theory of Operation ...................................................................... 17 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 52 AD9252 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3 Temperature Min 14 AD9252-50 Typ Max Full Full Full Full Full Full Full Guaranteed ±1 ±3 ±1.5 ±0.3 ±0.4 ±1.5 Full Full Full ±2 ±17 ±21 Full Full Full ±2 3 6 Full Full Full Full 2 AVDD/2 7 325 Full Full Full Full Full Full Full Full Full 1 1.7 1.7 1.8 1.8 360 55.5 748 2 89 −90 −90 ±8 ±8 ±2.5 ±0.7 ±1 ±4 Unit Bits mV mV % FS % FS LSB LSB ppm/°C ppm/°C ppm/°C ±30 mV mV kΩ V p-p V pF MHz 1.9 1.9 373.4 58 773 11 V V mA mA mW mW mW dB dB See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. 2 Rev. 0 | Page 3 of 52 AD9252 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) EFFECTIVE NUMBER OF BITS (ENOB) SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST HARMONIC (Second or Third) WORST OTHER (Excluding Second or Third) TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS 1 fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C AD9252-50 Typ Max 73.2 71 73 72.7 71 72.5 70.2 72.2 72 70.5 11.87 11.5 11.84 11.79 11.5 85 73 84 83 79 −85 −84 −73 −83 −79 −90 −90 −80 −90 −89 80.0 Min 80.0 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 52 Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9252 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM)3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D+, D−), (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D−), (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temperature Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 Full Full 25°C 25°C 1.2 0 AD9252-50 Typ Max Unit CMOS/LVDS/LVPECL mV p-p V kΩ pF 1.2 20 1.5 3.6 0.3 V V kΩ pF 3.6 0.3 V V kΩ pF DRVDD + 0.3 0.3 V V kΩ pF 30 0.5 70 0.5 30 2 Full Full 1.79 0.05 V V LVDS Full Full 247 1.125 Full Full 150 1.10 454 1.375 Offset binary mV V LVDS 250 1.30 Offset binary mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only. This is specified for 13 SDIO pins sharing the same connection. Rev. 0 | Page 5 of 52 AD9252 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. AD9252-50 Parameter 1 CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) Temp Min Full Full Full Full 50 OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 Full Full Full Full Full 1.5 Typ Max 10 10.0 10.0 MSPS MSPS ns ns DCO to Data Delay (tDATA)4 Full (tSAMPLE/28) − 300 2.3 300 300 2.3 tFCO + (tSAMPLE/28) (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO to FCO Delay (tFRAME)4 Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Full ±50 ±200 ps 25°C 25°C Full 600 375 8 ns μs CLK cycles 25°C 25°C 25°C 750 <1 1 ps ps rms CLK cycles APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time 1.5 1 3.1 Unit 3.1 ns ps ps ns ns See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be adjusted via the SPI interface. Measurements were made using a part soldered to FR4 material. 4 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 2 3 Rev. 0 | Page 6 of 52 AD9252 TIMING DIAGRAMS N–1 AIN tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–8 D12 N–8 D11 N–8 D10 N–8 D9 N–8 D8 N–8 D7 N–8 D6 N–8 D5 N–8 D4 N–8 D3 N–8 D2 N–8 D1 N–8 D0 N–8 MSB N–7 D12 N–7 D+ Figure 2. 14-Bit Data Serial Stream (Default) N–1 AIN tA N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–8 D10 N–8 D9 N–8 D8 N–8 D7 N–8 D6 N–8 D5 N–8 D+ Figure 3. 12-Bit Data Serial Stream Rev. 0 | Page 7 of 52 D4 N–8 D3 N–8 D2 N–8 D1 N–8 D0 N–8 MSB N–7 D10 N–7 06296-002 D– 06296-003 D– AD9252 N–1 AIN tA N tEH tEL CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA LSB N–8 D0 N–8 D1 N–8 D2 N–8 D3 N–8 D4 N–8 D5 N–8 D6 N–8 D+ Figure 4. 14-Bit Data Serial Stream, LSB First Rev. 0 | Page 8 of 52 D7 N–8 D8 N–8 D9 N–8 D10 N–8 D11 N–8 D12 N–8 LSB N–7 D0 N–7 06296-004 D– AD9252 ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D+, D−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− VIN+, VIN− SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To Table 6. Rating AGND DRGND DRGND DRVDD DRGND −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.0 V −0.3 V to +2.0 V AGND AGND AGND AGND AGND AGND −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V Air Flow Velocity (m/s) 0.0 1.0 2.5 1 θJA1 17.7°C/W 15.5°C/W 13.9°C/W θJB θJC 8.7°C/W 0.6°C/W θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. ESD CAUTION −40°C to +85°C 150°C 300°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 52 AD9252 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VIN+F VIN–F AVDD VIN–E VIN+E AVDD REFT REFB VREF SENSE RBIAS VIN+D VIN–D AVDD VIN–C VIN+C PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9252 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD VIN+B VIN–B AVDD VIN–A VIN+A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD D+A D–A Figure 5. 64-Lead LFCSP Top View Table 7. Pin Function Descriptions Pin No. 0 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 13, 36 14, 35 2 3 5 6 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic AGND AVDD Description Analog Ground (Exposed Paddle) 1.8 V Analog Supply DRGND DRVDD VIN+G VIN−G VIN−H VIN+H CLK− CLK+ D−H D+H D−G D+G D−F D+F D−E D+E DCO− DCO+ FCO− FCO+ D−D D+D D−C D+C D−B D+B Digital Output Driver Ground 1.8 V Digital Output Driver Supply ADC G Analog Input—True ADC G Analog Input—Complement ADC H Analog Input—Complement ADC H Analog Input—True Input Clock—Complement Input Clock—True ADC H Digital Output—Complement ADC H True Digital Output—True ADC G Digital Output—Complement ADC G True Digital Output—True ADC F Digital Output—Complement ADC F True Digital Output—True ADC E Digital Output—Complement ADC E True Digital Output—True Data Clock Digital Output—Complement Data Clock Digital Output—True Frame Clock Digital Output—Complement Frame Clock Digital Output—True ADC D Digital Output—Complement ADC D True Digital Output—True ADC C Digital Output—Complement ADC C True Digital Output—True ADC B Digital Output—Complement ADC B True Digital Output—True Rev. 0 | Page 10 of 52 06296-005 D–G D+G D–F D+F D–E D+E DCO– DCO+ FCO– FCO+ D–D D+D D–C D+C D–B D+B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD VIN+G VIN–G AVDD VIN–H VIN+H AVDD AVDD CLK– CLK+ AVDD AVDD DRGND DRVDD D–H D+H AD9252 Pin No. 33 34 38 39 40 41 43 44 46 47 49 50 52 53 54 55 56 57 58 60 61 63 64 Mnemonic D−A D+A SCLK/DTP SDIO/ODM CSB PDWN VIN+A VIN−A VIN−B VIN+B VIN+C VIN−C VIN−D VIN+D RBIAS SENSE VREF REFB REFT VIN+E VIN−E VIN−F VIN+F Description ADC A Digital Output—Complement ADC A True Digital Output—True Serial Clock/Digital Test Pattern Serial Data Input-Output/Output Driver Mode Chip Select Bar Power Down ADC A Analog Input—True ADC A Analog Input—Complement ADC B Analog Input—Complement ADC B Analog Input—True ADC C Analog Input—True ADC C Analog Input—Complement ADC D Analog Input—Complement ADC D Analog Input—True External Resistor to Set the Internal ADC Core Bias Current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) ADC E Analog Input—True ADC E Analog Input—Complement ADC F Analog Input—Complement ADC F Analog Input—True Rev. 0 | Page 11 of 52 AD9252 EQUIVALENT CIRCUITS DRVDD V V D– D+ 06296-006 V V DRGND 06296-009 VIN Figure 9. Equivalent Digital Output Circuit Figure 6. Equivalent Analog Input Circuit 10Ω CLK 10kΩ 1.25V 10kΩ SCLK/DTP OR PDWN 10Ω 1kΩ CLK 06296-010 06296-007 30kΩ Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit Figure 7. Equivalent Clock Input Circuit RBIAS 30kΩ 06296-011 350Ω 06296-008 SDIO/ODM 100Ω Figure 11. Equivalent RBIAS Circuit Figure 8. Equivalent SDIO/ODM Input Circuit Rev. 0 | Page 12 of 52 AD9252 AVDD 70kΩ CSB 1kΩ 6kΩ Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit 1kΩ 06296-013 SENSE 06296-014 06296-012 VREF Figure 13. Equivalent SENSE Circuit Rev. 0 | Page 13 of 52 AD9252 TYPICAL PERFORMANCE CHARACTERISTICS 0 AIN = –0.5dBFS SNR = 71.16dB ENOB = 11.53 BITS –20 SFDR = 72.92dBc AMPLITUDE (dBFS) –20 –40 –60 –80 10 15 20 25 –120 5 0 10 15 20 25 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 18. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 50 MSPS 90 0 AIN = –0.5dBFS SNR = 72.98dB ENOB = 11.83 BITS –20 SFDR = 83.8dBc SFDR 85 –40 SNR/SFDR (dB) AMPLITUDE (dBFS) –80 06296-051 5 06296-048 0 FREQUENCY (MHz) –60 –80 80 75 SNR 70 65 –100 0 5 10 15 20 25 FREQUENCY (MHz) 60 10 06296-049 –120 –60 –100 –100 –120 –40 25 30 35 40 45 50 Figure 19. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 50 MSPS 90 AIN = –0.5dBFS SNR = 72.36dB ENOB = 11.73 BITS SFDR = 86.21dBc –20 20 ENCODE (MSPS) Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 50 MSPS 0 15 06296-039 AMPLITUDE (dBFS) 0 AIN = –0.5dBFS SNR = 73.71dB ENOB = 11.95 BITS SFDR = 85.86dBc 85 SNR/SFDR (dB) –60 –80 75 SNR 70 65 0 5 10 15 FREQUENCY (MHz) 20 25 06296-050 –100 –120 80 Figure 17. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 50 MSPS 60 10 15 20 25 30 35 40 45 50 ENCODE (MSPS) Figure 20. SNR/SFDR vs. fSAMPLE, fIN = 19.7 MHz, fSAMPLE = 50 MSPS Rev. 0 | Page 14 of 52 06296-040 AMPLITUDE (dBFS) SFDR –40 AD9252 90 0 AIN1 AND AIN2 = –7dBFS SFDR = 83.64dB IMD2 = 95.57dBc –20 IMD3 = 84.26dBc 80 SFDR AMPLITUDE (dBFS) SNR/SFDR (dB) 70 60 50 80dB REFERENCE 40 –40 –60 –80 SNR 30 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 06296-041 10 –60 –120 0 Figure 21. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS 5 10 15 FREQUENCY (MHz) 20 25 06296-044 –100 20 Figure 24. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 50 MSPS 90 90 80 85 SFDR SFDR 80 60 SNR/SFDR (dB) SNR/SFDR (dB) 70 50 80dB REFERENCE 40 SNR 75 SNR 70 30 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) –10 0 60 06296-042 10 –60 1 90 AIN1 AND AIN2 = –7dBFS SFDR = 86.27dB IMD2 = 97.82dBc IMD3 = 86.13dBc 85 –40 SINAD/SFDR (dB) –60 –80 –100 SFDR 80 75 SINAD 70 65 0 5 10 15 FREQUENCY (MHz) 20 Figure 23. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 50 MSPS 25 60 –40 06296-043 –120 –20 0 20 40 TEMPERATURE (°C) 60 80 06296-046 AMPLITUDE (dBFS) –20 1000 Figure 25. SNR/SFDR vs. fIN, fSAMPLE = 50 MSPS Figure 22. SNR/SFDR vs. Analog Input Level, fIN = 19.7 MHz, fSAMPLE = 50 MSPS 0 10 100 ANALOG INPUT FREQUENCY (MHz) 06296-045 65 20 Figure 26. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, fSAMPLE = 50 MSPS Rev. 0 | Page 15 of 52 AD9252 2.0 1.8 1.5 1.6 NUMBER OF HITS (Millions) 1.047LSB rms 1.0 0 –0.5 –1.0 –1.5 1.0 0.8 0.6 0.4 0.2 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE 0 06296-053 –2.0 1.2 N–3 N–1 N N+ 1 N+2 N+3 CODE Figure 27. INL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 30. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS 1.0 0 NPR = 62.5dB NOTCH = 18.0MHz NOTCH WIDTH = 2.3MHz 0.8 –20 0.6 AMPLITUDE (dBFS) 0.4 DNL (LSB) N–2 06296-054 INL (LSB) 0.5 1.4 0.2 0 –0.2 –0.4 –0.6 –40 –60 –80 –100 0 2000 4000 6000 8000 10000 12000 14000 16000 CODE –120 06296-052 –1.0 5 0 10 15 Figure 28. DNL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS 25 Figure 31. Noise Power Ratio (NPR), fSAMPLE = 50 MSPS –30 0 –1 –35 –3dB BANDWIDTH = 325MHz –2 –40 AMPLITUDE (dBFS) –3 –45 –50 –55 –4 –5 –6 –7 –8 –60 –9 –65 –10 0 5 10 15 20 25 30 35 FREQUENCY (MHz) 40 –11 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 32. Full Power Bandwidth vs. Frequency, fSAMPLE = 50 MSPS Figure 29. CMRR vs. Frequency, fSAMPLE = 50 MSPS Rev. 0 | Page 16 of 52 06296-037 –70 06296-055 CMRR (dB) 20 FREQUENCY (MHz) 06296-038 –0.8 AD9252 THEORY OF OPERATION The AD9252 architecture consists of a pipelined ADC that is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock. realizing the maximum bandwidth of the ADC. Such use of low-Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit any unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” for more information on this subject. In general, the precise values depend on the application. The analog inputs of the AD9252 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 34 and Figure 35. 90 SFDR (dBc) 85 The analog input to the AD9252 is a differential switched-capacitor circuit designed for processing differential input signals. The input can support a wide common-mode range and maintain excellent performance. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. SNR/SFDR (dB) ANALOG INPUT CONSIDERATIONS 80 75 70 SNR (dB) CPAR 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 06296-056 60 H 1.6 06296-057 65 ANALOG INPUT COMMON-MODE VOLTAGE (V) H VIN+ Figure 34. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, fSAMPLE = 50 MSPS CSAMPLE S S S 90 S CSAMPLE VIN– 85 Figure 33. Switched-Capacitor Input Circuit The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 33). When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce the high differential capacitance seen at the analog inputs, thus SNR/SFDR (dB) H 06296-017 H CPAR Rev. 0 | Page 17 of 52 SFDR (dBc) 80 75 SNR (dB) 70 65 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 35. SNR/SFDR vs. Common-Mode Voltage, fIN = 35 MHz, fSAMPLE = 50 MSPS AD9252 ADT1–1WT 1:1 Z RATIO For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as 2V p-p 49.9Ω C R VIN+ ADC AD9252 CDIFF1 R AVDD VIN– C 1kΩ AGND 1kΩ REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF 06296-018 0.1μF 1C DIFF IS OPTIONAL. Figure 36. Differential Transformer-Coupled Configuration for Baseband Applications 2V p-p 16nH It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. ADT1–1WT 0.1μF 1:1 Z RATIO 16nH 65Ω 499Ω 16nH 33Ω VIN+ 2.2pF ADC AD9252 1kΩ 33Ω VIN– AVDD Maximum SNR performance is always achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9252, the largest input span available is 2 V p-p. 1kΩ 06296-019 0.1μF 1kΩ Figure 37. Differential Transformer-Coupled Configuration for IF Applications Differential Input Configurations Single-Ended Input Configuration There are several ways in which to drive the AD9252 either actively or passively. In either case, the optimum performance is achieved by driving the analog input differentially. One example is by using the AD8334 differential driver. It provides excellent performance and a flexible interface to the ADC (see Figure 39) for baseband applications. This configuration is common for medical ultrasound systems. A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+ pin while the VIN− pin is terminated. Figure 38 details a typical single-ended input configuration. However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9252. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. Two examples are shown in Figure 36 and Figure 37. AVDD C R In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. 2V p-p VIN+ 0.1µF 1kΩ 49.9Ω 1kΩ 25Ω R VIN– C 1kΩ 06296-020 0.1µF ADC AD9252 CDIFF1 AVDD 1C DIFF IS OPTIONAL. Figure 38. Single-Ended Input Configuration 0.1μF VIP 0.1μF 120nH VOH INH 1V p-p 187Ω AD8334 22pF 0.1μF LNA VGA 374Ω LMD VOL LON 18nF 274Ω VIN+ VIN 187Ω R VIN– VREF 0.1μF 0.1μF 0.1μF Figure 39. Differential Input Configuration Using the AD8334 Rev. 0 | Page 18 of 52 ADC AD9252 C 1.0kΩ 0.1μF R 1.0kΩ 10μF 06296-021 LOP AD9252 For optimum performance, the AD9252 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 40 shows one preferred method for clocking the AD9252. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9252 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9252 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. ADC AD9252 0.1µF CLK+ 100Ω PECL DRIVER 0.1µF CLK 150Ω RESISTORS ARE ADC AD9252 CLK– 240Ω 06296-023 240Ω 50Ω1 OPTIONAL. Figure 41. Differential PECL Sample Clock 0.1µF CLOCK INPUT AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1µF CLK+ CLK 0.1µF LVDS DRIVER 100Ω 0.1µF CLK 50Ω1 ADC AD9252 CLK– 50Ω1 150Ω RESISTORS ARE OPTIONAL. Figure 42. Differential LVDS Sample Clock 06296-024 CLOCK INPUT CMOS DRIVER CLK 0.1µF CLK CLK 0.1µF AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 50Ω1 39kΩ AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1µF 50Ω1 06296-022 SCHOTTKY DIODES: HSM2812 If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 41. The AD9510/AD9511/AD9512/AD9513/AD9514/ AD9515 family of clock drivers offers excellent jitter performance. CLOCK INPUT CLK– 0.1µF Figure 40. Transformer-Coupled Differential Clock 0.1µF CLK+ ADC AD9252 CLK 0.1µF CLOCK INPUT CLK– CLOCK INPUT OPTIONAL 0.1µF 100Ω CMOS DRIVER CLK+ 0.1µF 0.1µF CLK 50Ω1 Figure 43. Single-Ended 1.8 V CMOS Sample Clock 100Ω 50Ω 0.1µF CLOCK INPUT OPTIONAL 0.1µF 100Ω 0.1µF CLK+ ADC AD9252 CLK– 150Ω RESISTOR IS OPTIONAL. 06296-026 CLOCK INPUT AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 150Ω RESISTOR IS OPTIONAL. MINI-CIRCUITS ADT1–1WT, 1:1Z 0.1µF XFMR 0.1µF In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 43). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. 06296-025 CLOCK INPUT CONSIDERATIONS Figure 44. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9252 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9252. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. Rev. 0 | Page 19 of 52 AD9252 Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 46, the power dissipated by the AD9252 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 0.40 In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 45). Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit www.analog.com). 130 0.35 AVDD CURRENT 0.15 0 10 10 BITS 8 BITS 40 30 1 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 20 25 30 35 40 45 50 0.50 ENCODE (MSPS) 12 BITS 50 15 Figure 46. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS 70 60 0.55 DRVDD CURRENT 0.05 06296-015 SNR (dB) 14 BITS 80 0.60 0.10 110 16 BITS 0.65 TOTAL POWER POWER (W) 0.20 RMS CLOCK JITTER REQUIREMENT 90 0.70 0.25 120 100 0.75 0.30 CURRENT (A) The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9252. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 0.80 Figure 45. Ideal SNR vs. Input Frequency and Jitter Rev. 0 | Page 20 of 52 06296-062 SNR degradation = 20 × log 10 [1/2 × π × fA × tJ] AD9252 In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 4.7 μF decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 375 μs to restore full operation. There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features. Digital Outputs and Timing The AD9252 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SDIO/ODM pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO/ODM Pin section or Table 15 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9252 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. An example of the FCO and data stream with proper trace length and position can be found in Figure 47. CH1 500mV/DIV = FCO CH2 500mV/DIV = DCO CH3 500mV/DIV = DATA 5.0ns/DIV 06296-027 By asserting the PDWN pin high, the AD9252 is placed in power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed in a high impedance state. The AD9252 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. Figure 47. LVDS Output Timing Example in ANSI Mode (Default) An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 48. Figure 49 shows an example of when the trace lengths exceed 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all eight outputs in order to drive longer trace lengths (see Figure 50). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. Also notice in Figure 50 that the histogram has improved. In cases that require increased driver strength to the DCO and FCO outputs because of load mismatch, Register 15 allows the user to increase the drive strength by 2×. To do this, set the appropriate bit in Register 5. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 15. Bit 4 and Bit 5 will take precedence over this feature. See the Memory Map section for more details. Rev. 0 | Page 21 of 52 AD9252 EYE: ALL BITS 400 ULS: 12071/12071 EYE DIAGRAM VOLTAGE (mV) EYE DIAGRAM VOLTAGE (mV) 400 300 200 100 0 –100 –200 –300 –400 –0.5ns 0ns 0.5ns 1.0ns 0 –100 –200 –300 80 80 70 70 60 50 40 30 20 500 –50ps 0ps 50ps 100ps 150ps 06296-030 –100ps EYE: ALL BITS 0ns 0.5ns 1.0ns 1.5ns –100ps –50ps 0ps 50ps 100ps 150ps 50 40 30 20 Figure 50. Data Eye for LVDS Outputs in ANSI Mode with 100 Ω Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. If it is desired to change the output data format to twos complement, see the Memory Map section. ULS: 12067/12067 300 200 100 Table 8. Digital Output Coding 0 –100 Code 16383 8192 8191 0 –200 –300 –400 –500 –1.0ns –0.5ns 0ns 0.5ns 1.0ns (VIN+) − (VIN−), Input Span = 2 V p-p (V) +1.00 0.00 −0.000122 −1.00 Digital Output Offset Binary (D13 ... D0) 11 1111 1111 1111 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0000 1.5ns Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 14 bits times the sample clock rate, with a maximum of 700 Mbps (14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up for encode rates lower than 10 MSPS via the SPI. This allows encode rates as low as 5 MSPS. See the Memory Map section to enable this feature. 100 90 80 70 60 50 40 30 20 –100ps 0ps 100ps 200ps 06296-028 10 0 –200ps –0.5ns 60 0 –150ps 400 –1.5ns –1.0ns 10 Figure 48. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less than 24 Inches on Standard FR-4 EYE DIAGRAM VOLTAGE (mV) 100 –1.5ns 1.5ns TIE JITTER HISTOGRAM (Hits) TIE JITTER HISTOGRAM (Hits) –1.0ns 10 TIE JITTER HISTOGRAM (Hits) 200 90 0 –150ps ULS: 12072/12072 300 –400 –500 –1.5ns EYE: ALL BITS 06296-029 500 Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than 24 Inches on Standard FR-4 Rev. 0 | Page 22 of 52 AD9252 Two output clocks are provided to assist in capturing data from the AD9252. The DCO is used to clock the output data and is equal to seven times the sampling clock (CLK) rate. Data is clocked out of the AD9252 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. Table 9. Flex Output Test Modes Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checker board 0101 0110 0111 PN sequence long 1 PN sequence short1 One/zero word toggle 1000 1001 User input One/zero bit toggle 1010 1× sync 1011 One bit high 1100 Mixed frequency 1 Digital Output Word 1 N/A 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) N/A N/A 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) Register 0x19 to Register 0x1A 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) Digital Output Word 2 N/A Same Subject to Data Format Select N/A Yes Same Yes Same Yes 0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit) N/A N/A 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) Register 0x1B to Register 0x1C N/A No Yes Yes No No No N/A No N/A No N/A No PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is 9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1 (short), defines the pseudorandom sequence. Rev. 0 | Page 23 of 52 AD9252 When using the serial port interface (SPI), the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO timing, as shown in Figure 2, is 90° relative to the output data edge. Selected ODM Normal Operation ODM An 8-, 10-, and 12-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility to lower resolution systems. When changing the resolution to an 8-, 10-, or 12-bit serial stream, the data stream is shortened. See Figure 3 for a 12-bit example. SCLK/DTP Pin When using the SPI, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is represented first in the data output serial stream (see Figure 4). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. It should be noted that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Table 10. Output Driver Mode Pin Settings ODM Voltage 10 kΩ to AGND AVDD Resulting Output Standard ANSI-644 (default) Resulting FCO and DCO ANSI-644 (default) Low power, reduced signal option Low power, reduced signal option For applications that do not require SPI mode operation, the serial clock/digital test pattern (SCLK/DTP) pin can enable a single digital test pattern if this pin and the CSB pin are held high during device power-up. When the DTP is tied to AVDD, all the ADC channel outputs shift out the following pattern: 10 0000 0000 0000. The FCO and DCO outputs still work as usual while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant. Table 11. Digital Test Pattern Pin Settings Selected DTP Normal Operation DTP DTP Voltage 10 kΩ to AGND AVDD Resulting D+ and D− Normal operation 10 0000 0000 0000 Resulting FCO and DCO Normal operation Normal operation Please consult the Memory Map section for information on how to change these additional digital output timing features through the serial port interface or SPI. Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section to choose from the different options available. SDIO/ODM Pin CSB Pin For applications that do not require SPI mode operation, the SDIO/ODM pin can enable a low power, reduced signal option similar to the IEEE 1596.3 reduced range link output standard if this pin and the CSB pin are tied to AVDD during device powerup. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. The FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p. This output mode allows the user to further lower the power on the DRVDD supply. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 kΩ internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. The chip select bar (CSB) pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. RBIAS Pin To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the ADC’s AVDD current to a nominal 360 mA at 50 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. If SFDR performance is not as critical as power, simply adjust the ADC core current to achieve a lower power. Figure 51 and Figure 52 show the relationship between the dynamic range and power as the RBIAS resistance is changed. Nominally, a 10.0 kΩ value is used, as indicated by the dashed line. Rev. 0 | Page 24 of 52 AD9252 90 Internal Reference Operation A comparator within the AD9252 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 53), setting VREF to 1 V. 85 SNR/SFDR (dB) SFDR 80 The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. 75 70 SNR 60 0 5 10 15 20 25 RBIAS (kΩ) 06296-058 65 If the reference of the AD9252 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 55 depicts how the internal reference voltage is affected by loading. Figure 51. SNR/SFDR vs. RBIAS VIN+ 1.0 VIN– REFT 0.9 0.8 ADC CORE IAVDD (A) 0.7 0.1µF 0.1µF + 2.2µF REFB 0.6 0.1µF VREF 0.5 1µF 0.4 0.1µF SELECT LOGIC 0.3 0.5V SENSE 0.2 5 10 15 RBIAS (kΩ) 20 25 Figure 53. Internal Reference Configuration Figure 52. IAVDD vs. RBIAS Voltage Reference VIN+ A stable and accurate 0.5 V voltage reference is built into the AD9252. This is gained up by a factor of 2 internally, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9252. The recommended capacitor values and configurations for the AD9252 reference pin can be found in Figure 53. REFT ADC CORE SENSE Voltage AVDD Resulting VREF (V) N/A AGND to 0.2 V 1.0 + 2.2µF 0.1µF VREF 0.1µF1 AVDD 0.1µF REFB EXTERNAL REFERENCE 1µF1 0.1µF SELECT LOGIC 0.5V SENSE 1OPTIONAL. Table 12. Reference Settings Selected Mode External Reference Internal, 2 V p-p FSR VIN– 06296-032 0 06296-063 0 06296-031 0.1 Resulting Differential Span (V p-p) 2 × external reference 2.0 Rev. 0 | Page 25 of 52 Figure 54. External Reference Operation AD9252 0.02 External Reference Operation –0.02 –0.04 –0.10 –0.12 –0.14 –0.16 –20 0 20 40 TEMPERATURE (°C) 0 Figure 56. Typical VREF Drift –5 –10 –15 –20 –25 06296-061 VREF ERROR (%) –0.08 –0.18 –40 5 –30 –0.06 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) Figure 55. VREF Accuracy vs. Load Rev. 0 | Page 26 of 52 60 80 06296-060 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal of 1.0 V. 0 VREF ERROR (%) The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 56 shows the typical drift characteristics of the internal reference in 1 V mode. AD9252 SERIAL PORT INTERFACE (SPI) Table 13. Serial Port Pins Pin SCLK SDIO CSB Function Serial Clock. The serial shift clock in. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles. The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Fields W0 and W1. An example of the serial timing and its definitions can be found in Figure 58 and Table 14. In normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the user manual Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 13 compose the physical interface between the user’s programming device and the serial port of the AD9252. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load as the AD9252, Figure 57 shows the number of SDIO pins that can be connected together and the resulting VOH level. 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 Figure 57. SDIO Pin Loading Rev. 0 | Page 27 of 52 80 90 NUMBER OF SDIO PINS CONNECTED TOGETHER 100 06296-059 There are three pins that define the serial port interface, or SPI, to this particular ADC. They are the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 13). In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the Serial Port Interface (SPI) section. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. VOH The AD9252 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., user manual Interfacing to High Speed ADCs via SPI. AD9252 This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pinstrappable functions are supported on the SPI pins. tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 06296-033 SDIO DON’T CARE DON’T CARE Figure 58. Serial Timing Details Table 14. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Timing (minimum, ns) 5 2 40 5 2 16 16 1 tDIS_SDIO 5 Description Set-up time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Set-up time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 58) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 58) Rev. 0 | Page 28 of 52 AD9252 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), device index and transfer register map (Address 0x05 and Address 0xFF), and program register map (Address 0x08 to Address 0x25). Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. The left-hand column of the memory map indicates the register address number in hexadecimal. The default value of this address is shown in hexadecimal in the right-hand column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, Clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 at this address, the duty cycle stabilizer turns off. For more information on this and other functions, consult the user manual Interfacing to High Speed ADCs via SPI. Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 15, where an X refers to an undefined feature. DEFAULT VALUES LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Rev. 0 | Page 29 of 52 AD9252 Table 15. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 00 chip_port_config 0 01 chip_id 02 chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) Bit 0 (LSB) Default Value (Hex) 0 0x18 8-bit Chip ID Bits 7:0 (AD9252 = 0x09), (default) Read only Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode registers correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices. Child ID 6:4 (identify device variants of Chip ID) 011 = 50 MSPS X X X X Read only Device Index and Transfer Registers 04 device_index_2 X X X X Data Channel G 1 = on (default) 0 = off Data Channel F 1 = on (default) 0 = off Data Channel E 1 = on (default) 0 = off 0x0F Bits are set to determine which on-chip device receives the next write command. 05 device_index_1 X X X X Data Channel C 1 = on (default) 0 = off X Data Channel B 1 = on (default) 0 = off X Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) Bits are set to determine which on-chip device receives the next write command. device_update Clock Channel FCO 1 = on 0 = off (default) X 0x0F FF Clock Channel DCO 1 = on 0 = off (default) X Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X 0x00 Synchronously transfers data from the master shift register to the slave. ADC Functions 08 modes X X X X X 0x00 Determines various generic modes of chip operation. 09 clock X X X X X Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset X X Duty cycle stabilizer 1 = on (default) 0 = off 0x01 Turns the internal duty cycle stabilizer on and off. 0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Output test mode—see Table 9 in the Digital Outputs and Timing section 0x00 When set, the test data is placed on the output pins in place of normal data. X 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = user input 1001 = one/zero bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) Rev. 0 | Page 30 of 52 AD9252 Addr. (Hex) 14 Parameter Name output_mode Bit 7 (MSB) X 15 output_adjust X Bit 6 0 = LVDS ANSI (default) 1 = LVDS low power, (IEEE 1596.3 similar) X 16 output_phase X 19 user_patt1_lsb 1A Bit 5 X Bit 4 X Bit 0 (LSB) Bit 1 00 = offset binary (default) 01 = twos complement Default Value (Hex) 0x00 Bit 3 X Bit 2 Output invert 1 = on 0 = off (default) Output driver termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω X X X X X 0x03 B7 B6 B5 B4 0011 = output clock phase adjust (0000 through 1010) (Default: 180° relative to DATA edge) 0000 = 0° relative to DATA edge 0001 = 60° relative to DATA edge 0010 = 120° relative to DATA edge 0011 = 180° relative to DATA edge 0100 = 240° relative to DATA edge 0101 = 300° relative to DATA edge 0110 = 360° relative to DATA edge 0111 = 420° relative to DATA edge 1000 = 480° relative to DATA edge 1001 = 540° relative to DATA edge 1010 = 600° relative to DATA edge 1011 to 1111 = 660° relative to DATA edge B3 B2 B1 B0 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 21 serial_control LSB first 1 = on 0 = off (default) X X X 000 = 14 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 22 serial_ch_stat X X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default) X Channel powerdown 1 = on 0 = off (default) 0x00 Rev. 0 | Page 31 of 52 X X Channel output reset 1 = on 0 = off (default) DCO and FCO 2× drive strength 1 = on 0 = off (default) 0x00 0x00 Default Notes/ Comments Configures the outputs and the format of the data. Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSB. User-defined pattern, 2 MSB. Serial stream control. Default causes MSB first and the native bit stream (global). Used to power down individual sections of a converter (local). AD9252 Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9252, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length. It is required that the exposed paddle on the underside of the ADC is connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9252. An exposed continuous copper plane on the PCB should mate to the AD9252 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder filled or plugged. A single PC board ground plane should be sufficient when using the AD9252. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance is easily achieved. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the ADC and PCB. See Figure 59 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. 06296-034 SILKSCREEN PARTITION PIN 1 INDICATOR Figure 59. Typical PCB Layout Rev. 0 | Page 32 of 52 AD9252 EVALUATION BOARD capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply is needed. The 5.0 V supply, or AVDD_5 V, should have a 1 A current capability. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or AVDD_3.3 V, should have a 1 A current capability as well. The AD9252 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a transformer (default) or through the AD8334 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8334 drive circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 62 to Figure 66). Figure 60 shows the typical bench characterization setup used to evaluate the ac performance of the AD9252. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Analog Devices uses TTE, Allen Avionics, and K&L types of band-pass filters. The filter should be connected directly to the evaluation board if possible. See Figure 62 to Figure 72 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Simply connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. OUTPUT SIGNALS The default setup uses the HSC-ADC-FPGA high speed deserialization board to deserialize the digital output data and convert it to parallel CMOS. These two channels interface directly with the Analog Devices standard dual-channel FIFO data capture board (HSC-ADC-EVALB-DC). Two of the eight channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO. When operating the evaluation board in a nondefault condition, L701 to L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P702 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current WALL OUTLET 100V AC TO 240V AC 47Hz TO 63Hz – + – + – + AVDD_3.3V GND 3.3V_D GND 1.5V_FPGA GND VCC GND 3.3V + AD9252 EVALUATION BOARD CLK 1.5V – GND AVDD_5V XFMR INPUT 3.3V 3.3V + CHA TO CHH 14-BIT SERIAL LVDS HSC-ADC-FPGA HIGH SPEED DESERIALIZATION BOARD 2-CH SPI Figure 60. Evaluation Board Connection Rev. 0 | Page 33 of 52 14-BIT PARALLEL CMOS SPI HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD USB CONNECTION SPI PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE SPI 06296-035 ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER 1.8V – DRVDD_DUT – GND ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER 1.8V + + GND 5.0V – SWITCHING POWER SUPPLY AVDD_DUT 6V DC 2A MAX AD9252 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9252 Rev. A evaluation board. • POWER: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701. • AIN: The evaluation board is set up for a transformercoupled analog input with optimum 50 Ω impedance matching out to 150 MHz (see Figure 61). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2. A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Simply populate R406 and R407 with 0 Ω resistors and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 μF capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default working condition. Consult the AD9515 data sheet for more information about these and other options. If using an oscillator, two oscillator footprint options are also available (OSC401) to check the ADC performance. J401 gives the user flexibility in using the enable pin, which is common on most oscillators. 0 –1 –3dB CUTOFF = 186MHz –2 AMPLITUDE (dBFS) –3 –4 • PDWN: To enable the power-down feature, simply short J301 to the on position (AVDD) on the PDWN pin. • SCLK/DTP: To enable a digital test pattern on the digital outputs of the ADC, use J304. If J304 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 0000 will be enabled. See the SCLK/DTP Pin section for details. • SDIO/ODM: To enable the low power, reduced signal option similar to the IEEE 1595.3 reduced range link LVDS output standard, use J303. If J303 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, which reduces the power of the DRVDD supply. See the SDIO/ODM Pin section for more details. • CSB: To enable the SPI information on the SDIO and SCLK pins that is to be processed, simply tie J302 low in the always enable mode. To ignore the SDIO and SCLK information, tie J302 to AVDD. • Non-SPI Mode: For users who wish to operate the DUT without using SPI, simply remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/OMD pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. • D+, D−: If an alternative data capture method to the setup described in Figure 62 is used, optional receiver terminations, R318, R320 to R328, can be installed next to the high speed backplane connector. –5 –6 –7 –8 –9 –10 –11 –12 –14 0 50 100 150 200 250 300 350 400 450 FREQUENCY (MHz) 500 06296-036 –13 Figure 61. Evaluation Board Full Power Bandwidth • VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Simply populate R312 and R313 and remove C307. Proper use of the VREF options is noted in the Voltage Reference section. • RBIAS: RBIAS has a default setting of 10 kΩ (R301) to ground and is used to set the ADC core bias current. To further lower the core power (excluding the LVDS driver supply), simply change the resistor setting. However, performance of the ADC will degrade depending on the resistor chosen. See RBIAS section for more information. • CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is Rev. 0 | Page 34 of 52 AD9252 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION • Populate R101, R114, R127, R140, R201, R217, R233, and R251 with 0 Ω resistors in the analog input path. The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this particular drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 16. For more details on the AD8334 dual VGA, including how it works and its optional pin settings, consult the AD8334 data sheet. • Populate R106, R107, R119, R120, R132, R133, R144, R145, R206, R207, R223, R224, R239, R240, R257, and R258 with 10 kΩ resistors to provide an input common-mode level to the analog input. • Populate R105, R113, R118, R124, R131, R137, R151, and R160, R205, R213, R221, R222, R239, R240, R255, and R256 with 0 Ω resistors in the analog input path. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. • Currently, L505 to L520 and L605 to L620 are populated with 0 Ω resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary. Remove R102, R115, R128, R141, R202, R218, R234, R252, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path. Rev. 0 | Page 35 of 52 Rev. 0 | Page 36 of 52 Channel A P101 Figure 62. Evaluation Board Schematic, DUT Analog Inputs VGA Input Connection R115 64.9Ω R114 0Ω−DNP INH2 R102 64.9Ω R101 0Ω−DNP DNP: DO NOT POPULATE. Ain P103 Channel B Ain INH1 VGA Input Connection Ain DNP P104 Ain 0Ω R117 R103 0Ω C109 0.1µF C108 0.1µF AVDD_DUT R116 0Ω FB104 10Ω E102 R125 1KΩ R126 1kΩ 1 R105 0Ω−DNP R113 3 2 C114 0.1µF 0Ω−DNP R124 4 5 6 R118 0Ω−DNP C107 0.1µF 0Ω−DNP 4 5 T101 6 1 T102 3 2 1 CM2 CH_B CM2 CH_B CM1 CH_A CM1 CH_A R112 1kΩ 1 R111 1kΩ E101 C102 0.1µF C101 0.1µF AVDD_DUT FB101 10Ω R104 0Ω C113 DNP R120 DNP CM2 C106 DNP R107 DNP CM1 R119 DNP R106 DNP R162 499Ω FB106 10Ω FB105 10Ω FB103 10Ω R161 499Ω FB102 10Ω R122 33Ω R121 33Ω R110 33Ω R108 33Ω C110 DNP C103 DNP R156 DNP R109 1kΩ R157 DNP R123 1kΩ AVDD_DUT C112 DNP C111 2.2pF R153 DNP AVDD_DUT AVDD_DUT C105 DNP C104 2.2pF R152 DNP AVDD_DUT VIN_B VIN_B VIN_A VIN_A Ain Channel D P107 Ain INH4 Channel C P105 R141 64.9Ω R140 0Ω−DNP VGA Input Connection R128 64.9Ω R127 0Ω−DNP VGA Input Connection INH3 Ain P106 DNP DNP P108 Ain R142 0Ω R129 0Ω 1 CM3 CH_C CM3 CH_C E104 C123 0.1µF C122 0.1µF R149 1kΩ R150 1kΩ 1 3 2 1 3 2 1 R137 T104 4 5 6 R151 0Ω−DNP C121 0.1µF 0Ω−DNP 4 5 6 R131 0Ω−DNP T103 C128 0.1µF R160 CH_D CM4 0Ω−DNP CM4 CH_D R138 1kΩ R139 1kΩ E103 C116 0.1µF C115 0.1µF AVDD_DUT R143 0Ω FB110 10Ω AVDD_DUT FB107 10Ω R130 0Ω C127 DNP R145 DNP CM4 C120 DNP R133 DNP CM3 R144 DNP R132 DNP FB109 10Ω FB111 10Ω FB112 10Ω R164 499Ω R163 499Ω FB108 10Ω R147 33Ω C124 DNP R146 33Ω R136 33Ω C117 DNP R134 33Ω R159 DNP VIN_D R148 1kΩ VIN_D R155 DNP AVDD_DUT C126 DNP VIN_C R158 DNP AVDD_DUT C125 2.2pF VIN_C R135 1kΩ AVDD_DUT C119 DNP C118 2.2pF R154 DNP AVDD_DUT 06296-072 DNP P102 AD9252 Rev. 0 | Page 37 of 52 Ain Figure 63. Evaluation Board Schematic, DUT Analog Inputs (Continued) P203 Channel F VGA Input Connection R202 64.9Ω R201 0Ω−DNP R218 64.9Ω R217 0Ω−DNP INH6 INH5 DNP: DO NOT POPULATE. Ain P201 Channel E VGA Input Connection Ain DNP P204 Ain R219 0Ω R203 0Ω C209 0.1µF C208 0.1µF AVDD_DUT R220 0Ω FB204 10Ω 1 R231 1kΩ 2 3 CM6 R232 1kΩ 1 CH_F CM6 CH_F 4 5 6 4 C214 0.1µF 0Ω−DNP R222 T202 R221 0Ω−DNP C207 0.1µF 0Ω−DNP 5 6 3 R213 T201 R205 0Ω−DNP 2 1 1 CM5 CH_E CM5 CH_E R211 1kΩ R212 1kΩ E202 E201 C202 0.1µF C201 0.1µF AVDD_DUT FB201 10Ω R204 0Ω C213 DNP R224 DNP CM6 C206 DNP R207 DNP CM5 R223 DNP R206 DNP R225 499Ω FB206 10Ω FB205 10Ω FB203 10Ω R208 499Ω FB202 10Ω R227 33Ω R226 33Ω R210 33Ω R209 33Ω C210 DNP C203 DNP R215 DNP R229 DNP R228 1kΩ AVDD_DUT C212 DNP C211 2.2pF R230 DNP AVDD_DUT VIN_E VIN_E VIN_F VIN_F R214 1kΩ AVDD_DUT C205 DNP C204 2.2pF R216 DNP AVDD_DUT Ain DNP P207 Channel H Ain P205 Channel G R252 64.9Ω R251 0Ω−DNP INH8 VGA Input Connection R234 64.9kΩ R233 0Ω−DNP INH7 VGA Input Connection Ain DNP P208 Ain DNP P206 R253 0Ω R235 0Ω 1 E204 C223 0.1µF C222 0.1µF R265 1kΩ R266 1kΩ 1 CH_H CM8 CH_H 3 2 1 3 2 1 CM8 CM7 CH_G CM7 CH_G R249 1kΩ R250 1kΩ E203 C216 0.1µF C215 0.1µF AVDD_DUT R254 0Ω FB210 10Ω AVDD_DUT FB207 10Ω R236 0Ω 4 5 6 4 C228 0.1µF 0Ω−DNP R256 5 T204 6 R255 0Ω−DNP C221 0.1µF 0Ω−DNP R238 T203 R237 0Ω−DNP C227 DNP R258 DNP CM8 C220 DNP R240 DNP CM7 R257 DNP R239 DNP FB211 10Ω FB209 10Ω FB212 10Ω R259 499Ω R241 499Ω FB208 10Ω R261 33Ω C224 DNP R260 33Ω R245 33Ω C217 DNP R242 33Ω R263 DNP VIN_H R262 1kΩ VIN_H R264 DNP AVDD_DUT C226 DNP VIN_G R247 DNP AVDD_DUT C225 2.2pF VIN_G R246 1kΩ AVDD_DUT C219 DNP C218 2.2pF R248 DNP AVDD_DUT 06296-073 DNP P202 AD9252 Rev. 0 | Page 38 of 52 16 D+H D−H DRVDD DRGND AVDD D+C VIN−D D−C VIN+D D+D RBIAS FCO+ D−D FCO− DCO+ DCO− AVDD D+E VIN+E VIN−E D−E D+F AVDD D−F VIN+F VIN−F D+G D−G 32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CHB CHD CHD FCO FCO Figure 64. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface CHC CHC C305 0.1µF VOUT CHB R308 470kΩ D−B 31 R310 10kΩ R311 DNP R313 DNP C307 1µF R312 DNP VREF_DUT Remove C214 when using external Vref C306 0.1µF Reference Circuitry R306 100kΩ ADR510ARTZ TRIM/NC 1.0V D+B R309 4.99kΩ CHA CHA DRVDD_DUT GND AVDD_DUT 1kΩ R305 100kΩ OPTIONAL EXT REF 33 34 35 36 37 38 39 J301 J302 J303 J304 R317 0Ω R31 DNP R315 DNP R314 DNP Vref Select SCLK_DTP 1 1 SDIO_ODM R307 10kΩ U302 VIN−C AVDD_DUT D−A D+A DRVDD DRGND AVDD SCLK/DTP SDIO/ODM R319 1 CSB_DUT 1 R304 DNP 3 3 3 3 VREF = 1V CHH CHG CHF CHE CHD CHC CHB CHA FCO DCO SDO_CHB CSB4_CHB CSB3_CHB SDI_CHB SCLK_CHB VSENSE_DUT NC DTP Enable ODM Enable ALWAYS ENABLE SPI PDWN ENABLE VREF = 0.5V(1 + R219/R220) VREF = External VREF = 0.5V 2 DNP: DO NOT POPULATE. CHH 15 14 13 AVDD U301 40 AVDD_DUT R303 100kΩ AVDD_DUT R302 DNP CHH DRVDD_DUT GND 12 CLK+ AVDD CSB 41 42 VIN_A VIN_A AVDD_DUT VIN_B VIN_B AVDD_DUT 2 AVDD_DUT 11 10 VIN+C CLK CLK− PDWN AVDD 43 44 45 46 47 48 2 AVDD_DUT 9 REFB CLK REFT AD9252BCPZ-50 VREF AVDD SENSE 8 AVDD VIN+A VIN−A AVDD VIN−B VIN+B AVDD 2 AVDD_DUT SLUG 7 0 AVDD_DUT 64 VIN+H VIN_F 63 6 VIN_F 62 VIN_H AVDD_DUT 61 VIN−H VIN_E 60 AVDD VIN_E 59 5 58 VIN_H 57 AVDD_DUT AVDD_DUT 56 VIN−G VREF_DUT 55 4 54 3 VSENSE_DUT 53 VIN_G VIN_D 52 VIN+G R301 10kΩ 51 2 VIN_D 50 VIN_G AVDD_DUT 49 AVDD C304 0.1µF VIN_C 1 C303 4.7µF Reference Decoupling VIN_C AVDD_DUT C302 0.1µF C301 0.1µF 1 21 2 22 3 23 4 24 5 25 6 26 7 27 8 28 9 29 10 30 31 51 32 52 33 53 34 54 35 55 36 56 37 57 38 58 39 59 40 60 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 P301 Digital Outputs GNDAB1 GNDAB2 GNDAB3 GNDAB4 GNDAB5 GNDAB6 GNDAB7 GNDAB8 GNDAB9 GNDAB10 GNDCD1 GNDCD2 GNDCD3 GNDCD4 GNDCD5 GNDCD6 GNDCD7 GNDCD8 GNDCD9 GNDCD10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 11 12 13 14 15 16 17 18 19 20 41 42 43 44 45 46 47 48 49 50 DNP DNP R328 SDO_CHA CSB2_CHA CSB1_CHA SDI_CHA SCLK_CHA CHH DNP R327 DNP R326 CHG DNP R325 CHF DNP R324 DNP R323 DNP R322 DNP R321 DNP R320 R318 CHE CHD CHC CHB CHA FCO DCO R318,R320−R328 Optional Output Terminations AD9252 AVDD_DUT CW GND DCO DCO CHE CHE CHF CHF CHG CHG 06296-074 Figure 65. Evaluation Board Schematic, Clock Circuitry Rev. 0 | Page 39 of 52 DNP: DO NOT POPULATE. R405 0Ω 0Ω 1 6 C411 0.1µF R418 0Ω 7 5 8 S7 CR401 S8 S6 HSMS-2812-TR1G S9 9 4 T401 VREF 10 2 S10 S10 S9 11 3 1 SIGNAL=DNC;27,28 S5 S4 S3 S2 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 S8 12 R416 E401 GND_PAD AD9515BCPZ S7 13 0Ω R415 R417 0Ω SYNCB CLKB CLK U401 S6 14 C403 0.1µF OPT_CLK R413 10kΩ 5 3 2 AVDD_3.3V S5 15 Enc R404 49.9Ω C402 0.1µF R407 0Ω R412 DNP DNP R411 49.9Ω DNP R414 4.12kΩ S4 DNP P402 P401 OPT_CLK OPT_CLK R406 0Ω DNP R410 10kΩ S3 S1 OUT0 OUT1B OUT1 OUT0B 16 Clock Circuit Enc CRYSTAL_3 7 1 R409 DNP RSET R403 0Ω DNP GND R402 10kΩ OPT_CLK DISABLE OSC401 R408 DNP VS OUT 5 3 1 J401 ENABLE OSC401 S0 C410 0.1µF 0.1µF C409 18 19 22 23 R420 240Ω CLK R423 100Ω R421 240Ω R422 100Ω C408 0.1µF DNP DNP C407 0.1µF DNP 0.1µF C406 DNP 0.1µF C405 CLK CLIP SINE OUT (DEFAULT) OPTIONAL CLOCK DRIVE CIRCUIT GND 8 OE OE 3 32 OUT GND VCC VCC 2 1 10 12 14 Optional Clock Oscillator OSC401 AVDD_3.3V 31 Input Encode AVDD_3.3V R401 10kΩ S2 25 3 S1 2 C401 0.1µF 33 S0 1 AVDD_3.3V CLK R446 DNP LVDS OUTPUT CLK LVPECL OUTPUT C 41 2 0.1µF C413 0.1µF AVDD_3.3V S5 AVDD_3.3V S4 AVDD_3.3V S3 AVDD_3.3V S2 AVDD_3.3V S1 AVDD_3.3V S0 AVDD_3.3V C 4 14 0.1µF DNP 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω C 415 0.1µF R434 DNP R432 DNP R430 DNP R428 DNP R426 DNP R424 C416 0.1µF R435 R433 R431 R429 R427 R425 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω C417 0.1µF C 4 18 0.1µF S10 AVDD_3.3V S9 AVDD_3.3V S8 AVDD_3.3V S7 AVDD_3.3V S6 AVDD_3.3V DNP R444 DNP R442 DNP R440 DNP R438 R436 0Ω 0Ω 0Ω 0Ω 0Ω AD9515 Pin−strap settings R445 R443 R441 R439 DNP R437 0Ω 0Ω 0Ω 0Ω 0Ω AD9252 6 06296-075 1 2 EXT VG CW GND VG12 EXT VG L502 120nH Variable Gain Circuit (0−1.0V DC) VG12 External Variable Gain Drive Rev. 0 | Page 40 of 52 R508 274Ω INH1 C524 0.1µF 16 15 INH3 LMD3 VIP4 LON4 LOP4 COM4X LMD1 LMD4 INH1 INH4 COM1 COM4 COM3 L501 120nH 0.1µF C513 27 26 24 23 20 19 18 R509 274Ω GND VG34 External Variable Gain Drive Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive C532 0.1µF VIN4 25 VG34 AVDD_5V 22 17 C527 0.018µF HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV DNP 10kΩ R510 COM34 VOH4 VOL4 VPS34 VOL3 VOH3 AVDD_5V 31 Rclamp Pin VPS4 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C540 0.1µF CH_D AVDD_5V C542 DNP R514 187Ω R515 374Ω R516 DNP L505 0Ω AVDD_5V C541 0.1µF L506 0Ω 187Ω C550 DNP R526 187Ω R525 187Ω R527 374Ω R528 DNP L513 0Ω C549 0.1µF L514 0Ω 187Ω R530 C552 0.1µF L517 0Ω R532 374Ω R533 DNP L518 0Ω C554 DNP 187Ω R531 C553 0.1µF CH_A L520 0Ω C555 DNP C551 DNP L519 0Ω CH_A R534 DNP L516 0Ω CH_B R529 DNP L515 0Ω CH_B C548 0.1µF AVDD_5V R519 C545 0.1µF R518 R520 374Ω R521 DNP L510 0Ω C546 DNP 187Ω C544 0.1µF L509 0Ω CH_C L512 0Ω C547 DNP L507 0Ω C543 DNP L511 0Ω CH_C Populate L505−L520 with 0Ω resistors or design your own filter. R522 DNP L508 0Ω CH_D R517 DNP MODE Pin Positive Gain Slope = 0−1.0V Negitive Gain Slope = 2.25−5.0V C535 10µF C531 1000pF GAIN34 C530 0.1µF CLMP34 0.1µF HILO C529 VCM4 EN12 C528 0.1µF COM3X LON3 LOP3 VIP3 EN34 C534 0.1µF R512 10kΩ VG34 Variable Gain Circuit (0−1.0V DC) DNP: DO NOT POPULATE. C515 0.018µF 14 13 12 11 COM34 NC MODE COM12 VOH2 VOL2 VPS12 VOL1 VOH1 COM12 C533 10µF R536 39kΩ R535 10kΩ R507 274Ω NC 2 C523 VIN3 CLMP12 VCM3 1 0.1µF C501 INH2 C503 22pF 0.1µF COM2 10 COM1X VPS3 LOP1 9 LON1 AD8334ACPZ-REEL VIP1 AVDD_5V 64 VIN1 VPS2 63 VPS1 AVDD_5V 62 VIN2 C505 0.1µF VIP2 61 GAIN12 8 60 7 59 6 58 LOP2 57 LON2 56 5 55 4 AVDD_5V C511 0.1µF JP502 AVDD_5V 54 R513 187Ω 0.1µF C518 VG12 COM2X 53 LMD2 52 3 51 VCM2 INH2 R504 10kΩ VCM1 2 50 1 U501 AVDD_5V 0.1µF C506 HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV Rclamp Pin AVDD_5V 49 R524 10kΩ 0.1µF C522 C538 0.1µF C537 0.1µF C504 0.1µF DNP 10kΩ R506 R505 10kΩ C509 0.1µF INH3 INH4 C508 0.1µF C510 10µF R502 39kΩ R501 10kΩ C507 1000pF Power Down Enable (0−1V=Disable Power) C512 10µF 06296-076 JP501 AD9252 R523 10kΩ C536 0.1µF R511 10kΩ 30 29 28 21 C526 22pF L504 120nH 0.1µF C525 R503 274Ω C502 0.018µF C521 0.018µF C514 22pF C520 22pF L503 120nH 0.1µF C519 CW AVDD_5V 1 CW C615 0.018µF L602 120nH GND VG56 Variable Gain Circuit (0−1.0V DC) VG56 External Variable Gain Drive Rev. 0 | Page 41 of 52 R608 274Ω INH5 C624 0.1µF 16 15 INH3 LMD3 COM3X LON3 LOP3 VPS4 VIN4 LOP4 VIP4 COM4X LON4 LMD4 INH1 INH4 COM1 COM4 COM3 L601 120nH 0.1µF C613 AVDD_5V 30 27 26 25 24 20 19 R609 274Ω 18 17 VG78 External Variable Gain Drive Figure 67. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued) C632 0.1µF GAIN34 31 VG78 AVDD_5V 23 C627 0.018µF C631 1000pF CLMP34 32 Rclamp Pin HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV DNP 10kΩ R610 HILO C630 0.1µF EN12 0.1µF VCM4 C629 EN34 C628 0.1µF COM34 VOH4 VOL4 VPS34 VOL3 NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C634 0.1µF C635 10µF R612 10kΩ VG78 Variable Gain Circuit (0−1.0V DC) DNP: DO NOT POPULATE. R607 274Ω 14 13 12 VOH3 COM34 NC MODE COM12 VOH2 VOL2 VPS12 VOL1 VOH1 COM12 C633 10µF R635 39kΩ R634 10kΩ C623 0.1µF VIP3 VIN3 CLMP12 VCM3 2 0.1µF C601 EXT VG C603 22pF 11 LMD1 VPS3 COM1X AD8334ACPZ-REEL LON1 VPS2 VIP1 10 COM2 VIN2 LOP1 9 64 VIN1 AVDD_5V 63 VIP2 62 VPS1 8 C605 0.1µF 7 61 GAIN12 AVDD_5V 60 6 59 LOP2 58 5 57 INH6 C618 56 0.1µF 55 LON2 AVDD_5V COM2X 54 4 53 3 52 VCM2 LMD2 51 VCM1 INH2 VG56 50 2 49 1 U601 10kΩ JP602 AVDD_5V 0.1µF C606 Rclamp Pin HILO Pin=LO=+/− 50mV HILO Pin=H=+/− 75mV AVDD_5V AVDD_5V R604 0.1µF C622 C617 0.1µF C616 0.1µF C604 0.1µF DNP 10kΩ R606 R605 10kΩ C609 0.1µF INH7 INH8 C608 0.1µF C610 10µF R602 39kΩ R601 10kΩ C607 1000pF Power Down Enable (0−1V=Disable Power) AVDD_5V AVDD_5V CH_H C642 DNP R614 187Ω R615 374Ω R618 187Ω R620 374Ω C645 0.1µF L610 0Ω C646 DNP C640 0.1µF C644 0.1µF L609 0Ω R621 DNP C641 0.1µF L606 0Ω R616 DNP L605 0Ω L612 0Ω C647 DNP C643 DNP L607 0Ω CH_G R625 187Ω AVDD_5V R623 10kΩ R624 10kΩ R619 187Ω C648 0.1µF CH_F C651 DNP R629 DNP C649 0.1µF L614 0Ω L616 0Ω CH_F R626 187Ω R627 374Ω R628 DNP L613 0Ω C650 DNP L615 0Ω Populate L605−L620 with 0Ω resistors or design your own filter. R622 DNP L611 0Ω CH_G R617 DNP L608 0Ω CH_H Positive Gain Slope = 0−1.0V Negative Gain Slope = 2.25−5.0V MODE Pin R613 187Ω 1 2 EXT VG C612 10µF R630 187Ω C652 0.1µF L617 0Ω L619 0Ω CH_E R631 187Ω R632 374Ω R633 DNP L618 0Ω C654 DNP L620 0Ω C655 DNP R636 DNP C653 0.1µF CH_E 06296-077 JP601 AD9252 C611 0.1µF C636 0.1µF 29 R611 10kΩ 28 22 21 C626 22pF L604 120nH R603 274Ω 0.1µF C625 C602 0.018µF C621 0.018µF C614 22pF C620 22pF L603 120nH 0.1µF C619 GND CW AVDD_5V 4 OPTIONAL GREEN Rev. 0 | Page 42 of 52 Figure 68. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry ADP3339ZAKC−1.8-RL GND 1 2 OUT 4 OUT 4 E701 J702 1 0Ω−DNP R704 C717 1µF L706 10µH C715 1µF L705 10µH 0Ω−DNP R703 DUT_DRVDD DUT_AVDD 0Ω−DNP R705 R711 10kΩ C721 1µF PWR_IN C719 1µF PWR_IN R714 10kΩ R715 10kΩ 3 IN IN GND ADP3339ZAKC−3.3-RL U703 3 A2 2 1 A1 5 Y1 Y2 R712 1kΩ SDIO_ODM 2 OUT 4 OUT 2 OUT 4 OUT 4 VCC 5 6 Y2 4 VCC Y1 6 NC7WZ16P6X_NL U702 ADP3339ZAKC−5-RL7 U705 U706 3 GND 3 A2 2 1 A1 NC7W207P6X_NL GND DNP: DO NOT POPULATE. GND C716 1µF 2 IN 10 U704 MCLR/GP3 9 3 CR701 1 PWR_IN 8 OUT OUT GP0 7 2 GP1 6 GND 1 5 ADP3339ZAKC−1.8-RL PICVCC 4 ISP 2 3 C714 1µF MCLR/GP3 1 IN 5 PICVCC PWR_IN GP0 C703 0.1µF U707 MCLR/GP3 GP2 PIC12F629-I/SNG GP1 C702 0.1µF 3 R702 261Ω 4 6 7 AVDD_DUT C722 1µF L708 10µH C720 1µF L707 10µH CSB_DUT AVDD_DUT SCLK_DTP AVDD_DUT R713 1kΩ 5V_AVDD 3.3V_AVDD R710 1kΩ AVDD_3.3V AVDD_DUT AVDD_DUT AVDD_5V AVDD_3.3V C744 0.1µF C730 0.1µF C723 0.1µF 2 Input Optional Power 3 C741 0.1µF C746 0.1µF C732 0.1µF C725 0.1µF P8 P7 P6 P5 P4 P3 P2 P1 P702 DNP 8 7 6 5 4 3 2 1 DRVDD_DUT C747 0.1µF C733 0.1µF C726 0.1µF Decoupling Capacitors C740 0.1µF C745 0.1µF C731 0.1µF C724 0.1µF 1 7.5V POWER CON005 2.5MM JACK P701 6V, 2A max Power Supply Input C748 0.1µF C734 0.1µF C742 0.1µF C743 0.1µF AVDD_5V C735 0.1µF DUT_DRVDD DUT_AVDD 5V_AVDD 3.3V_AVDD 10µF C704 C727 0.1µF F701 NANOSMDC110F-2 D701 C749 0.1µF S2A-TP C750 0.1µF L704 10µH L702 10µH L701 10µH L703 10µH C711 10µF C707 10µF C705 10µF C709 10µF FER701 C751 0.1µF 4 1 3 2 C752 0.1µF C712 0.1µF C753 0.1µF DRVDD_DUT C708 0.1µF AVDD_DUT C706 0.1µF AVDD_5V C710 0.1µF AVDD_3.3V SK33-TP D702 +1.8V +1.8V +5.0V +3.3V GREEN PIC PROGRAMMING HEADER RESET/ REPROGRAM 3 2 GP1 GP0 0Ω GP4 0Ω R706 GP5 R707 3 0Ω 2 0Ω R708 R701 4.7kΩ 8 REMOVE WHEN USING OR PROGRAMMING PIC (U402) PWR_IN R716 261Ω CR702 1 S701 VSS SDI_CHA R709 VDD U701 CSB1_CHA 1 3 SCLK_CHA 0.1µF J701 AVDD_5V SDO_CHA C701 1 AVDD_3.3V SPI CIRCUITRY FROM FIFO 06296-078 +5V = PROGRAMMING = AVDD_5V +3.3V = NORMAL OPERATION = AVDD_3.3V AD9252 1 06296-079 AD9252 Figure 69. Evaluation Board Layout, Primary Side Rev. 0 | Page 43 of 52 06296-080 AD9252 Figure 70. Evaluation Board Layout, Ground Plane Rev. 0 | Page 44 of 52 06296-081 AD9252 Figure 71. Evaluation Board Layout, Power Plane Rev. 0 | Page 45 of 52 06296-082 AD9252 Figure 72. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. 0 | Page 46 of 52 AD9252 Table 16. Evaluation Board Bill of Materials (BOM) 1 Item 1 2 Qty per Board 1 118 3 8 4 8 5 1 6 4 7 8 REFDES AD9252LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753 C104, C111, C118, C125, C204, C211, C218, C225 C510, C512, C533, C535, C610, C612, C633, C635 C303 Device PCB Capacitor Package PCB 402 Value PCB 0.1 μF, ceramic, X5R, 10 V, 10% tol Manufacturer Manufacturer Part Number Murata GRM155R71C104KA88D Capacitor 402 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V Murata GRM1555C1H2R20CZ01D Capacitor 805 10 μF, 6.3 V ±10% ceramic, X5R Murata GRM219R60J106KE19D Capacitor 603 Murata GRM188R60J475KE19D C507, C531, C607, C631 C502, C515, C521, C527, C602, C615, C621, C627 Capacitor 402 Murata GRM155R71H102KA01D Capacitor 402 4.7 μF, ceramic, X5R, 6.3 V, 10% tol 1000 pF, ceramic, X7R, 25 V, 10% tol 0.018 μF, ceramic, X7R, 16 V, 10% tol AVX 0402YC183KAT2A Rev. 0 | Page 47 of 52 AD9252 Item 8 Qty per Board 8 9 1 10 9 11 16 12 4 13 REFDES C503, C514, C520, C526, C603, C614, C620, C626 C704 Device Capacitor Package 402 Value 22 pF, ceramic, NPO, 5% tol, 50 V Manufacturer Murata Manufacturer Part Number GRM1555C1H220JZ01D Capacitor 1206 Rohm TCA1C106M8R Capacitor 603 10 μF, tantalum, 16 V, 20% tol 1 μF, ceramic, X5R, 6.3 V, 10% tol Murata GRM188R61C105KA93D Capacitor 805 0.1 μF, ceramic, X7R, 50 V, 10% tol Murata GRM21BR71H104KA01L 10 μF, ceramic, X5R, 6.3 V, 20% tol 30 V, 20 mA, dual Schottky Green, 4 V, 5 m candela 3 A, 30 V, SMC Murata GRM188R60J106ME47D Agilent Technologies Panasonic Micro Commercial Co. Micro Commercial Co. Tyco/Raychem HSMS-2812-TR1G Capacitor 603 1 C307, C714, C715, C716, C717, C719, C720, C721, C722 C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, C648, C649, C652, C653 C705, C707, C709, C711 CR401 Diode SOT-23 14 15 2 1 CR701, CR702 D702 LED Diode 16 1 D701 Diode 17 1 F701 Fuse 603 DO214AB DO214AA 1210 18 1 FER701 Choke coil 2020 19 24 Ferrite bead 603 20 4 Connector 2-pin 21 6 Connector 3-pin 23 1 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212 JP501, JP502, JP601, JP602 J301, J302, J303, J304, J401, J701 J702 Connector 10-pin 24 8 Ferrite bead 1210 25 8 Inductor 402 L701, L702, L703, L704, L705, L706, L707, L708 L501, L502, L503, L504, L601, L602, L603, L604 5 A, 50 V, SMC 6.0 V, 2.2 A trip-current resettable fuse 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz 10 Ω, test frequency 100 MHz, 25% tol, 500 mA LNJ314G8TRA SK33-TP S2A-TP NANOSMDC110F-2 Murata DLW5BSN191SQ2L Murata BLM18BA100SN1D 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin 100 mil header, male, 2 × 5 double row straight 10 μH, bead core 3.2 × 2.5 × 1.6 SMD, 2 A Samtec TSW-102-07-G-S Samtec TSW-103-07-G-S Samtec TSW-105-08-G-D Murata BLM31PG500SN1L 120 nH, test freq 100 MHz, 5% tol, 150 mA Murata LQG15HNR12J02D Rev. 0 | Page 48 of 52 AD9252 Item 26 Qty per Board 32 27 1 28 9 29 Manufacturer Part Number NRC04Z0TRF REFDES L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 OSC401 Device Resistor Package 805 Value 0 Ω, 1/8 W, 5% tol Manufacturer NIC Components Corp. Oscillator SMT Valphey Fisher VFAC3H-L-50MHz Connector SMA Johnson Components 142-0701-851 1 P101, P103, P105, P107, P201, P203, P205, P207, P401 P301 Clock oscillator, 50.00 MHz, 3.3 V, ±5% duty cycle Side-mount SMA for 0.063" board thickness Connector HEADER Tyco 6469169-1 30 1 P701 Connector Switchcraft RAPC722X 31 21 Resistor NIC Components Corp. NRC04J103TRF 32 18 Resistor 402 0 Ω, 1/16 W, 5% tol NIC Components Corp. NRC04Z0TRF 33 8 Resistor 402 64.9 Ω, 1/16 W, 1% tol 8 Resistor 603 0 Ω, 1/10 W, 5% tol 35 28 Resistor 402 1 kΩ, 1/16 W, 1% tol NIC Components Corp. NIC Components Corp. NIC Components Corp. NRC04F64R9TRF 34 36 16 R301, R307, R401, R402, R410, R413, R504, R505, R511, R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715 R103, R117, R129, R142, R203, R219, R235, R253, R317, R405, R415, R416, R417, R418, R706, R707, R708, R709 R102, R115, R128, R141, R202, R218, R234, R252 R104, R116, R130, R143, R204, R220, R236, R254 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713 R108, R110, R121, R122, R134, R136, R146, R147, R209, R210, R226, R227, R242, R245, R260, R261 0.1", PCMT 402 1469169-1, right angle 2-pair, 25 mm, header assembly RAPC722, power supply connector 10 kΩ, 1/16 W, 5% tol Resistor 402 33 Ω, 1/16 W, 5% tol NIC Components Corp. NRC04J330TRF Rev. 0 | Page 49 of 52 NRC06Z0TRF NRC04F1001TRF AD9252 Item 37 Qty per Board 8 38 Device Resistor Package 402 Value 499 Ω, 1/16 W, 1% tol 3 REFDES R161, R162, R163, R164, R208, R225, R241, R259 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W, 1% tol 39 1 R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol 40 1 R404 Resistor 402 41 1 R309 Resistor 402 49.9 Ω, 1/16 W, 0.5% tol 4.99 kΩ, 1/16 W, 5% tol 42 5 R310, R501, R535, R601, R634 Potentiometer 3-lead 43 1 R308 Resistor 402 44 4 R502, R536, R602, R635 Resistor 402 39 kΩ, 1/16 W, 5% tol 45 16 Resistor 402 187 Ω, 1/16 W, 1% tol 46 8 Resistor 402 374 Ω, 1/16 W, 1% tol 47 8 Resistor 402 274 Ω, 1/16 W, 1% tol 48 11 Resistor 201 0 Ω, 1/20 W, 5% tol 49 1 R513, R514, R518, R519, R525, R526, R530, R531, R613, R614, R618, R619, R625, R626, R630, R631 R515, R520, R527, R532, R615, R620, R627, R632 R503, R507, R508, R509, R603, R607, R608, R609 R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445 R701 Resistor 402 4.7 kΩ, 1/16 W, 1% tol 50 1 R702 Resistor 402 261 Ω, 1/16 W, 1% tol 51 1 R716 Resistor 603 261 Ω, 1/16 W, 1% tol 52 2 R420, R421 Resistor 402 240 Ω, 1/16 W, 5% tol 53 2 R422, R423 Resistor 402 100 Ω, 1/16 W, 1% tol 54 1 S701 Switch SMD LIGHT TOUCH, 100GE, 5 mm 10 kΩ, Cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 W 470 kΩ, 1/16 W, 5% tol Rev. 0 | Page 50 of 52 Manufacturer NIC Components Corp. NIC Components Corp. NIC Components Corp. Susumu Manufacturer Part Number NRC04F4990TRF NRC04F1003TRF NRC04F4121TRF RR0510R-49R9-D NIC Components Corp. COPAL ELECTRONICS NRC04F4991TRF NIC Components Corp. NIC Components Corp. NIC Components Corp. NRC04J474TRF NIC Components Corp. NIC Components Corp. NIC Components Corp. NRC04F3740TRF NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. Panasonic NRC04J472TRF CT94EW103 NRC04J393TRF NRC04F1870TRF NRC04F2740TRF NRC02Z0TRF NRC04F2610TRF NRC06F261OTRF NRC04J241TRF NRC04F1000TRF EVQ-PLDA15 AD9252 Item 55 Qty per Board 9 56 Device Transformer Package CD542 2 REFDES T101, T102, T103, T104, T201, T202, T203, T204, T401 U704, U707 IC SOT-223 57 2 U501, U601 IC CP-64-3 58 59 60 1 1 1 U706 U705 U301 IC IC IC SOT-223 SOT-223 CP-64-3 61 1 U302 IC SOT-23 62 1 U401 IC 63 1 U702 IC 64 1 U703 IC 65 1 U701 IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC 1 Value ADT1-1WT+, 1:1 impedance ratio transformer ADP33339AKC-1.8-RL, 1.5 A, 1.8 V LDO regulator AD8334ACPZ-REEL, ultralow noise precision dual VGA ADP33339AKC-5-RL7 ADP33339AKC-3.3-RL AD9252BCPZ-50, octal, 14-bit, 50 MSPS serial LVDS 1.8 V ADC ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference AD9515BCPZ, 1.6 GHz clock distribution IC NC7WZ07P6X_NL, UHS dual buffer NC7WZ16P6X_NL, UHS dual buffer Flash prog mem 1kx14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series This BOM is RoHS compliant. Rev. 0 | Page 51 of 52 Manufacturer Mini-Circuits Manufacturer Part Number ADT1-1WT+ Analog Devices ADP3339AKCZ-1.8-RL Analog Devices AD8334ACPZ-REEL Analog Devices Analog Devices Analog Devices ADP3339AKCZ-5-RL7 ADP3339AKCZ-3.3-RL AD9252BCPZ-50 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ Fairchild NC7WZ07P6X_NL Fairchild NC7WZ16P6X_NL Microchip PIC12F629-I/SNG AD9252 OUTLINE DIMENSIONS 9.00 BSC SQ 0.30 0.25 0.18 0.60 MAX 0.60 MAX 64 1 48 49 PIN 1 INDICATOR PIN 1 INDICATOR 8.75 BSC SQ TOP VIEW (BOTTOM VIEW) 0.50 0.40 0.30 33 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 17 16 32 0.25 MIN 0.05 MAX 0.02 NOM SEATING PLANE 0.50 BSC 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 063006-B 1.00 0.85 0.80 7.25 7.10 SQ 6.95 EXPOSED PAD Figure 73. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Octal (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model AD9252BCPZ-50 1 AD9252BCPZRL7-501 AD9252-50EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel Evaluation Board Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06296-0-10/06(0) Rev. 0 | Page 52 of 52 Package Option CP-64-3 CP-64-3