CXD3400N 6-channel CCD Vertical Clock Driver Description The CXD3400N is a vertical clock driver for CCD image sensor. This IC is composed of 6 channels which supports high frame rate readout mode. 20 pin SSOP (Plastic) Features • Composition Vertical transfer output 3 levels driver × 4 2 levels driver × 2 Electronic shutter output 2 levels driver × 1 • Suitable drive capability for high-pixel CCD (40% improved compared to current device) • Small package (20-pin SSOP) • 2.7 to 5.5V supported input interface Applications Digital still camera Structure CMOS Absolute Maximum Ratings • Supply voltage VDD GND – 0.3 to +7.0 • Supply voltage VL GND to –10 • Supply voltage VH VL + 26 • Input voltage VIN GND – 0.3V to VDD + 0.3 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 V V V V °C °C Recommended Operating Conditions • Supply voltage VDD 2.7 to 5.5 • Supply voltage VL –5.0 to –9.0 • Supply voltage VH 11.5 to 15.5 • Operating temperature Topr –20 to +75 V V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98Y42A9X CXD3400N Block Diagram VDD 20 SHT 1 Input Buffer XSHT 2 19 V3B XV3 3 18 VL XSG3B 4 17 V3A XSG3A 5 16 V1B XV1 6 15 VH XSG1B 7 14 V1A XSG1A 8 13 V4 XV4 9 12 V2 XV2 10 11 GND Pin Description Pin No. Symbol Functions I/O — 1 VDD Input power supply (3.3V system) 2 XSHT I SHT pulse input 3 XV3 I V3A and V3B transfer pulse input 4 XSG3B I V3B readout pulse input 5 XSG3A I V3A readout pulse input 6 XV1 I V1A and V1B readout pulse input 7 XSG1B I V1B readout pulse input 8 XSG1A I V1A readout pulse input 9 XV4 I V4 transfer pulse input 10 XV2 I V2 transfer pulse input 11 GND — GND (= VM) 12 V2 O High voltage output (2 levels: VM, VL) 13 V4 O High voltage output (2 levels: VM, VL) 14 V1A O High voltage output (3 levels: VH, VM, VL) 15 VH — Positive power supply for high voltage output (15V system) 16 V1B O High voltage output (3 levels: VH, VM, VL) 17 V3A O High voltage output (3 levels: VH, VM, VL) 18 VL — Negative power supply for high voltage output (–7.5V system) 19 V3B O High voltage output (3 levels: VH, VM, VL) 20 SHT O High voltage output (2 levels: VH, VL) –2– CXD3400N Truth Table Input Output XV1, 3 XSG1A, 1B, 3A, 3B XV2, 4 XSHT V1A, 1B, 3A, 3B V2, 4 SHT L L X X VH X X L H X X VM X X H L X X Z X X H H X X VL X X X X L X X VM X X X H X X VL X X X X L X X VH X X X H X X VL Z: High impedance X: Don't care Electrical Characteristics (VDD = 3.3V, VH = 15V, VM = GND, VL = –8.5V) DC Characteristics Item Symbol Conditions Min. Typ. Max. Unit "H" level input voltage VIH 0.7VDD — — V "L" level input voltage VIL — — 0.3VDD V Input current IIN –10 0.0 10 µA Operating supply current IH VIN = GND to 5V ∗1 — 0.10 0.20 mA Operating supply current IDD ∗1 — 0.25 0.50 mA Operating supply current IL ∗1 –8.5 –5.5 — mA Output current IOL V1A, 1B, 3A, 3B, V2, 4 = –8.25V 10 — — mA Output current IOM1 V1A, 1B, 3A, 3B, V2, 4 = –0.25V — — –5.0 mA Output current IOM2 V1A, 1B, 3A, 3B = 0.25V 5.0 — — mA Output current IOH V1A, 1B, 3A, 3B = 14.75V — — –7.2 mA Output current IOSL SHT = –8.25V 5.4 — — mA Output current IOSH SHT = 14.75V — — –4.0 mA ∗1 See Measurement Circuit. Shutter speed 1/10000 Note) Current direction +: inflow to IC; –: outflow from IC –3– CXD3400N Switching Characteristics Item (VDD = 3.3V, VH = 15V, VM = GND, VL = –7.5V) Symbol Conditions Min. Typ. Max. Unit Propagation delay time TPLM ∗1 50 70 100 ns Propagation delay time TPMH ∗1 50 70 100 ns Propagation delay time TPLH ∗1 50 70 100 ns Propagation delay time TPML ∗1 10 30 50 ns Propagation delay time TPHM ∗1 10 30 50 ns Propagation delay time TPHL ∗1 10 30 50 ns Rise time TTLM VL → VM∗1 200 350 500 ns Rise time TTMH 200 350 500 ns Rise time TTLH 30 60 90 ns Fall time TTML 200 350 500 ns Fall time TTHM 200 350 500 ns Fall time TTHL 30 60 90 ns Output noise voltage VCLH VH → VL∗1 ∗2 — — 1.0 V Output noise voltage VCLL ∗2 — — 1.0 V Output noise voltage VCMH ∗2 — — 1.0 V Output noise voltage VCML ∗2 — — 1.0 V VM → VH∗1 VL → VH∗1 VM → VL∗1 VH → VM∗1 ∗1 See Switching Waveform. ∗2 See Noise on a Waveform. Note) Each item is evaluated by Measurement Circuit. Notes on Operation (See Application Circuit.) 1. Be sure to protect against static electricity because this IC is MOS structure. 2. A bypass capacitor (0.1µF or more) is connected between GND and near each power supply (VH, VDD, VL). 3. In order to protect CCD image sensor, input SHT pin output to SUB pin of CCD image sensor after that has been clamped at VH. –4– CXD3400N Switching Waveform VDD (3.3V) 50% XV1 to 4 GND VDD (3.3V) 50% XSG1A, 1B, 3A, 3B TPHM TTHM GND TPMH VH TTMH 90% V1A, 1B, 3A, 3B TTLM TTML TPLM TPML 10% VM 90% 10% VL TTLM VM TTML TPLM TPML 90% V2, 4 10% VL VDD (3.3V) XSHT 50% GND VH TTHL TTLH TPLH TPHL 90% SHT 10% VL Noise on a Waveform VCHH VCHL VM VL VCLH VCLL –5– VCHH VCHL CXD3400N Measurement Circuit C1 C1 R1 C2 C2 C1 R1 C2 R1 C2 C2 C2 C2 C2 C2 C2 C1 C2 R1 C2 R1 C2 C1 C2 C2 R2 C1 R1 15V –7.5V 0V Between vertical transfer clock and GND C1 3300pF Capacitance between vertical transfer clocks C2 560pF Capacitance between substrate clock and GND C3 820pF Vertical transfer clock series resistor R1 30Ω Vertical transfer clock ground resistor R2 10Ω C3 20 19 18 17 16 15 14 13 12 11 7 10 CXD3400N 1 2 3 4 5 6 8 9 3.3V Timing Generator –6– CXD3400N Application Circuit 15V 3.3V 0.1µ 2200p 100k 1µ/35V 1 20 2 19 3 18 4 17 V3B 5 16 V3A 6 15 7 14 V1A 8 13 V4 9 12 V2 10 11 0.1µ 1M –7.5V from Timing Generator SUB 0.1µ V1B 0.1µ CCD CXD3400N ∗ See with drive circuit of CCD image sensor. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Note with Power-on Sequence To protect CCD image sensor, rise two power supplies, VL and VH as follows. Note that rise VDD first. VH t1 20% VM 20% t2 VL t2 ≥ t1 –7– CXD3400N Package Outline Unit: mm 20PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗6.5 ± 0.1 0.1 11 20 1 6.4 ± 0.2 ∗4.4 ± 0.1 A 10 0.65 b b=0.22 ± 0.03 0.5 ± 0.2 0.1 ± 0.1 + 0.03 0.15 – 0.01 0.13 M DETAIL B : PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. 0° to 10° PACKAGE STRUCTURE DETAIL A PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-20P-L01 LEAD TREATMENT PALLADIUM PLATING EIAJ CODE SSOP020-P-0044 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.1g JEDEC CODE –8–