DALLAS DS2229

DS2229
Word-Wide 8 Meg SRAM Stik
www.dalsemi.com
FEATURES
1M
SRAM
Organized as a high density 512k x 16 bit
StikTM
Fast access time of 85 ns
Unlimited write cycles
Employs popular JEDEC standard 80-position
SIMM connector
Full ±10% operating range
Read cycle time equals write cycle time
Ultra-low standby current < 10 µA
Suitable for battery-backed applications
1
PIN ASSIGNMENT
1M
SRAM
1M
SRAM
1M
SRAM
80
80-PIN SIP STIK
DESCRIPTION
The DS2229 is an 8,388,608-bit low-power fully static Random Access Memory organized as a 524,888
word by 16 bits using CMOS technology. The device employs the popular JEDEC standard 80-pin SIMM
connection scheme with no additional circuitry required. The device operates from a single power supply
with a voltage input of 4.5 to 5.5 volts. The Chip Enable inputs ( CE0 , CE1 , CE2 , CE3 ) are used for
device selection and can be used in order to achieve the minimum standby current mode which facilitates
battery backup. The device provides a fast access time of 85 ns. The DS2229 maintains TTL levels over
input voltage range 4.5V to 5.5V. The DS2229 is JEDEC pin compatible (see Figure 1) with flash
EEPROM memory SIMM boards of similar density.
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112099
DS2229
PIN DESCRIPTION Figure 1
PIN #
1
2
3
4
5
PIN NAME
GND
VCC
NC
WEH
PIN #
32
33
34
35
36
PIN NAME
NC
NC
NC
NC
A16
PIN #
63
64
65
66
67
PIN NAME
DQ7
DQ6
DQ5
DQ4
DQ3
6
WEL
37
A15
68
DQ2
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NC
CS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
69
70
71
72
73
74
75
76
77
78
79
80
DQ1
DQ0
NC
VCC
NC
GND
NC
GND
GND
NC
NC
GND
CE3
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
22
CE2
53
23
CE1
24
OE
PIN NAME
DESCRIPTION
GND
A0 - A16
Address Input
54
GND
WEL
Write Enable Input Low
CE0
55
DQ15
WEH
Write Enable Input High
25
GND
56
DQ14
OE
Output Enable Input
26
27
NC
NC
57
58
DQ13
DQ12
NC
No Connect
Chip Enable Input
28
29
30
31
NC
NC
NC
NC
59
60
61
62
DQ11
DQ10
DQ9
DQ8
CS
DQ0 - DQ15
VCC
GND
CE0
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- CE3
Chip Select
Data Input/Output
+5 Volts
Ground
DS2229
DS2229 STATIC RAM MODULE FUNCTION DIAGRAM Figure 2
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DS2229
ABSOLUTE MAXIMUM RATINGS*
Power Supply Voltage
Input, Input/Output Voltage
Operating Temperature
Storage Temperature
*
-0.3V to +7.0V
-0.3 to VCC +0.3V
0°C to 70°C
-55°C to +125°C
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATION MODE
MODE
CE0 - CE3
CS
OE
WE
A0 - A16
DQ - DQ15
POWER
READ
L
H
L
H
STABLE
DATA OUT
ICC0
WRITE
L
H
X
L
STABLE
DATA IN
ICC0
DESELECT
L
H
H
H
X
HIGH-Z
ICC0
STANDBY
H
X
X
X
X
HIGH-Z
ICCS1, ICCS2
STANDBY
X
L
X
X
X
HIGH-Z
ICCS1, ICCS2
CAPACITANCE
(tA=25°C)
PARAMETER
Input Capacitance
SYMBOL
CIN
Input/Output Capacitance
MIN
TYP
CI/O
MAX
64
UNITS
pF
80
pF
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
(tA= 0°C to 70°C)
SYMBOL
MIN
TYP
MAX
UNITS
Power Supply Voltage
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.0
VCC+0.3
V
Input Low Voltage
VIL
-0.3
0.8
V
NOTES
(tA= 0°C to 70°C; VCC= 5V ± 10%)
DC CHARACTERISTICS
PARAMETER
Input Leakage Current
NOTES
SYMBOL
IIL
CONDITIONS
MIN
0V ≤ VIN ≤ VCC
MAX
8
UNITS
8
µA
µA
I/O Leakage Current
ILO
Output High Current
IOH
VOH = 2.4V
-1.0
mA
Output Low Current
IOL
VOL = 0.4V
2.1
mA
- CE3 = VIH,
0V ≤ VI/O ≤ VCC
CE0
Standby Current
ICCS1
Standby Current
ICCS2
CE0
Operating Current
ICCO
- CE3 =2.0V tA=25°C
8
mA
- CE3 ≥ VCC -0.3V
tA=25°C
10
µA
- CE3 = 0.8V;
Cycle=100 ns tA=25°C
100
mA
CE0
CE0
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NOTES
9
DS2229
LOW VCC DATA RETENTION CHARACTERISTICS
(tA= 0°C to 70°C)
PARAMETER
VCC for Data Retention
SYMBOL
VDR
MIN
2.0
TYP
-
MAX
-
UNITS
V
TEST CONTIDION
CE0 - CE3 ≥ VCC -0.2V,
CS ≥ VCC -0.2V or 0V
≤ CS ≤ 0.2V VIN ≥ 0V
Data Retention Current
ICCDR
-
1
8
µA
VCC = 3.0V, VIN ≥ 0V
CE0 - CE3 ≥ VCC -0.2V,
CS ≥ VCC -0.2V or 0V ≤
CS ≤ 0.2V tA =25°C
Chip Deselect to Data
Retention Time
tCDR
0
-
-
ns
See Retention
Waveform
tR
5
-
-
ms
Operation Recovery Time
LOW VCC DATA RETENTION TIMING WAVEFORM (1) ( CE0 - CE3 Controlled)
Figure 3
SEE NOTE 5
LOW VCC DATA RETENTION TIMING WAVEFORM (2) (CS Controlled) Figure 4
SEE NOTE 5
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DS2229
PRODUCT CHARACTERISTICS
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DS2229
AC ELECTRICAL CHARACTERISTICS
READ CYCLE
PARAMETER
Read Cycle Time
Access Time
OE
to Output Valid
CE0 - CE3
to Output Valid
SYMBOL
tRC
(0°C to 70°C; VCC = 5V + 10%)
MIN
85
MAX
UNITS
ns
tACC
85
ns
tOE
45
ns
tCO
85
ns
tCOE
10
Output High-Z from Deselection
tOD
0
Output Hold from Address Change
tOH
10
OE
or CE0 - CE3 to Output In Low-Z
AC ELECTRICAL CHARACTERISTICS
WRITE CYCLE
PARAMETER
TYP
30
NOTES
ns
8
ns
8
ns
(0°C to 70°C; VCC = 5V + 10%)
SYMBOL
MIN
Write Cycle Time
tWC
85
ns
Write Pulse Width
tWP
65
ns
Address Setup Time
tAW
0
ns
Write Recovery Time
tWR
10
ns
4
Output High-Z from WE
tODW
0
ns
8
Output Active from WE
tOEW
5
ns
8
Data Setup Time
tDS
35
ns
3
Data Hold Time from WE
tDH
0
ns
3
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TYP
MAX
30
UNITS
NOTES
1
DS2229
READ CYCLE Figure 5
WRITE CYCLE 1 Figure 6
SEE NOTES 1, 3, 4, 6, 7, AND 9
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DS2229
WRITE CYCLE 2 Figure 7
NOTES:
1. A write occurs during the overlap of a low CE0 - CE3 , a high CS, and a low WE . A write begins at the
latest transition among CE0 - CE3 going low, CS going high, and WE going low. A write ends at the
earliest transition among CE0 - CE3 going high, CS going low and WE going high. tWP is measured
from the beginning of write to the end of write.
2. WE is high for a read cycle.
3. tDS ends and tDH begins at the earliest transaction among CE0 - CE3 going high.
4. tWR is measured from the earliest of CE0 - CE3 or WE going high or CS going low to the end of write
cycle.
5. CS controls address buffer, WE buffer, CE0 - CE3 buffer, OE buffer and DIN buffer. If CS controls
data retention mode, VIN levels (address, WE , OE , CE0 - CE3 , I/O) can be in the high impedance state.
If CE0 - CE3 controls data retention mode, CS must be CS ≥ VCC - 0.2V or 0V < CS < 0.2V. The other
input levels (address, WE , OE , I/O) can be in the high impedance state.
6. If CE0 - CE3 goes low simultaneously with WE going low or after WE going low, the outputs remain
in a high impedance state.
7. If CE0 - CE3 is low and CS is high during this period, I/O pins are in the output state. Therefore, the
input signals of the opposite phase to the outputs must not be applied to them.
8. This parameter is sampled and not 100% tested.
9. Only one CE active during any read or write cycle.
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DS2229
DS2229 80-PIN SIP STIK
PKG
80-PIN
DIM
MIN
MAX
A
4.645
4.655
B
4.379
4.389
C
0.729
0.739
D
0.395
0.405
E
0.245
0.255
F
0.050 BSC
G
0.075
0.085
H
0.245
0.255
I
J
1.950 BSC
0.120
0.130
K
2.320
2.330
L
2.445
2.455
M
0.057
0.067
N
0.130
O
0.130
P
0.054
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