19-0849; Rev 0; 7/07 10-Bit LVDS Serializer Applications Lane Departures Security Cameras Rear View Cameras Production Line Monitoring Features ♦ Stand-Alone Serializer (vs. SERDES) Ideal for Unidirectional Links ♦ Framing Bits for Deserializer Resync Allow Hot Insertion Without System Interruption ♦ LVDS Serial Output Rated for Point-to-Point Applications ♦ Wide Reference Clock Input Range 16MHz to 40MHz ♦ Low 31mA Supply Current ♦ 10-Bit Parallel LVCMOS/LVTTL Interface ♦ Up to 400Mbps Payload Data Rate ♦ Small 16-Pin TQFN (3mm x 3mm) Package Ordering Information PINPACKAGE REF CLOCK RANGE (MHz) PKG CODE 16 TQFN-EP* 16 to 40 TI633-5 PART MAX9235ETE+ +Denotes a lead-free package. Note: The device is specified over the -40°C to +105°C temperature range. *EP = Exposed pad. Pin Configuration and Functional Diagram appear at end of data sheet. TCLK PLL LVDS 100Ω IN+ 100Ω OUT- INPCB OR TWISTED PAIR 10 OUT_ REFCLK TIMING AND CONTROL MAX9235 OUTPUT LATCH OUT+ SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL 10 IN_ INPUT LATCH Typical Application Circuit PLL MAX9206 TIMING AND CONTROL CLOCK RECOVERY EN LOCK RCLK RCLK_R/F ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9235 General Description The MAX9235 serializer transforms 10-bit-wide parallel LVCMOS/LVTTL data into a serial high-speed, low-voltage differential signaling (LVDS) data stream. The serializer typically pairs with deserializers like the MAX9206, which receives the serial output and transforms it back to 10-bit-wide parallel data. The MAX9235 transmits serial data at speeds up to 400Mbps over PCB traces or twisted-pair cables. Since the clock is recovered from the serial data stream, clock-to-data and data-to-data skew that would be present with a parallel bus are eliminated. The MAX9235 serializer requires no external components and no control signals and can lock to a 16MHz to 40MHz system clock. The serializer output is held in high impedance until the device is fully locked to the local system clock. The MAX9235 operates from a single +3.3V supply, is specified for operation from -40°C to +105°C, and is available in a 16-pin TQFN (3mm x 3mm) package. MAX9235 10-Bit LVDS Serializer ABSOLUTE MAXIMUM RATINGS Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Operating Temperature Range .........................-40°C to +105°C Lead Temperature (soldering, 10s) .................................+300°C ESD Protection (Human Body Model, OUT+, OUT-) ...........±8kV ESD Protection (Human Body Model, IN_, TCLK) ...............±2kV VCC to GND .........................................……………-0.3V to +4.0V IN_, TCLK to GND ......................................-0.3V to (VCC + 0.3V) OUT+, OUT- to GND .............................................-0.3V to +4.0V Output Short-Circuit Duration.....................................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TQFN (derate 14.7mW/°C above +70°C) ......1177mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 50Ω ±1%, CL = 10pF, TA = -40°C to +105°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC V LVCMOS/LVTLL LOGIC INPUTS (IN0 TO IN9, EN, TCLK) High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Current LVDS OUTPUTS (OUT+, OUT-) IIN Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States 2.0 VIN_ = 0 or VCC VOD Figure 1 ΔVOD Figure 1 VOS Figure 1 ΔVOS Figure 1 GND 0.8 V -20 +20 µA RL = 100Ω 600 735 950 RL = 50Ω 250 370 470 1 35 mV mV RL = 100Ω 1.025 1.265 1.375 RL = 50Ω 1.125 1.265 1.375 3 35 mV -13 -15 mA +10 µA Output Short-Circuit Current IOS OUT+ or OUT- = 0, IN0 to IN9 = EN = high Power-Off Output Current IOX VCC = 0, OUT+ or OUT- = 0 or 3.6V ICC RL = 100Ω or 50Ω worst-case pattern (Figures 2, 4) -10 V POWER SUPPLY Supply Current 2 16MHz 22 35 40MHz 31 45 mA _______________________________________________________________________________________ 10-Bit LVDS Serializer (VCC = +3.0V to +3.6V, RL = 50Ω ±1%, CL = 5pF, TA = -40°C to +105°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRANSMIT CLOCK (TCLK) TIMING REQUIREMENTS TCLK Center Frequency fTCCF 16 40 MHz TCLK Frequency Variation TCFV -200 +200 ppm TCLK Period tTCP 25 62.5 ns TCLK Duty Cycle TCDC TCLK Input Transition Time tCLKT TCLK Input Jitter 40 Figure 3 3 tJIT 60 % 6 ns 150 ps (RMS) SWITCHING CHARACTERISTICS RL = 100Ω 370 500 RL = 50Ω 350 500 RL = 100Ω 370 500 RL = 50Ω 350 500 Low-to-High Transition Time tLHT Figure 4 High-to-Low Transition Time tHLT Figure 4 IN_ Setup to TCLK tS Figure 5 IN_ Hold from TCLK tH Figure 5 3 Figure 6 2048 x tTCP PLL Lock Time tPL Bus LVDS Bit Width tBIT Serializer Delay tSD 1 tTCP / 6 ps ns ns 2049 x tTCP tTCP / 12 Figure 7 ps ns ns (tTCP / 6) +5 ns Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and VOS. Note 2: CL includes scope probe and test jig capacitance. Note 3: Parameters 100% tested at TA = +25°C. Limits over operating temperature range guaranteed by design and characterization. Note 4: AC parameters are guaranteed by design and characterization. _______________________________________________________________________________________ 3 MAX9235 AC ELECTRICAL CHARACTERISTICS MAX9235 10-Bit LVDS Serializer RL 2 OUT+ TCLK VOD VOS ODD IN_ RL 2 OUT- EVEN IN_ Figure 1. Output Voltage Definitions Figure 2. Worst-Case ICC Test Pattern 3V 90% 90% TCLK 10% 10% tCLKT 0 tCLKT Figure 3. Input Clock Transition Time Requirement 5pF OUT+ 80% 80% VDIFF = 0 RL 20% VDIFF 20% OUT5pF tLHT tHLT VDIFF = (OUT+) - (OUT-) Figure 4. Output Load and Transition Times tTCP 1.5V TCLK tS IN_ 1.5V 1.5V 1.5V tH 1.5V Figure 5. Data Input Setup and Hold Times 4 _______________________________________________________________________________________ 10-Bit LVDS Serializer 2.5V MAX9235 VCC 2.5V tPL TCLK OUT± ACTIVE HIGH IMPEDANCE HIGH IMPEDANCE Figure 6. PLL Lock Time IN IN0–IN9 SYMBOL N + 1 IN0–IN9 SYMBOL N tSD TCLK 1.5V START BIT OUT0–OUT9 SYMBOL N STOP BIT START BIT OUT0–OUT9 SYMBOL N + 1 STOP BIT OUT± VDIFF = 0 VDIFF = (OUT+) - (OUT-) Figure 7. Serializer Delay _______________________________________________________________________________________ 5 Typical Operating Characteristics (VCC = +3.3V, RL = 50Ω, CL = 5pF, TA = +25°C, unless otherwise noted.) WORST-CASE PATTERN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX9205 toc01 34 33 SUPPLY CURRENT (mA) MAX9235 10-Bit LVDS Serializer 32 31 30 29 TCLK = 40MHz 28 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) PIN NAME 1–7, 14, 15, 16 IN3–IN9, IN0, IN1, IN2 8 TCLK LVCMOS/LVTTL Reference Clock Input. Accepts a 16MHz to 40MHz clock. TCLK provides a frequency reference to the PLL and strobes parallel data into the input latch on the rising edge. 9, 12 GND Ground 10 OUT- Inverting Bus LVDS Differential Output 11 OUT+ Noninverting Bus LVDS Differential Output 13 VCC — EP 6 FUNCTION LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the rising TCLK edge. Each input is internally pulled to ground. Power-Supply Input. Bypass to ground with a 0.1µF capacitor and a 0.001µF capacitor. Place the 0.001µF capacitor closest to VCC. Exposed Pad. Solder EP to ground for improved heat dissipation. _______________________________________________________________________________________ 10-Bit LVDS Serializer The MAX9235 10-bit serializer transmits data over balanced media that may be a standard twisted-pair cable or PCB traces at 100Mbps to 400Mbps. The interface may be single- or double-terminated point-to-point. A double-terminated point-to-point interface uses a 100Ωtermination resistor at each end of the interface, resulting in a 50Ω load. The serializer requires a deserializer such as the MAX9206 for a complete data transmission application. A high-state start bit and a low-state stop bit, added internally, frame the 10-bit parallel input data and ensure a transition in the serial data stream. Therefore, 12 serial bits are transmitted for each 10-bit parallel input. The MAX9235 accepts a 16MHz to 40MHz reference clock, producing a serial data rate of 192Mbps (12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). Since only 10 bits are from input data, the actual throughput is 10 times the TCLK frequency. To transmit data, the serializer sequences through two modes: initialization mode and data transmission mode. Initialization Mode When V CC is applied, the outputs are held in high impedance and internal circuitry is disabled by on-chip power-on-reset circuitry. When VCC reaches 2.35V, the PLL starts to lock to a local reference clock. The reference clock, TCLK, is provided by the system. The serializer locks within 2049 cycles of TCLK. Once locked, the serializer is ready to send data. Data Transmission Mode After initialization, input data at IN0–IN9 are clocked into the serializer by the TCLK input. Data strobes on the rising edge of TCLK. A start bit high and a stop bit low frame the 10-bit data and function as the embedded clock edge in the serial data stream. The serial rate is the TCLK frequency times the data and appended bits. For example, if TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) = 480Mbps. Since only 10 bits are from input data, the payload rate is 40 x 10 = 400Mbps. High-Impedance State The serializer output pins (OUT+ and OUT-) are held in high impedance when VCC is first applied and while the PLL is locking to the local reference clock. If the serializer goes into high impedance, the deserializer loses PLL lock and needs to reestablish phase lock before data transfer can resume. This is done by transmitting all zeroes for at least one frame. Applications Information Power-Supply Bypassing Bypass VCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. Differential Traces and Termination Use controlled-impedance media and terminate at both ends of the transmission line in the media's characteristic impedance. Termination with a single resistor at the end of a point-to-point link typically provides acceptable performance. The MAX9235 output levels are specified for double-terminated point-to-point applications. With a single 100Ω termination, the output swing is larger. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. The differential output signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. _______________________________________________________________________________________ 7 MAX9235 Detailed Description MAX9235 10-Bit LVDS Serializer used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Topologies The MAX9235 can operate in point-to-point or broadcast topologies. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections. Since repeater jitter subtracts from the serializer-deserializer timing margin, a low-jitter repeater is essential in most high data rate applications. A point-to-point connection terminated at each end in the characteristic impedance of the cable or PCB traces is shown in Figure 8. The total load seen by the serializer is 50Ω. The double termination typically reduces reflections compared to a single 100Ω termination. A single 100Ω termination at the deserializer input is feasible and will make the differential signal swing larger. Board Layout For LVDS applications, a four-layer PCB that provides separate power, ground, and input/output signals is recommended. Separate LVTTL/LVCMOS and LVDS signals from each other to prevent coupling into the LVDS lines. A point-to-point broadcast configuration is shown in Figure 9. The low-jitter MAX9150 10-port repeater is SERIALIZED DATA PARALLEL DATA IN 100Ω PARALLEL DATA OUT 100Ω MAX9235 MAX9206 Figure 8. Double-Terminated Point-to-Point ASIC ASIC ASIC MAX9206 MAX9206 MAX9235 100Ω 100Ω 100Ω MAX9150 REPEATER 100Ω 100Ω 100Ω Figure 9. Point-to-Point Broadcast Using MAX9150 Repeater 8 _______________________________________________________________________________________ 10-Bit LVDS Serializer 10 OUT+ GND OUT+ OUT- GND PARALLEL-TO-SERIAL IN_ INPUT LATCH TOP VIEW 12 11 10 9 VCC 13 8 TCLK IN0 14 7 IN9 6 IN8 5 IN7 OUT- MAX9235 IN1 15 TCLK IN3 1 MAX9235 2 3 4 IN6 + IN5 TIMING AND CONTROL IN4 IN2 16 PLL THIN QFN 3mm x 3mm Chip Information PROCESS: CMOS _______________________________________________________________________________________ 9 MAX9235 Pin Configuration Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) (NE - 1) X e E MARKING 12x16L QFN THIN.EPS MAX9235 10-Bit LVDS Serializer E/2 D2/2 (ND - 1) X e D/2 AAAA e CL D D2 k CL b 0.10 M C A B E2/2 L E2 0.10 C C L 0.08 C C L A A2 A1 L L e e PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 10 ______________________________________________________________________________________ I 1 2 10-Bit LVDS Serializer PKG 8L 3x3 12L 3x3 REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 b 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 D 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 E 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 e L 0.55 0.75 0.45 0.55 0.65 0.30 0.40 N 8 12 16 ND 2 3 4 NE 2 3 4 0 A1 A2 k 0.02 0.05 0 0.20 REF 0.25 - 0.02 0.05 0 0.20 REF - 0.25 - EXPOSED PAD VARIATIONS 0.50 BSC. 0.50 BSC. 0.65 BSC. 0.35 16L 3x3 0.02 0.50 0.05 0.20 REF - 0.25 - PKG. CODES E2 D2 MIN. NOM. MAX. MIN. NOM. MAX. PIN ID JEDEC TQ833-1 0.25 0.70 1.25 0.25 0.70 1.25 0.35 x 45° T1233-1 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEEC WEED-1 T1233-3 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1 WEED-1 T1233-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° T1633-2 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 T1633F-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2 T1633FH-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2 T1633-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 T1633-5 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 - NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm. PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 I 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX9235 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)