19-1477; Rev 0; 4/99 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output The MAX5175/MAX5177 low-power, serial, voltage-output, 12-bit digital-to-analog converters (DACs) feature a precision output amplifier in a space-saving 16-pin QSOP package. The MAX5175 operates from a single +5V supply, and the MAX5177 operates from a single +3V supply. The output amplifier’s inverting input is available to allow specific gain configurations, remote sensing, and high output current capability. This makes the MAX5175/MAX5177 ideal for a wide range of applications, including industrial process control. Both devices draw only 260µA of supply current, which reduces to 1µA in shutdown mode. In addition, the programmable power-up reset feature allows for a userselectable output voltage state of either 0 or midscale. The 3-wire serial interface is compatible with SPI™, QSPI™, and MICROWIRE™ standards. An input register followed by a DAC register provides a double-buffered input, allowing the registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include software and hardware shutdown, shutdown lockout, a hardware reset pin, and a reference input capable of accepting DC and offset AC signals. These devices provide a programmable digital output pin for added functionality and a serial-data output pin for daisy-chaining. All logic inputs are TTL/CMOS compatible and are internally buffered with Schmitt triggers to allow direct interfacing to optocouplers. The MAX5175/MAX5177 incorporate a proprietary on-chip circuit that keeps the output voltage virtually “glitch free,” limiting the glitches to a few millivolts during power-up. Both devices come in 16-pin QSOP packages and are specified for the extended (-40°C to +85°C) temperature range. The MAX5171/MAX5173 are 14-bit pin-compatible upgrades to the MAX5175/MAX5177. For pin-compatible DACs with an internal reference, see the 13-bit MAX5132/MAX5133 and 12-bit MAX5122/MAX5123. Features ♦ ±1 LSB INL ♦ 1µA Shutdown Current ♦ “Glitch Free” Output Voltage at Power-Up ♦ Single-Supply Operation +5V (MAX5175) +3V (MAX5177) ♦ Full-Scale Output Range +2.048V (MAX5177, VREF = +1.25V) +4.096V (MAX5175, VREF = +2.5V) ♦ Rail-to-Rail® Output Amplifier ♦ Adjustable Output Offset ♦ Low THD (-80dB) in Multiplying Operation ♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface ♦ Programmable Shutdown Mode and Power-Up Reset (0 or midscale) ♦ Buffered Output Capable of Driving 4–20mA or 5kΩ || 100pF Loads ♦ User-Programmable Digital Output Pin Allows Serial Control of External Components ♦ 14-Bit Upgrades Available (MAX5171/MAX5173) Ordering Information TEMP. RANGE PIN-PACKAGE MAX5175AEEE -40°C to +85°C 16 QSOP ±1 MAX5175BEEE MAX5177AEEE MAX5177BEEE -40°C to +85°C -40°C to +85°C -40°C to +85°C 16 QSOP 16 QSOP 16 QSOP ±2 ±2 ±4 Pin Configuration Applications Digitally Programmable 4–20mA Current Loops Industrial Process Controls Digital Offset and Gain Adjustment Motion Control Automatic Test Equipment (ATE) Remote Industrial Controls µP-Controlled Systems Functional Diagram appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. INL (LSB) PART TOP VIEW FB 1 16 VDD OUT 2 15 N.C. RS 3 14 REF PDL 4 CLR 5 MAX5175 MAX5177 13 AGND 12 SHDN CS 6 11 UPO DIN 7 10 DOUT SCLK 8 9 DGND QSOP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5175/MAX5177 General Description MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) FB, OUT REF to AGND...............................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8mW/°C above +70°C)...............667mW Operating Temperature Range .............................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX5175 (VDD = +5V ±10%, VREF = 2.5V, AGND = DGND, FB = OUT, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 Integral Nonlinearity (Note 1) INL Differential Nonlinearity DNL Offset Error (Note 2) VOS Gain Error Power-Supply Rejection Ratio GE ±1 MAX5175B ±2 ±1 mV LSB LSB RL = 5kΩ -1.6 ±8 10 120 Output Thermal Noise Density LSB ±4 -0.6 f = 100kHz LSB ±10 RL = ∞ PSRR Output Noise Voltage Bits MAX5175A µV/V 1 LSBp-p 50 nV/√Hz REFERENCE INPUT Reference Input Range VREF 0 Reference Input Resistance RREF 18 VDD - 1.4 V kΩ MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth VREF = 0.5Vp-p + 2.5VDC, slew-rate limited 350 kHz Reference Feedthrough VREF = 3.6Vp-p + 1.8VDC, f = 1kHz, code = all 0s -84 dB VREF = 1.4Vp-p + 2.5VDC, f = 10kHz, code = FFF hex 84 dB Signal-to-Noise Plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 3 VHYS Input Leakage Current IIN Input Capacitance CIN V 0.8 200 VIN = 0 or VDD 0.001 V mV ±1 8 µA pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 2 VDD - 0.5 V 0.13 _______________________________________________________________________________________ 0.4 V Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output (VDD = +5V ±10%, VREF = 2.5V, AGND = DGND, FB = OUT, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time 0.6 To ±0.5LSB, from 10mV to full-scale Output Voltage Swing (Note 3) 0 Current into FB -0.1 Time Required to Exit Shutdown CS = VDD; fSCLK = 100kHz, VSCLK = 5Vp-p Digital Feedthrough V/µs 12 0 µs VDD V 0.1 µA 40 µs 1 nV-s POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current (Note 4) IDD 4.5 Shutdown Current (Note 4) 5.5 V 0.26 0.35 mA 1 10 µA TIMING CHARACTERISTICS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SDI Setup Time tDS 40 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 80 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 80 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 40 ns CS Pulse Width High tCSW 100 ns _______________________________________________________________________________________ 3 MAX5175/MAX5177 ELECTRICAL CHARACTERISTICS—MAX5175 (continued) MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output ELECTRICAL CHARACTERISTICS—MAX5177 (VDD = +2.7V to +3.6V, VREF = 1.25V, AGND = DGND, FB = OUT, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 Bits MAX5177A ±2 MAX5177B ±4 Integral Nonlinearity (Note 5) INL Differential Nonlinearity DNL ±1 Offset Error (Note 2) VOS ±10 mV LSB LSB Gain Error Power-Supply Rejection Ratio GE RL = ∞ -0.6 ±4 RL = 5kΩ -1.6 ±8 10 120 PSRR Output Noise Voltage f = 100kHz Output Thermal Noise Density LSB LSB µV/V 2 LSBp-p 50 nV/√Hz REFERENCE Reference Input Range VREF 0 Reference Input Resistance RREF 18 VDD - 1.4 V kΩ MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth VREF = 0.5Vp-p + 1.25VDC, slew-rate limited 350 kHz Reference Feedthrough VREF = 1.6Vp-p + 0.8VDC, f = 1kHz, code = all 0s -84 dB VREF = 0.9Vp-p + 1.25VDC, f = 10kHz, code = FFF hex 78 dB Signal-to-Noise Plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis VIH 2.2 V VIL 0.8 VHYS Input Leakage Current IIN Input Capacitance CIN 200 VIN = 0 or VDD 0.001 V mV ±1 8 µA pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 4 VDD - 0.5 V 0.13 _______________________________________________________________________________________ 0.4 V Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output (VDD = +2.7V to +3.6V, VREF = 1.25V, AGND = DGND, FB = OUT, RL = 5kΩ, CL = 100pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time 0.6 To ±0.5LSB, from 10mV to full-scale Output Voltage Swing (Note 3) 0 Current into FB -0.1 Time Required to Exit Shutdown CS = VDD, DIN = 50kHz, fSCLK = 100kHz, VSCLK = 3Vp-p Digital Feedthrough V/µs 12 0 µs VDD V 0.1 µA 40 µs 1 nV-s POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current (Note 4) IDD 2.7 Shutdown Current (Note 4) 3.6 V 0.26 0.35 mA 1 10 µA TIMING CHARACTERISTICS SCLK Clock Period tCP 150 ns SCLK Pulse Width High tCH 75 ns SCLK Pulse Width Low tCL 75 ns CS Fall to SCLK Rise Setup Time tCSS 60 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SDI Setup Time tDS 60 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 200 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 200 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 75 ns CS Pulse Width High tCSW 150 ns Note 1: Note 2: Note 3: Note 4: Note 5: INL guaranteed between codes 16 and 4095. Offset is measured at the code that comes closest to 10mV. Accuracy is better than 1LSB for VOUT = 10mV to VDD - 180mV. Guaranteed by PSR test on end points. RL = open and digital inputs are either VDD or DGND. INL guaranteed between codes 32 and 4095. _______________________________________________________________________________________ 5 MAX5175/MAX5177 ELECTRICAL CHARACTERISTICS—MAX5177 (continued) Typical Operating Characteristics (MAX5175: VDD = +5V, VREF = 2.5V; MAX5177: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = FFF hex, TA = +25°C, unless otherwise noted.) MAX5175 280 270 260 250 240 230 262 260 258 256 254 252 MAX5175-03 264 1.4 SHUTDOWN SUPPLY CURRENT (µA) 290 266 MAX5175-02 1.3 1.2 1.1 1.0 0.9 250 220 210 0.8 248 4.4 4.6 4.8 5.0 5.2 5.4 5.6 -50 -30 -10 OUTPUT VOLTAGE vs. TEMPERATURE OUTPUT VOLTAGE (V) -50 90 -30 -10 10 30 50 TEMPERATURE (°C) OUTPUT VOLTAGE vs. LOAD RESISTANCE DYNAMIC RESPONSE 70 90 MAX5175-06 2.5 2.49934 2.49930 -50 70 MAX5175-05 MAX5175-04 2.49938 50 3.0 2.49946 2.49942 30 TEMPERATURE (°C) SUPPLY VOLTAGE (V) 2.49950 10 5V VCS (5V/div) 0 2.0 1.5 2.5V VOUT (1V/div) 1.0 0.5 10mV 0 -30 -10 10 30 50 TEMPERATURE (°C) 70 90 10 1k 10k 2µs/div 100k RL (Ω) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY DYNAMIC RESPONSE MAX5175-07 -80 2.5V VOUT (1V/div) THD + NOISE (dB) 0 REFERENCE FEEDTHROUGH MAX5175-08 -78 5V VCS (5V/div) 100 0 VREF = 1.8VDC + 3.6Vp-p at f = 1kHz VOUT/VREF (12.5dB/div) MAX5175 toc9 NO-LOAD SUPPLY CURRENT (µA) 300 NO-LOAD SUPPLY CURRENT (µA) MAX5175-01 310 -82 -84 -86 -88 10mV -90 -92 2µs/div 10 100 1k FREQUENCY (Hz) 6 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT VOLTAGE (V) MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output 10k 100k 20 FREQUENCY (Hz) _______________________________________________________________________________________ 10k Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output MAX5175 FFT PLOT MAJOR-CARRY TRANSITION DIGITAL FEEDTHROUGH VREF = 2.5 VDC + 1.414Vp-p at f = 10kHz VOUT/VREF (12.5dB/div) MAX5175 toc10 MAX5175-11 0 MAX5175-12 VCS (2V/div) VOUT (2mV/div) VOUT (100mV/div) V/SCLK (5V/div) 20 100k FREQUENCY (Hz) 400ns/div AC-COUPLED START-UP GLITCH REFERENCE INPUT FREQUENCY RESPONSE MAX5175-14 MAX5175-13 0 GAIN (dB) -5 VDD (1V/div) -10 -15 VOUT (10mV/div) -20 VREF = 0.67Vp-p + 1.25VDC -25 0 500 1000 1500 2000 2500 50ms/div 3000 AC-COUPLED FREQUENCY (kHz) MAX5177 265 260 255 250 245 240 264 262 260 258 256 254 235 230 SUPPLY VOLTAGE (V) 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 252 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 MAX5175-17 266 0.60 SHUTDOWN SUPPLY CURRENT (µA) 270 268 MAX5175-16 NO-LOAD SUPPLY CURRENT (µA) 275 NO-LOAD SUPPLY CURRENT (µA) MAX5175-15 280 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. TEMPERATURE NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE -50 -30 -10 10 30 50 TEMPERATURE (°C) 70 90 -50 -30 -10 10 30 50 70 90 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX5175/MAX5177 Typical Operating Characteristics (continued) (MAX5175: VDD = +5V, VREF = 2.5V; MAX5177: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = FFF hex, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (MAX5175: VDD = +5V, VREF = 2.5V; MAX5177: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = FFF hex, TA = +25°C, unless otherwise noted.) MAX5177 OUTPUT VOLTAGE vs. TEMPERATURE OUTPUT VOLTAGE vs. RESISTANCE LOAD MAX5175-19 1.2 OUTPUT VOLTAGE (V) 1.24970 1.24960 1.24950 DYNAMIC RESPONSE MAX5175-20 1.4 MAX5175-18 1.24980 OUTPUT VOLTAGE (V) 3V VCS (3V/div) 0 1.0 0.8 0.6 1.25V VOUT (500mV/div) 0.4 1.24940 0.2 1.24930 10mV 0 -30 -10 10 30 50 70 90 10 100 TEMPERATURE (°C) 1k 10k 100k 2µs/div RL (Ω) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY DYNAMIC RESPONSE MAX5175-21 -74 0 -76 1.25V VOUT (500mV/div) REFERENCE FEEDTHROUGH MAX5175-22 3V THD + NOISE (dB) VCS (3V/div) -72 0 VREF = 0.8VDC + 1.6Vp-p at f = 1kHz VOUT/VREF (12.5dB/div) MAX5175 toc23 -50 -78 -80 -82 -84 10mV -86 -88 10 2µs/div 100 1k 10k 20 100k FREQUENCY (Hz) 10k FREQUENCY (Hz) DIGITAL FEEDTHROUGH (SCLK, OUT) MAX5175/77 toc25 VREF = 1.5VDC + 0.848Vp-p at f = 10kHz MAJOR-CARRY TRANSITION VCS (2V/div) MAX5175/77 toc26 FFT PLOT 0 MAX5175 toc24 MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output SCLK (2V/div) VOUT/VREF (12.5dB/div) VOUT (100mV/div) 20 8 FREQUENCY (Hz) OUT (500µV/div) 100k AC-COUPLED 5µs/div 2µs/div AC-COUPLED _______________________________________________________________________________________ Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output MAX5177 REFERENCE INPUT FREQUENCY RESPONSE START-UP GLITCH MAX5175-28 MAX5175-27 0 GAIN (dB) -5 VDD (1V/div) -10 -15 VOUT (10mV/div) AC-COUPLED -20 VREF = 0.67Vp-p + 1.25VDC -25 0 500 1000 1500 2000 2500 3000 50ms/div FREQUENCY (kHz) Pin Description PIN NAME FUNCTION 1 FB 2 OUT 3 RS Reset Mode Select (digital input). Connect to VDD to select midscale reset output value. Connect to DGND to select 0 reset output value. 4 PDL Power-Down Lockout (digital input). Connect to VDD to allow shutdown. Connect to DGND to disable shutdown. 5 CLR Clear DAC (digital input). Clears the DAC to its predetermined output state as set by RS. 6 CS Chip-Select Input (digital input). DIN is ignored when CS is high. 7 DIN Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK. 8 SCLK Serial Clock Input (digital input) 9 DGND Digital Ground 10 DOUT Serial-Data Output 11 UPO 12 SHDN Shutdown (digital input). Pulling SHDN high when PDL = VDD places the chip in shutdown with a maximum shutdown current of 10µA. 13 AGND Analog Ground 14 REF Reference Input. Maximum VREF is VDD - 1.4V. 15 N.C. No Connect 16 VDD Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a 0.1µF capacitor. Feedback Input Voltage Output. High impedance in shutdown. Output voltage is limited to VDD. User-Programmable Output. State is set by the serial input. _______________________________________________________________________________________ 9 MAX5175/MAX5177 Typical Operating Characteristics (continued) (MAX5175: VDD = +5V, VREF = 2.5V; MAX5177: VDD = +3V, VREF = 1.25V; CL = 100pF, FB = OUT, code = FFF hex, TA = +25°C, unless otherwise noted.) MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output Detailed Description FB The MAX5175/MAX5177 12-bit, serial, voltage-output DACs operate with a 3-wire serial interface. These devices include a 16-bit shift register and a doublebuffered input composed of an input register and a DAC register (see Functional Diagram). In addition, the negative terminal of the output amplifier is available. The DACs are designed with an inverted R-2R ladder network (Figure 1) that produces a weighted voltage proportional to the reference voltage. Reference Inputs The reference input accepts both AC and DC values with a voltage range extending from 0 to VDD - 1.4V. The following equation represents the resulting output voltage: VOUT = VREF ⋅ N ⋅ GAIN 4096 where N is the numeric value of the DAC’s binary input code (0 to 4095), VREF is the reference voltage, and Gain is the externally set voltage gain. The maximum output voltage is VDD. The reference pin has a minimum impedance of 18kΩ and is code dependent. Output Amplifier The MAX5175/MAX5177’s DAC output is internally buffered by a precision amplifier with a typical slew rate of 0.6V/µs. Access to the output amplifier’s inverting input provides flexibility in output gain setting and signal conditioning (see Applications Information). The output amplifier settles to ±0.5LSB from a full-scale transition within 12µs, when loaded with 5kΩ in parallel with 100pF. Loads less than 2kΩ degrade performance. Shutdown Mode The MAX5175/MAX5177 feature a software- and hardware-programmable shutdown mode that reduces the typical supply current to 1µA. Enter shutdown by writing the appropriate input-control word as shown in Table 1 or by using the hardware shutdown function. In shutdown mode, the reference input and the amplifier output become high impedance and the serial interface remains active. Data in the input register is saved, allowing the MAX5175/MAX5177 to recall the prior output state when returning to normal operation. Exit shutdown by reloading the DAC register from the shift register, by simultaneously loading the input and DAC registers, or by toggling PDL. When returning from shutdown, wait 40µs for the output to settle. 10 R 2R 2R R 2R OUT R 2R 2R MSB REF AGND SHOWN FOR ALL 1s ON DAC Figure 1. Simplified DAC Circuit Diagram Power-Down Lockout Power-down lockout disables the software/hardware shutdown mode. A high-to-low transition on PDL brings the device out of shutdown, returning the output to its previous state. Shutdown Pulling SHDN high while PDL is high places the MAX5175/MAX5177 in shutdown. Pulling SHDN low does not take the device out of shutdown. A high-to-low transition on PDL or an appropriate command from the serial data line (see Table 1 for commands) is required to exit shutdown. Serial Interface The 3-wire serial interface is compatible with SPI, QSPI (Figure 2), and MICROWIRE (Figure 3) interface standards. The 16-bit serial input word consists of two control bits, 12 bits of data (MSB to LSB), and two sub-bits. The control bits determine the MAX5175/MAX5177’s response as outlined in Table 1. The digital inputs are double buffered, which allows any of the following: • Loading the input register without updating the DAC register • Updating the DAC register from the input register • Updating the input and DAC registers simultaneously. ______________________________________________________________________________________ Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output • Clock edge on which serial data output (DOUT) is clocked out • State of the user-programmable logic output • Reset state. Specific commands for setting these are shown in Table 1. The general timing diagram in Figure 4 illustrates how the MAX5175/MAX5177 acquire data. CS must go low at least tCSS before the rising edge of the serial clock (SCLK). With CS low, data is clocked into the register on the rising edge of SCLK. The maximum serial clock frequency guaranteed for proper operation is 10MHz for the MAX5175 and 6MHz for the MAX5177. See Figure 5 for a detailed timing diagram of the serial interface. Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION C1 C0 D11..................D0 S1, S0 0 0 12-bit DAC data 00 Load input register; DAC registers are unchanged. 0 1 12-bit DAC data 00 Load input register; DAC registers are updated (start up DAC with new data). 1 0 xxxx xxxx xxxx xx Update DAC register from input register (start up DAC with data previously stored in the input registers). 1 1 0 0 x x xxxx xxxx xx No operation (NOP). 1 1 0 1 x x xxxx xxxx xx Shut down DAC (provided PDL = 1). 1 1 1 0 0 x xxxx xxxx xx UPO goes low (default). 1 1 1 0 1 x xxxx xxxx xx UPO goes high. 1 1 1 1 0 x xxxx xxxx xx Mode 1, DOUT clocked out on SCLK’s rising edge. 1 1 1 1 1 x xxxx xxxx xx Mode 0, DOUT clocked out on SCLK’s falling edge (default). +5V SS DIN MAX5175 MAX5177 SCLK CS MOSI SCK MICROWIRE PORT MAX5175 MAX5177 SCLK SK DIN SO CS I/O SPI/QSPI PORT I/O CPOL = 0, CPHA = 0 CPOL = 0, CPHA = 0 Figure 2. Connections for SPI/QSPI Standards Figure 3. Connections for MICROWIRE ______________________________________________________________________________________ 11 MAX5175/MAX5177 The MAX5175/MAX5177 accept one 16-bit packet or two 8-bit packets sent while CS remains low. The devices allow the following to be configured: MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output CS COMMAND EXECUTED SCLK 1 DIN C2 8 C1 C0 D9 D8 D7 D6 D5 9 D4 16 D3 D2 D1 D0 S2 S1 S0 Figure 4. Serial-Interface Timing Diagram tCSW CS tCSO tCSS tCSH tCS1 SCLK tCH tCL tCP DIN tDS tD01 tD02 tDH DOUT Figure 5. Detailed Serial-Interface Timing Diagram Serial-Data Output (DOUT) The serial-data output (DOUT) is the internal shift register’s output and allows for daisy-chaining of multiple devices as well as data readback (see Applications Information). By default upon start-up, data shifts out of DOUT on the serial clock’s rising edge (Mode 0) and provides a lag of 16 clock cycles, thus maintaining SPI, QSPI, and MICROWIRE compatibility. However, if the device is programmed for Mode 1, then the output data lags DIN by 16.5 clock cycles and is clocked out on the serial clock’s rising edge. During shutdown, DOUT retains its last digital state prior to shutdown. When CLR is pulled low, UPO will reset to its programmed default state. See Table 1 for specific commands to control the UPO. Reset (RS) and Clear (CLR) The MAX5175/MAX5177 offers a clear pin (CLR) which resets the output voltage. If RST = DGND, then CLR resets the output voltage to the minimum voltage (0 if no offset is introduced). If RST = VDD, then CLR resets the output voltage to midscale. In either case, CLR will reset UPO to its programmed default state. User-Programmable Logic Output (UPO) The UPO allows control of an external device through the serial interface, thereby reducing the number of microcontroller I/O pins required. During power-down, this output will retain its digital state prior to shutdown. 12 ______________________________________________________________________________________ Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output Unipolar Output Figure 6 shows the MAX5175/MAX5177 configured for unipolar, rail-to-rail operation with a gain of +2V/V. Table 2 lists the codes for unipolar output voltages. The output voltage is limited to VDD. Bipolar Output Figure 7 shows the MAX5175/MAX5177 configured for bipolar output operation. The output voltage is given by the following equation (FB = OUT): 2N VOUT = VREF − 1 4096 where N represents the numeric value of the DAC’s binary input code and VREF is the voltage of the external reference. Table 3 shows digital codes and the corresponding output voltage for Figure 7’s circuit. Daisy-Chaining Devices The serial data output pin (DOUT) allows multiple MAX5175/MAX5177s to be daisy-chained together as shown in Figure 8. The advantage of this is that only two lines are needed to control all of the DACs on the line. The disadvantage is that it takes n commands to program the DACs. Figure 9 shows several MAX5175/ MAX5177s sharing one common DIN signal line. In this configuration the data bus is common to all devices; however, more I/O lines are required because each device needs a dedicated CS line. The advantage of this configuration is that only one command is needed to program any DAC. 10k 10k REF MAX5175 MAX5177 +5V/+3.3V +5V/+3.3V REF VDD VDD 10k FB V+ FB VOUT 10k DAC DAC OUT OUT V- MAX5175 MAX5177 GND GND R1 = R2 = 10kΩ ± 0.1% Figure 6. Unipolar Output Circuit (Rail-to-Rail) Figure 7. Bipolar Output Circuit Table 2. Unipolar Code Table (Circuit of Figure 6) Table 3. Bipolar Code Table (Circuit of Figure 7) DAC CONTENTS MSB LSB ANALOG OUTPUT DAC CONTENTS MSB LSB ANALOG OUTPUT 11 1111 1111 11 (00) 2 · VREF (4095/4096) 11 1111 1111 11 (00) +VREF [(2 · 4095/4096) - 1] 10 0000 0000 01 (00) 2 · VREF (2049/4096) 10 0000 0000 01 (00) +VREF [(2 · 2049/4096) - 1] 10 0000 0000 00 (00) 2 · VREF (2048/4096) 10 0000 0000 00 (00) +VREF [(2 · 2048/4096) - 1] 01 1111 1111 11 (00) 2 · VREF (2047/4096) 01 1111 1111 11 (00) +VREF [(2 · 2047/4096) - 1] 00 0000 0000 01 (00) 2 · VREF (1/4096) 00 0000 0000 01 (00) +VREF [(2 · 1/4096) - 1] 00 0000 0000 00 (00) 0 00 0000 0000 00 (00) -VREF ______________________________________________________________________________________ 13 MAX5175/MAX5177 Applications Information MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output SCLK SCLK MAX5175 MAX5177 DIN DOUT CS SCLK MAX5175 MAX5177 DIN DOUT CS MAX5175 MAX5177 DOUT DIN CS TO OTHER SERIAL DEVICES Figure 8. Daisy-Chaining MAX5175/MAX5177s DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS MAX5175 MAX5177 CS MAX5175 MAX5177 MAX5175 MAX5177 SCLK SCLK SCLK DIN DIN DIN Figure 9. Multiple MAX5175/MAX5177s Sharing Common DIN and SCLK Lines 14 ______________________________________________________________________________________ Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output Digitally Programmable Current Source The circuit of Figure 11 places an NPN transistor (2N3904 or similar) within the op amp feedback loop to implement a digitally programmable, unidirectional current source. The output current is calculated with the following equation: IOUT = VREF R ⋅ ⋅ N 4096 power-supply source. Connect DGND and AGND pins together at the IC. The best ground connection is achieved by connecting the DAC’s DGND and AGND pins together and connecting that point to the system analog ground plane. If the DAC’s DGND is connected to the system digital ground, digital noise may infiltrate the DAC’s analog portion. Bypass the power supply with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Minimize capacitor lead lengths to reduce inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. In order to maintain INL and DNL performance, as well as gain drift, it is extremely important to provide the lowest possible reference output impedance at the DAC reference input pin. INL degrades if the series resistance on the REF pin exceeds 0.1Ω. The same consideration must be made for the AGND pin. where N is the numeric value of the DAC’s binary input code and R is the sense resistor shown in Figure 11. Power-Supply and Layout Considerations Wire-wrap boards are not recommended. For optimum system performance, use printed circuit boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance +5V/ +3.3V AC REFERENCE INPUT +5V/+3.3V R1 +5V/+3.3V REF MAX495 VDD VL DAC 500mVp-p R1 REF MAX5175 MAX5177 IOUT OUT VDD 2N3904 FB DAC OUT GND R MAX5175 MAX5177 GND Figure 10. AC Reference Input Circuit Figure 11. Digitally Programmable Current Source ______________________________________________________________________________________ 15 MAX5175/MAX5177 Using an AC Reference The MAX5175/MAX5177 accept reference voltages containing AC components, as long as the reference voltage remains between 0 and VDD - 1.4V. Figure 10 shows a technique for applying a sine-wave signal to REF. The reference voltage must remain above AGND. Functional Diagram Chip Information TRANSISTOR COUNT: 3457 VDD AGND DGND CS DIN SCLK PDL SHDN RS CLR SERIAL CONTROL 16-BIT SHIFT REGISTER DECODE CONTROL INPUT REGISTER DAC REGISTER DOUT LOGIC OUTPUT MAX5175 MAX5177 UPO FB OUT DAC REF Package Information QSOP.EPS MAX5175/MAX5177 Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.