19-3064; Rev 1; 12/04 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Features The MAX5522–MAX5525 are dual, 10-bit, ultra-lowpower, voltage-output, digital-to-analog converters (DACs) offering rail-to-rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and consume less than 5µA, making the devices suitable for lowpower and low-voltage applications. A shutdown mode reduces overall current, including the reference input current, to just 0.18µA. The MAX5522–MAX5525 use a 3-wire serial interface that is compatible with SPI™, QSPI™, and MICROWIRE™. Upon power-up, the MAX5522–MAX5525 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that need to be off during power-up. The zero-scale outputs enable glitch-free power-up. ♦ Ultra-Low 5µA Supply Current The MAX5522 accepts an external reference input and provides unity-gain outputs. The MAX5523 contains a precision internal reference and provides a buffered external reference output with unity-gain DAC outputs. The MAX5524 accepts an external reference input and provides force-sense outputs. The MAX5525 contains a precision internal reference and provides a buffered external reference output with force-sense DAC outputs. The MAX5524/MAX5525 are available in a 4mm x 4mm x 0.8mm, 12-pin, thin QFN package. The MAX5522/ MAX5523 are available in an 8-pin µMAX package. All devices are guaranteed over the extended -40°C to +85°C temperature range. For 12-bit compatible devices, refer to the MAX5532– MAX5535 data sheet. For 8-bit compatible devices, refer to the MAX5512–MAX5515 data sheet. ♦ Glitch-Free Outputs During Power-Up Applications Portable Battery-Powered Devices Instrumentation Automatic Trimming and Calibration in Factory or Field Programmable Voltage and Current Sources Industrial Process Control and Remote Industrial Devices Remote Data Conversion and Monitoring Chemical Sensor Cell Bias for Gas Monitors Programmable LCD Bias SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ♦ Shutdown Mode Reduces Supply Current to 0.18µA (max) ♦ Single +1.8V to +5.5V Supply ♦ Small 4mm x 4mm x 0.8mm Thin QFN Package ♦ Internal Reference Sources 8mA of Current (MAX5523/MAX5525) ♦ Flexible Force-Sense-Configured Rail-to-Rail Output Buffers ♦ Fast 16MHz, 3-Wire, SPI-/QSPI-/MICROWIRECompatible Serial Interface ♦ TTL- and CMOS-Compatible Digital Inputs with Hysteresis Ordering Information PART TEMP RANGE PIN-PACKAGE MAX5522EUA -40°C to +85°C 8 µMAX MAX5523EUA -40°C to +85°C 8 µMAX MAX5524ETC -40°C to +85°C 12 Thin QFN-EP* MAX5525ETC -40°C to +85°C 12 Thin QFN-EP* *EP = Exposed paddle (internally connected to GND). Selector Guide PART OUTPUTS REFERENCE TOP MARK MAX5522EUA Unity gain External — MAX5523EUA Unity gain Internal — MAX5524ETC Force sense External AACK MAX5525ETC Force sense Internal AACL Pin Configurations TOP VIEW CS 1 SCLK 2 DIN 3 8 OUTA MAX5522 MAX5523 REFIN(MAX5522) 4 REFOUT(MAX5523) 7 GND 6 VDD 5 OUTB µMAX Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5522–MAX5525 General Description MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUTA, OUTB to GND .................................-0.3V to (VDD + 0.3V) FBA, FBB to GND .......................................-0.3V to (VDD + 0.3V) SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V) REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 12-Pin Thin QFN (derate 16.9mW/°C above +70°C).....1349mW 8-Pin µMAX (derate 5.9mW/°C above +70°C) .............471mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX VDD = 5V, VREF = 4.096V ±1 ±4 VDD = 1.8V, VREF = 1.024V ±1 ±4 Guaranteed monotonic, VDD = 5V, VREF = 4.096V ±0.2 ±1 Guaranteed monotonic, VDD = 1.8V, VREF = 1.024V ±0.2 ±1 VDD = 5V, VREF = 4.096V ±1 ±20 VDD = 1.8V, VREF = 1.024V ±1 ±20 UNITS STATIC ACCURACY (MAX5522/MAX5524 EXTERNAL REFERENCE) Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Offset Error (Note 2) N INL DNL VOS 10 ±2 GE PSRR ±0.5 ±2 VDD = 1.8V, VREF = 1.024V ±0.5 ±2 1.8V ≤ VDD ≤ 5.5V mV µV/°C VDD = 5V, VREF = 4.096V Gain-Error Temperature Coefficient Power-Supply Rejection Ratio LSB LSB Offset-Error Temperature Drift Gain Error (Note 3) Bits LSB ±4 ppm/°C 85 dB STATIC ACCURACY (MAX5523/MAX5525 INTERNAL REFERENCE) Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Offset Error (Note 2) N INL DNL VOS 10 ±1 ±4 VDD = 1.8V, VREF = 1.2V ±1 ±4 Guaranteed monotonic, VDD = 5V, VREF = 3.9V ±0.2 ±1 Guaranteed monotonic, VDD = 1.8V, VREF = 1.2V ±0.2 ±1 VDD = 5V, VREF = 3.9V ±1 ±20 VDD = 1.8V, VREF = 1.2V ±1 ±20 Gain-Error Temperature Coefficient 2 GE LSB LSB ±2 Offset-Error Temperature Drift Gain Error (Note 3) Bits VDD = 5V, VREF = 3.9V µV/°C VDD = 5V, VREF = 3.9V ±0.5 ±2 VDD = 1.8V, VREF = 1.2V ±0.5 ±2 ±4 _______________________________________________________________________________________ mV LSB ppm/°C Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs (VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Power-Supply Rejection Ratio SYMBOL PSRR CONDITIONS MIN 1.8V ≤ VDD ≤ 5.5V TYP MAX 85 UNITS dB REFERENCE INPUT (MAX5522/MAX5524) Reference-Input Voltage Range Reference-Input Impedance VREFIN RREFIN 0 Normal operation VDD 4.1 In shutdown V MΩ 2.5 GΩ REFERENCE OUTPUT (MAX5523/MAX5525) Initial Accuracy VREFOUT Output-Voltage Temperature Coefficient VTEMPCO Line Regulation Load Regulation Output Noise Voltage Short-Circuit Current (Note 6) No external load, VDD = 1.8V 1.197 1.214 1.231 No external load, VDD = 2.5V 1.913 1.940 1.967 No external load, VDD = 3V 2.391 2.425 2.459 No external load, VDD = 5V 3.828 3.885 3.941 TA = -40°C to +85°C (Note 4) 12 30 ppm/°C VREFOUT < VDD - 200mV (Note 5) 2 200 µV/V 0 ≤ IREFOUT ≤ 1mA, sourcing, VDD = 1.8V, VREF = 1.2V 0.3 2 0 ≤ IREFOUT ≤ 8mA, sourcing, VDD = 5V, VREF = 3.9V 0.3 2 -150µA ≤ IREFOUT ≤ 0, sinking 0.2 0.1Hz to 10Hz, VREF = 3.9V 150 10Hz to 10kHz, VREF = 3.9V 600 0.1Hz to 10Hz, VREF = 1.2V 50 10Hz to 10kHz, VREF = 1.2V 450 VDD = 5V 30 VDD = 1.8V 14 V µV/µA µVP-P mA Capacitive Load Stability Range (Note 7) 0 to 10 nF Thermal Hysteresis (Note 8) 200 ppm Reference Power-Up Time (from Shutdown) REFOUT unloaded, VDD = 5V 5.4 REFOUT unloaded, VDD = 1.8V 4.4 Long-Term Stability DAC OUTPUTS (OUTA, OUTB) Capacitive Driving Capability Short-Circuit Current (Note 6) CL ms 200 ppm/ 1khrs 1000 pF VDD = 5V, VOUT set to full scale, OUT shorted to GND, source current 65 VDD = 5V VOUT set to 0V, OUT shorted to VDD, sink current 65 VDD = 1.8V, VOUT set to full scale OUT shorted to GND, source current 14 VDD = 1.8V, VOUT set to 0V, OUT shorted to VDD, sink current 14 mA _______________________________________________________________________________________ 3 MAX5522–MAX5525 ELECTRICAL CHARACTERISTICS (continued) MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS TYP VDD = 5V VDD = 1.8V 3.8 Coming out of standby (MAX5523/MAX5525) VDD = 1.8V to 5.5V 0.4 DAC Power-Up Time Output Power-Up Glitch MIN Coming out of shutdown (MAX5522/MAX5524) MAX UNITS 3 CL = 100pF FB_ Input Current µs 10 mV 10 pA DIGITAL INPUTS (SCLK, DIN, CS) 4.5V ≤ VDD ≤ 5.5V Input High Voltage VIH 2.4 2.7V < VDD ≤ 3.6V V 2.0 1.8V ≤ VDD ≤ 2.7V 0.7 x VDD 4.5V ≤ VDD ≤ 5.5V Input Low Voltage VIL 0.8 2.7V < VDD ≤ 3.6V 0.6 1.8V ≤ VDD ≤ 2.7V Input Leakage Current IIN Input Capacitance CIN V 0.3 x VDD ±0.05 (Note 9) ±0.5 µA 10 pF Positive and negative (Note 10) 10 V/ms 0.1 to 0.9 of full scale to within 0.5 LSB (Note 10) 660 µs DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Voltage-Output Settling Time 0.1Hz to 10Hz Output Noise Voltage 10Hz to 10kHz VDD = 5V 80 VDD = 1.8V 55 VDD = 5V 620 VDD = 1.8V 476 µVP-P POWER REQUIREMENTS Supply Voltage Range VDD 1.8 MAX5523/MAX5525 Supply Current (Note 9) IDD MAX5522/MAX5524 Standby Supply Current Shutdown Supply Current 4 IDDSD IDDPD MAX5523/MAX5525 (Note 9) (Note 9) 5.5 VDD = 5V 7.0 8.0 VDD = 3V 6.4 8.0 VDD = 1.8V 7.0 8.0 VDD = 5V 3.8 5.0 VDD = 3V 3.8 5.0 VDD = 1.8V 4.7 6.0 VDD = 5V 3.3 4.5 VDD = 3V 2.8 4.0 VDD = 1.8V 2.4 3.5 0.05 0.25 _______________________________________________________________________________________ V µA µA µA Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522–MAX5525 TIMING CHARACTERISTICS (VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 16.7 MHz TIMING CHARACTERISTICS (VDD = 4.5V to 5.5V ) Serial Clock Frequency fSCLK 0 DIN to SCLK Rise Setup Time tDS 15 ns DIN to SCLK Rise Hold Time tDH 0 ns SCLK Pulse-Width High tCH 24 ns SCLK Pulse-Width Low tCL 24 ns CS Pulse-Width High tCSW 100 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns CS Fall to SCLK Rise Setup Time tCSS 20 ns SCLK Fall to CS Fall Setup tCSO 0 ns CS Rise to SCK Rise Hold Time tCS1 20 ns TIMING CHARACTERISTICS (VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 MHz TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V ) Serial Clock Frequency fSCLK 0 DIN to SCLK Rise Setup Time tDS 24 ns DIN to SCLK Rise Hold Time tDH 0 ns SCLK Pulse-Width High tCH 40 ns ns SCLK Pulse-Width Low tCL 40 CS Pulse-Width High tCSW 150 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns CS Fall to SCLK Rise Setup Time tCSS 30 ns SCLK Fall to CS Fall Setup tCSO 0 ns CS Rise to SCK Rise Hold Time tCS1 30 ns Note 1: Linearity is tested within codes 24 to 1020. Note 2: Offset is tested at code 24. Note 3: Gain is tested at code 1023. For the MAX5524/MAX5525, FB_ is connected to its respective OUT_. Note 4: Guaranteed by design. Not production testsed Note 5: VDD must be a minimum of 1.8V. Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded. Note 7: Optimal noise performance is at 2nF load capacitance. Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN. Note 9: All digital inputs at VDD or GND. Note 10: Load = 10kΩ in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5522/MAX5524) or VREF = 3.9V (MAX5523/MAX5525). _______________________________________________________________________________________ 5 Typical Operating Characteristics (VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.) 4.5 3.5 3.0 2.5 2.0 1.5 3.5 3.0 2.5 2.0 1.5 8 7 6 5 4 3 1.0 1.0 2 0.5 0.5 1 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 -40 -15 10 35 60 85 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) TEMPERATURE (°C) SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. TEMPERATURE (MAX5523/MAX5525) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5522/MAX5524) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5523/MAX5525) 7 6 5 4 3 2 100 10 1 MAX5522 toc06 1000 SHUTDOWN SUPPLY CURRENT (nA) 8 1000 MAX5522 toc05 9 SHUTDOWN SUPPLY CURRENT (nA) MAX5522 toc04 10 SUPPLY CURRENT (µA) 9 SUPPLY CURRENT (µA) 4.0 SUPPLY CURRENT (µA) 4.0 10 MAX5522 toc02 4.5 SUPPLY CURRENT (µA) 5.0 MAX5522 toc01 5.0 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5523/MAX5525) SUPPLY CURRENT vs. TEMPERATURE (MAX5522/MAX5524) MAX5522 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5522/MAX5524) 100 10 1 1 0.1 -40 -15 10 35 60 85 0.1 -40 -15 10 35 60 85 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) STANDBY SUPPLY CURRENT vs. TEMPERATURE (MAX5523/MAX5525) SUPPLY CURRENT vs. CLOCK FREQUENCY SUPPLY CURRENT vs. LOGIC INPUT VOLTAGE 4.0 3.5 SUPPLY CURRENT (µA) VREF = 3.9V VREF = 2.4V 3.0 2.5 VREF = 1.9V 2.0 CS = LOGIC LOW CODE = 0 VREF = 1.2V 1.5 5.0 VDD = 5V 100 10 VDD = 1.8V VDD = 5V ALL DIGITAL INPUTS SHORTED TOGETHER 4.5 4.0 SUPPLY CURRENT (mA) 4.5 MAX5522 toc08 1000 MAX5522 toc07 5.0 85 3.5 3.0 2.5 2.0 1.5 1.0 1.0 0.5 0.5 0 1 0 -40 -15 10 35 TEMPERATURE (°C) 6 -40 TEMPERATURE (°C) MAX5522 toc09 0 STANDBY SUPPLY CURRENT (µA) MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs 60 85 0.01 0.1 1 10 100 1000 10000 100000 FREQUENCY (kHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC INPUT VOLTAGE (V) _______________________________________________________________________________________ Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs INL vs. INPUT CODE (VDD = VREF = 1.8V) -0.2 -0.4 0.05 0.04 0.03 DNL (LSB) -0.2 INL (LSB) 0 -0.4 0.02 0.01 -0.6 -0.6 -0.8 -0.8 -0.01 -1.0 -1.0 -0.02 -1.2 0 -0.03 -1.2 400 600 800 1000 1200 0 200 400 600 800 1000 400 600 800 DIGITAL INPUT CODE DNL vs. INPUT CODE (VDD = VREF = 5V) OFFSET VOLTAGE vs. TEMPERATURE GAIN ERROR CHANGE vs. TEMPERATURE MAX5522 toc13 1.0 0.8 0.6 OFFSET VOLTAGE (mV) 0.02 0.01 0 -0.01 VDD = 5V VREF = 3.9V 0.4 0.2 0 -0.2 -0.4 -0.6 -0.02 -0.8 -0.03 -1.0 400 600 800 1000 0.08 1200 VDD = 5V VREF = 3.9V 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -40 1200 0.10 1000 MAX5522 toc15 DIGITAL INPUT CODE 0.03 200 200 DIGITAL INPUT CODE 0.04 -15 10 35 60 -0.10 85 -40 -15 10 35 85 60 DIGITAL INPUT CODE TEMPERATURE (°C) TEMPERATURE (°C) DIGITAL FEEDTHROUGH RESPONSE DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT SCLK 5V/div DIN 5V/div 0.6048 0.6046 0.6044 0.6042 OUT 50mV/div 20µs/div 1.9440 1.9435 1.9430 MAX5522 toc18 CS 5V/div VDD = 1.8V DAC CODE = MIDSCALE VREF = 1.2V DAC OUTPUT VOLTAGE (V) 0.6050 MAX5522 toc17 MAX5522 toc16 ZERO SCALE DAC OUTPUT VOLTAGE (V) 0 0 1200 GAIN ERROR CHANGE (LSB) 200 MAX5522 toc14 0 MAX5522 toc12 0.2 0 0.06 MAX5522 toc11 0.2 INL (LSB) 0.4 MAX5522 toc10 0.4 DNL (LSB) DNL vs. INPUT CODE (VDD = VREF = 1.8V) INL vs. INPUT CODE (VDD = VREF = 5V) VDD = 5.0V DAC CODE = MIDSCALE VREF = 3.9V 1.9425 1.9420 1.9415 1.9410 1.9405 0.6040 -1000-800 -600 -400 -200 0 200 400 600 800 1000 DAC OUTPUT CURRENT (µA) 1.9400 -10 -8 -6 -4 -2 0 2 4 6 8 10 DAC OUTPUT CURRENT (mA) _______________________________________________________________________________________ 7 MAX5522–MAX5525 Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.) DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT VDD = 5V 2 VDD = 3V 1 MAX5522 toc20 VREF = VDD 4.5 DAC OUTPUT VOLTAGE (V) 4 MAX5522 toc21 5.0 MAX5522 toc19 VREF = VDD CODE = MIDSCALE 3 OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 1.8V, VREF = 1.2V) DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT 5 CODE = MIDSCALE 4.0 3.5 VDD = 5V 3.0 2.5 VOUT 200mV/div VDD = 3V 2.0 1.5 1.0 VDD = 1.8V 0 0.001 0.010 0.100 0.5 1 10 0 0.001 100 VDD = 1.8V 0.01 0.1 1 10 100 OUTPUT SOURCE CURRENT (mA) OUTPUT SINK CURRENT (mA) OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 5V, VREF = 3.9V) OUTPUT MINIMUM SERIES RESISTANCE vs. LOAD CAPACITANCE MAX5522 toc22 600 MINIMUM SERIES RESISTANCE (Ω) FOR NO OVERSHOOT VOUT 500mV/div 500 POWER-UP OUTPUT VOLTAGE GLITCH MAX5522 toc24 VDD 2V/div 400 300 200 VOUT 10mV/div 100 0 0.0001 0.001 200µs/div 100µs/div MAX5522 toc23 OUTPUT VOLTAGE (V) 0.01 0.1 1 10 100 20ms/div CAPACITANCE (µF) REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE VOUT AC-COUPLED 5mV/div MAX5522 toc26 3.940 VDD = 5V 3.935 3.930 3.925 3.920 3.915 3.910 3.905 3.900 100µs/div VDD = 1.8V 1.219 1.218 1.217 1.216 1.215 1.214 -40 -15 10 35 TEMPERATURE (°C) 8 1.220 REFERENCE OUTPUT VOLTAGE (V) MAX5522 toc25 REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT MAX5522 toc27 MAJOR CARRY OUTPUT VOLTAGE GLITCH (CODE 7FFh TO 800h) (VDD = 5V, VREF = 3.9V) REFERENCE OUTPUT VOLTAGE (V) MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs 60 85 -500 1500 3500 5500 7500 REFERENCE OUTPUT CURRENT (µA) _______________________________________________________________________________________ Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT 3.91 3.90 3.89 MAX5522 toc30 MAX5522 toc29 REFERENCE OUTPUT VOLTAGE (V) VDD = 5V 1.21750 REFERENCE OUTPUT VOLTAGE (mV) MAX5522 toc28 3.92 REFERENCE LINE-TRANSIENT RESPONSE (VREF = 1.2V) REFERENCE OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 1.21748 1.21746 2.8V VDD 1.21744 1.21742 1.8V 1.21740 VREF 500mV/div 1.21738 1.21736 1.21734 1.21732 3.88 -500 2000 4500 7000 1.21730 9500 12,000 14,500 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 REFERENCE OUTPUT CURRENT (µA) 100µs/div SUPPLY VOLTAGE (V) REFERENCE LOAD TRANSIENT (VDD = 1.8V) REFERENCE LINE-TRANSIENT RESPONSE (VREF = 3.9V) MAX5522 toc32 MAX5522 toc31 5.5V VDD REFOUT SOURCE CURRENT 0.5mA/div 4.5V VREF 500mV/div VREF 500mV/div 3.9V 200µs/div 100µs/div REFERENCE LOAD TRANSIENT (VDD = 1.8V) REFERENCE LOAD TRANSIENT (VDD = 5V) MAX5522 toc34 MAX5522 toc33 200µs/div REFOUT SOURCE CURRENT 0.5mA/div REFOUT SINK CURRENT 50µA/div VREF 500mV/div 3.9V VREF 500mV/div 200µs/div _______________________________________________________________________________________ 9 MAX5522–MAX5525 Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25°C, unless otherwise noted.) REFERENCE LOAD TRANSIENT (VDD = 5V) REFERENCE PSRR vs. FREQUENCY MAX5522 toc35 VREF 500mV/div 3.9V MAX5522 toc36 POWER-SUPPLY REJECTION RATIO (dB) 80 REFOUT SINK CURRENT 100µA/div VDD = 1.8V 70 60 50 40 30 20 10 0 0.01 200µs/div 0.1 1 10 100 1000 FREQUENCY (kHz) REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V) REFERENCE PSRR vs. FREQUENCY MAX5522 toc38 MAX5522 toc37 80 POWER-SUPPLY REJECTION RATIO (dB) MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs VDD = 5V 70 60 50 40 100µV/div 30 20 10 0 0.01 0.1 1 10 100 1000 1s/div FREQUENCY (kHz) REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V) DAC-TO-DAC CROSSTALK MAX5522 toc39 MAX5522 toc40 OUTA 1V/div 100µV/div OUTB AC-COUPLED 10mV/div OUTB AT FULL SCALE 1s/div 10 400µs/div ______________________________________________________________________________________ Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs PIN NAME FUNCTION MAX5522 MAX5523 MAX5524 MAX5525 1 1 1 1 CS 2 2 2 2 SCLK Serial-Interface Clock Input 3 3 3 3 DIN Serial-Interface Data Input 4 — 4 — REFIN — 4 — 4 REFOUT 5, 11 5, 11 Active-Low Digital Chip-Select Input Reference Input Reference Output No Connection. Leave N.C. inputs unconnected (floating) or connected to GND. — — N.C. — — 6 6 FBB 5 5 7 7 OUTB 6 6 8 8 VDD Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a 0.1µF capacitor. Channel B Feedback Input Channel B Analog Voltage Output 7 7 9 9 GND Ground 8 8 10 10 OUTA Channel A Analog Voltage Output — — 12 12 FBA — — EP EP Exposed Paddle Channel A Feedback Input Exposed Paddle. Connect EP to GND. Functional Diagrams VDD POWERDOWN CONTROL MAX5522 DAC REGISTER INPUT REGISTER SCLK DIN CS REFIN 10-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA DAC REGISTER INPUT REGISTER 10-BIT DAC OUTB GND ______________________________________________________________________________________ 11 MAX5522–MAX5525 Pin Description Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522–MAX5525 Functional Diagrams (continued) VDD POWERDOWN CONTROL 2-BIT PROGRAMMABLE REFERENCE REF BUF REFOUT MAX5523 INPUT REGISTER SCLK DIN CS DAC REGISTER 10-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA DAC REGISTER INPUT REGISTER 10-BIT DAC OUTB GND VDD POWERDOWN CONTROL MAX5524 DAC REGISTER INPUT REGISTER SCLK DIN CS REFIN 10-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA FBA DAC REGISTER INPUT REGISTER 10-BIT DAC OUTB FBB GND 12 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs VDD POWERDOWN CONTROL 2-BIT PROGRAMMABLE REFERENCE REF BUF REFOUT MAX5525 INPUT REGISTER SCLK DIN CS DAC REGISTER 10-BIT DAC CONTROL LOGIC AND SHIFT REGISTER OUTA FBA DAC REGISTER INPUT REGISTER 10-BIT DAC OUTB FBB GND Detailed Description The MAX5522–MAX5525 dual, 10-bit, ultra-low-power, voltage-output DACs offer rail-to-rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and require only 5µA (max) supply current. These devices feature a shutdown mode that reduces overall current, including the reference input current, to just 0.18µA (max) The MAX5523/MAX5525 include an internal reference that saves additional board space and can source up to 8mA, making it functional as a system reference. The 16MHz, 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE protocols. When VDD is applied, all DAC outputs are driven to zero scale with virtually no output glitch. The MAX5522/ MAX5523 output buffers are configured in unity gain and come in µMAX packages. The MAX5524/MAX5525 output buffers are configured in force sense allowing users to externally set voltage gains on the output (an output-amplifier inverting input is available). The MAX5524/MAX5525 come in 4mm x 4mm thin QFN packages. Digital Interface The MAX5522–MAX5525 use a 3-wire serial interface that is compatible with SPI/QSPI/MICROWIRE protocols (Figures 1 and 2). The MAX5522–MAX5525 include a single, 16-bit, input shift register. Data loads into the shift register through the serial interface. CS must remain low until all 16 bits are clocked in. The 16 bits consist of 4 control bits (C3–C0), 10 data bits (D9–D0) (Table 1), and 2 sub-bits (S1 and S0). D9–D0 are the DAC data bits and S1 and S0 are the sub-bits. The sub-bits must be set to zero for proper operation. Following the control bits, data loads MSB first, D9–D0. The control bits C3–C0 control the MAX5522–MAX5525, as outlined in Table 2. Each DAC channel includes two registers: an input register and a DAC register. The input register holds input data. The DAC register contains the data updated to the DAC output. The double-buffered register configuration allows any of the following: • Loading the input registers without updating the DAC registers • Updating the DAC registers from the input registers • Updating all the input and DAC registers simultaneously ______________________________________________________________________________________ 13 MAX5522–MAX5525 Functional Diagrams (continued) MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Table 1. Serial Write Data Format CONTROL DATA BITS MSB C3 LSB C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 Sub-bits S1 to S0 must be set to zero for proper operation. tCH SCLK tCL tDS C3 DIN tCS0 C2 C1 S0 tDH tCSH tCSS CS tCSW tCS1 Figure 1. Timing Diagram SCLK DIN 1 C3 2 C2 3 C1 CONTROL BITS 4 C0 5 D9 6 D8 7 D7 8 D6 9 D5 10 D4 DATA BITS 11 D3 12 D2 13 D1 14 D0 15 S1 S0 SUB-BITS COMMAND EXECUTED CS Figure 2. Register Loading Diagram 14 16 ______________________________________________________________________________________ S0 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs CONTROL BITS INPUT DATA SUB-BITS FUNCTION C3 C2 C1 C0 D9–D0 S1 AND S0 0 0 0 0 XXXXXXXXXX 00 No operation; command is ignored. 0 0 0 1 10-bit data 00 Load input register A from shift register; DAC registers unchanged; DAC outputs unchanged. 0 0 1 0 10-bit data 00 Load input register B from shift register; DAC registers unchanged; DAC outputs unchanged. 0 0 1 1 — — Command reserved. Do not use. 0 1 0 0 — — Command reserved. Do not use. 0 1 0 1 — — Command reserved. Do not use. 0 1 1 0 — — Command reserved. Do not use. 0 1 1 1 — — Command reserved. Do not use. 00 Load DAC registers A and B from respective input registers; DAC outputs A and B updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown. 00 Load input register A and DAC register A from shift register; DAC output A updated; Load DAC register B from input register B; DAC output B updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown. 1 1 0 0 0 0 0 1 10-bit data 10-bit data 1 0 1 0 10-bit data 00 Load input register B and DAC register B from shift register; DAC output B updated; Load DAC register A from input register A; DAC output A updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown. 1 0 1 1 — — Command reserved. Do not use. 1 1 0 0 D9, D8, XXXXXXXX 00 MAX5523/MAX5525 enter standby*, MAX5522/MAX5524 enter shutdown. For the MAX5523/MAX5525, D9 and D8 configure the internal reference voltage (Table 3). 1 1 0 1 D9, D8, XXXXXXXX 00 MAX5522–MAX5525 enter normal operation; DAC outputs reflect existing contents of DAC registers. For the MAX5523/MAX5525, D9 and D8 configure the internal reference voltage (Table 3). 1 1 1 0 D9, D8, XXXXXXXX 00 MAX5522–MAX5525 enter shutdown; DAC outputs set to high impedance. For the MAX5523/MAX5525, D9 and D8 configure the internal reference voltage (Table 3). 00 Load input registers A and B and DAC registers A and B from shift register; DAC outputs A and B updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown. 1 1 1 1 10-bit data X = Don’t care. *Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown. ______________________________________________________________________________________ 15 MAX5522–MAX5525 Table 2. Serial-Interface Programming Commands MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Power Modes The MAX5522–MAX5525 feature two power modes to conserve power during idle periods. In normal operation, the device is fully operational. In shutdown mode, the device is completely powered down, including the internal voltage reference in the MAX5523/MAX5525. The MAX5523/MAX5525 also offer a standby mode in which all circuitry is powered down except the internal voltage reference. Standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. It also helps reduce the wake-up delay by not requiring the reference to power up when returning to normal operation. For the MAX5523/MAX5525, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation first before entering standby mode. To enter standby from shutdown, issue the command to return to normal operation followed immediately by the command to go into standby. Table 2 shows several commands that bring the MAX5523/MAX5525 back to normal operation. When transitioning from standby mode to normal operation, only the DAC power-up time is required before the DAC outputs are valid. Reference Input Shutdown Mode The MAX5522–MAX5525 feature a software-programmable shutdown mode that reduces the supply current and the interface input-current to 0.18µA (max). Writing an input control word with control bits C[3:0] = 1110 (Table 2) places the device in shutdown mode. In shutdown, the MAX5522/MAX5524 reference input and DAC output buffers go high impedance. Placing the MAX5523/ MAX5525 into shutdown turns off the internal reference and the DAC output buffers go high impedance. The serial interface still remains active for all devices. The MAX5522/MAX5524 accept a reference with a voltage range extending from 0 to VDD. The output voltage (VOUT) is represented by a digitally programmable voltage source as: VOUT = (VREF x N / 256) x gain where N is the numeric value of the DAC’s binary input code (0 to 1023), VREF is the reference voltage, gain is the externally set voltage gain for the MAX5524, and gain is one for the MAX5522. In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5GΩ (typ). Table 2 shows several commands that bring the MAX5522–MAX5525 back to normal operation. The power-up time from shutdown is required before the DAC outputs are valid. Note: For the MAX5523/MAX5525, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation first before entering standby mode. The MAX5523/MAX5525 internal voltage reference is software configurable to one of four voltages. Upon power-up, the default reference voltage is 1.214V. Configure the reference voltage using D8 and D9 data bits (Table 3) when the control bits are as follows C[3:0] = 1100, 1101, or 1110 (Table 2). VDD must be kept at a minimum of 200mV above VREF for proper operation. Standby Mode (MAX5523/MAX5525 Only) The MAX5523/MAX5525 feature a software-programmable standby mode that reduces the typical supply current to 3µA (max). Standby mode powers down all circuitry except the internal voltage reference. Place the device in standby mode by writing an input control word with control bits C[3:0] = 1100 (Table 2). The internal reference and serial interface remain active while the DAC output buffers go high impedance. 16 Reference Output Table 3. Reference Output Voltage Programming D9 D8 REFERENCE VOLTAGE (V) 0 0 1.214 0 1 1.940 1 0 2.425 1 1 3.885 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs 1-Cell and 2-Cell Circuits See Figure 3 for an illustration of how to power the MAX5522–MAX5525 with either one lithium-ion battery or two alkaline batteries. The low current consumption of the devices make the MAX5522–MAX5525 ideal for battery-powered applications. Programmable Current Source See the circuit in Figure 4 for an illustration of how to configure the MAX5524/MAX5525 as a programmable current source for driving an LED. The MAX5524/ MAX5525 drive a standard NPN transistor to program the current source. The current source (ILED) is defined in the equation in Figure 4. VDD 1.8V ≤ VALKALINE ≤ 3.3V 2.2V ≤ VLITHIUM ≤ 3.3V 536kΩ +1.25V REFIN DAC VOUT 0.1µF 0.01µF MAX6006 (1µA, 1.25V SHUNT REFERENCE) VOUT (1.22mV / LSB) V × NDAC VOUT = REFIN 1024 MAX5524 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. GND Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell V+ LED REFIN DAC VOUT ILED REFIN DAC VOUT 1/2 MAX5524 V × NDAC ILED = REFIN 1024 × R 2N3904 1/2 MAX5524 R FB FB R NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. Figure 4. Programmable Current Source Driving an LED VOUT VOUT = VBIAS + (IT × R) TRANSDUCER VBIAS IT V × NDAC VBIAS = REFIN 1024 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. Figure 5. Transimpedance Configuration for a Voltage-Biased Current-Output Transducer ______________________________________________________________________________________ 17 MAX5522–MAX5525 Applications Information MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Voltage Biasing a Current-Output Transducer See the circuit in Figure 5 for an illustration of how to configure the MAX5524/MAX5525 to bias a current-output transducer. In Figure 5, the output voltage of the MAX5524/MAX5525 is a function of the voltage drop across the transducer added to the voltage drop across the feedback resistor R. Unipolar Output An example of a custom fixed gain using the MAX5524/ MAX5525 force-sense output is shown in Figure 8. In this example, R1 and R2 set the gain for VOUTA. VOUTA = [(VREFIN x NA) / 1024] x [1 + (R2 / R1)] where NA represents the numeric value of the DAC input code. Self-Biased Two-Electrode Potentiostat Application Figure 6 shows the MAX5524 in a unipolar output configuration with unity gain. Table 4 lists the unipolar output codes. See the circuit in Figure 10 for an illustration of how to use the MAX5525 to bias a two-electrode potentiostat on the input of an ADC. Bipolar Output Power Supply and Bypassing Considerations The MAX5524 output can be configured for bipolar operation as shown in Figure 7. The output voltage is given by the following equation: VOUT_ = VREFIN x [(NA - 512) / 512] where NA represents the decimal value of the DAC’s binary input code. Table 5 shows the digital codes (offset binary) and the corresponding output voltage for the circuit in Figure 7. Configurable Output Gain The MAX5524/MAX5525 have force-sense outputs, which provide a connection directly to the inverting terminal of the output op amp, yielding the most flexibility. The advantage of the force-sense output is that specific gains can be set externally for a given application. The gain error for the MAX5524/MAX5525 is specified in a unity-gain configuration (op-amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. Another advantage of the force-sense DAC is that it allows many useful circuits to be created with only a few simple external components. Bypass the power supply with a 4.7µF capacitor in parallel with a 0.1µF capacitor to GND. Minimize lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. For the thin QFN package, connect the exposed pad to ground. Table 4. Unipolar Code Table (Gain = +1) DAC CONTENTS MSB LSB ANALOG OUTPUT 1111 1111 1100 +VREF (1023/1024) 1000 0000 0100 +VREF (513/1024) 1000 0000 0000 +VREF (512/1024) = +VREF/2 0111 1111 1100 +VREF (511/1024) 0000 0000 0100 +VREF (1/1024) 0000 0000 0000 0V Table 5. Bipolar Code Table (Gain = +1) REFIN DAC OUT_ DAC CONTENTS MSB 1111 MAX5524 FB_ V × NA VOUT = REFIN 1024 NA IS THE DAC INPUT CODE (0 TO 1023 DECIMAL). LSB 1111 ANALOG OUTPUT 1100 +VREF (511/512) +VREF (1/512) 1000 0000 0100 1000 0000 0000 0V 0111 1111 1100 -VREF (1/512) 0000 0000 0100 -VREF (511/512) 0000 0000 0000 -VREF (512/512) = -VREF Figure 6. Unipolar Output Circuit 18 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Digital and AC transient signals coupling to GND can create noise at the output. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards. Good PC board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. V 255 - NPOT × NDAC VOUT = REFIN 1+ 1024 255 ( ) NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE. 1.8V ≤ VDD ≤ 5.5V REFIN DAC VOUT VOUT H CS1 1/2 MAX5524 FB MAX5401 SOT-POT 100kΩ W SCLK 5PPM/°C RATIOMETRIC TEMPCO DIN 10kΩ 10kΩ CS2 L V+ VOUT Figure 9. Software-Configurable Output Gain DAC OUT_ REFIN V- 1/2 MAX5524 FB_ REF DAC OUT Figure 7. Bipolar Output Circuit TO ADC IF RF FB WE 1/2 MAX5525 REFIN SENSOR DAC VOUTA VOUT1 R2 FBA CE V R2 × NDACA VOUT1 = REFIN 1+ 1024 R1 ( NDACA IS THE NUMERIC VALUE OF THE DAC A INPUT CODE. VOUTB BAND GAP REFOUT TO ADC VOUT2 VOUT2 = FBB ) CL R1 1/2 MAX5524 DAC TO ADC VREFIN × NDACB 1024 Figure 10. Self-Biased Two-Electrode Potentiostat Application NDACB IS THE NUMERIC VALUE OF THE DAC B INPUT CODE. Figure 8. Separate Force-Sense Outputs Create Unity and Greater-than-Unity DAC Gains Using the Same Reference ______________________________________________________________________________________ 19 MAX5522–MAX5525 Layout Considerations Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522–MAX5525 Pin Configurations (continued) REF TOP VIEW OUTA DAC TO ADC IF RF FBA N.C. OUTA 12 11 10 FBA WE CS 1 SCLK 2 DIN 3 9 GND 8 VDD 7 OUTB MAX5525 SENSOR REF MAX5524 MAX5525 CE DAC OUTB 4 REFIN(MAX5524) REFOUT(MAX5525) FBB BAND GAP REFOUT TO ADC 5 6 N.C. FBB THIN QFN CL Figure 11. Driven Two-Electrode Potentiostat Application Chip Information TRANSISTOR COUNT: 10,688 PROCESS: BiCMOS 20 ______________________________________________________________________________________ Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs 24L QFN THIN.EPS PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 ______________________________________________________________________________________ 21 MAX5522–MAX5525 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX5522–MAX5525 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 22 ______________________________________________________________________________________ C 2 2 Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs 8 INCHES DIM A A1 A2 b E ÿ 0.50±0.1 H c D e E H 0.6±0.1 L 1 1 α 0.6±0.1 S BOTTOM VIEW D MIN 0.002 0.030 MAX 0.043 0.006 0.037 0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6∞ 0∞ 0.0207 BSC 8LUMAXD.EPS 4X S 8 MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95 0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 5.03 4.78 0.41 0.66 0∞ 6∞ 0.5250 BSC TOP VIEW A1 A2 A α c e b L SIDE VIEW FRONT VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 8L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0036 REV. J 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5522–MAX5525 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)