19-2331; Rev 2; 5/09 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference The MAX5232/MAX5233 low-power, dual 10-bit voltageoutput digital-to-analog converters (DACs) feature an internal 10ppm/°C precision bandgap voltage reference and precision output amplifiers. The MAX5233 operates on a single 5V supply with an internal 2.465V reference and features a 4.092V full-scale output range. The MAX5232 operates on a single 3V supply with an internal 1.234V reference and features a 2.046V full-scale output range. The MAX5233 consumes only 470µA while the MAX5232 consumes only 420µA of supply current. Both devices feature low-power (2µA) software- and hardware-enabled shutdown modes. The MAX5232/MAX5233 feature a 13.5MHz SPI™-, QSPI™-, and MICROWIRE™-compatible 3-wire serial interface. An additional data output (DOUT) allows for daisy-chaining and read back. Each DAC has a doublebuffered digital input. The MAX5232/MAX5233 feature two software-selectable shutdown output impedances: 1kΩ or 200kΩ. A power-up reset feature sets DAC outputs at ground or at the midscale DAC code. The MAX5232/MAX5233 are specified over the extended temperature range (-40°C to +85°C) and are available in 16-pin QSOP packages. Features ♦ Internal 10ppm/°C Precision Bandgap Reference 2.465V (MAX5233) 1.234V (MAX5232) ♦ Single-Supply Operation 5V (MAX5233) 3V (MAX5232) ♦ Low Supply Current 470μA (MAX5233) 420μA (MAX5232) ♦ 13.5MHz SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial Interface ♦ Pin-Programmable Power-Up Reset State to Zero or Midscale Output Voltage ♦ Programmable Shutdown Modes with 1kΩ or 200kΩ Internal Output Loads ♦ Recalls Output State Prior to Shutdown or Reset ♦ Buffered Output Drives 5kΩ || 100pF Loads ♦ Space-Saving 16-Pin QSOP Package Applications Industrial Process Controls Automatic Test Equipment Ordering Information Digital Offset and Gain Adjustment TEMP RANGE PINPACKAGE MAX5232EEE+ -40°C to +85°C 16 QSOP ±0.5 MAX5233EEE+ -40°C to +85°C 16 QSOP ±0.5 PART Motion Control µP-Controlled Systems Pin Configuration INL (LSB) +Denotes a lead(Pb)-free/RoHS-compliant package. Note: For leaded version, contact factory. TOP VIEW OSA 1 16 OSB OUTA 2 15 OUTB RSTV 3 14 VDD LDAC 4 CLR 5 MAX5232 MAX5233 13 AGND 12 REF CS 6 11 PDL DIN 7 10 DOUT SCLK 8 Functional Diagram appears at end of data sheet. 9 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. DGND QSOP ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com MAX5232/MAX5233 General Description MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Output (DOUT) to DGND...................-0.3V to VDD + 0.3V OUT_ to AGND .............................................-0.3V to VDD + 0.3V OS_ to AGND...................................................-4V to VDD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX5233 (VDD = +4.5V to +5.5V, VOS_ = VAGND = VDGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 10 Bits Integral Nonlinearity (Note 1) INL ±0.5 LSB Differential Nonlinearity DNL ±1 LSB Offset Error (Note 2) Offset-Temperature Coefficient (Note 3) Full-Scale Voltage Full-Scale Temperature Coefficient (Notes 3 and 6) Power-Supply Rejection ±3 VOS TCVOS VFS 8 Code = 3FF hex, TA = +25°C 4.067 TCVFS PSR 4.5V ≤ VDD ≤ 5.5V mV µV/°C 4.092 4.117 V 10 55 ppm/°C 175 DC Crosstalk (Note 4) 500 µV 100 µV REFERENCE Output-Voltage Output Voltage Temperature Coefficient (Note 3) Reference External Load Regulation VREF 2.465 V TCVREF 10 ppm/°C VOUT/IOUT 0 ≤ IOUT ≤ 100µA (sourcing) 0.1 Reference Short-Circuit Current 2 4 µV/µA mA DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis VIH 0.7 x VDD V VIL 0.3 x VDD VHYS Input Leakage Current IIN Input Capacitance CIN 200 ±1 Digital inputs = 0 or VDD V mV 8 µA pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 2 4.25 _______________________________________________________________________________________ V 0.2 V 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference (VDD = +4.5V to +5.5V, VOS_ = VAGND = VDGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR To ±0.5LSB, VSTEP = ±4V Voltage-Output Settling Time (VDD - 0.25V) ≥ VOUT ≥ 0.25V Output-Voltage Swing (Note 5) OS_ Input Resistance ROS 83 0.6 V/µs 10 µs 0 to VDD V 121 kΩ Time Required for Output to Settle After Turning on VDD (Note 6) 95 400 µs Time Required for Output to Settle After Exiting Full Power-Down (Note 6) 95 400 µs Time Required for Output to Settle After Exiting DAC Power-Down (Note 6) 12 160 µs CS = VDD, fSCLK = 100kHz, VSCLK = 5VP-P Digital Feedthrough Major-Carry Glitch Energy 5 nV-s 90 nV-s POWER SUPPLIES Power-Supply Voltage VDD Power-Supply Current (Note 7) IDD Power-Supply Current in Power-Down and Shutdown Modes (Note 7) 4.5 470 5.5 V 525 µA Full power-down mode 1.4 5 One DAC shutdown mode 350 390 Both DACs shutdown mode 235 260 µA ELECTRICAL CHARACTERISTICS—MAX5232 (VDD = +2.7V to +3.6V, VOS_ = VAGND = VDGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Resolution SYMBOL CONDITIONS N MIN TYP MAX 10 UNITS Bits Integral Nonlinearity (Note 1) INL ±0.5 LSB Differential Nonlinearity DNL ±1 LSB Offset Error (Note 2) ±3 VOS Offset-Temperature Coefficient (Note 3) Full-Scale Voltage TCVOS VFS Full-Scale Temperature Coefficient (Notes 3 and 6) Power-Supply Rejection DC Crosstalk (Note 4) 8 Code = 3FF hex, TA = +25°C TCVFS PSR 2.7V ≤ VDD ≤ 3.6V 2.0335 mV µV/°C 2.0460 2.0585 V 10 55 ppm/°C 175 500 µV 100 µV _______________________________________________________________________________________ 3 MAX5232/MAX5233 ELECTRICAL CHARACTERISTICS—MAX5233 (continued) MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference ELECTRICAL CHARACTERISTICS—MAX5232 (continued) (VDD = +2.7V to +3.6V, VOS_ = VAGND = VDGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE Output Voltage Output-Voltage Temperature Coefficient (Note 3) Reference External Load Regulation VREF 1.234 V TCVREF 10 ppm/°C VOUT/IOUT 0 ≤ IOUT ≤ 100µA (sourcing) 0.1 Reference Short-Circuit Current 2 4 µV/µA mA DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis VIH 0.7 x VDD V VIL 0.3 x VDD VHYS Input Leakage Current IIN Input Capacitance CIN 200 ±1 Digital inputs = 0 or VDD V mV 8 µA pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 2.3 V 0.25 V DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR To ±0.5 LSB, VSTEP = ±2V (VDD - 0.25V) ≥ VOUT ≥ 0.25V Voltage-Output Settling Time Output-Voltage Swing (Note 5) OS_ Input Resistance ROS 83 0.6 V/µs 10 µs 0 to VDD V 121 kΩ Time Required for Output to Settle After Turning on VDD (Note 6) 95 400 µs Time Required for Output to Settle After Exiting Full Power-Down (Note 6) 95 400 µs Time Required for Output to Settle After Exiting DAC Power-Down (Note 6) 12 160 µs Digital Feedthrough Major-Carry Glitch Energy 4 CS =VDD, fSCLK = 100kHz, VSCLK = 3VP-P 5 nV-s 90 nV-s _______________________________________________________________________________________ 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference (VDD = +2.7V to +3.6V, VOS_ = VAGND = VDGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.6 V 420 475 µA POWER SUPPLIES Power-Supply Voltage VDD Power-Supply Current (Note 7) IDD Power-Supply Current in Power-Down and Shutdown Modes (Note 7) 2.7 Full power-down mode 0.9 5 One DAC shutdown mode 320 360 Both DACs shutdown mode 220 245 µA Note 1: Accuracy is guaranteed as shown in the following table: ACCURACY GUARANTEED VDD (V) FROM CODE TO CODE 3 6 1023 5 3 1023 Note 2: Offset is measured at the code closest to 12mV. Note 3: Temperature coefficient is determined by the box method in which the maximum ΔVOUT over the temperature range is divided by ΔT. Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change DAC B to full scale, and measure ΔVOUT for DAC A. Repeat the same measurement with DAC A and DAC B interchanged. DC crosstalk is the maximum ΔVOUT measured. Note 5: Accuracy is better than 1LSB for VOUT_ = 12mV to VDD - 180mV. Note 6: Guaranteed by design, not production tested. Note 7: RLOAD = ∞ and digital inputs are at either VDD or DGND. TIMING CHARACTERISTICS—MAX5233 (VDD = +4.5V to +5.5V, VAGND = VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figures 1 and 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Clock Period tCP 74 ns SCLK Pulse Width High tCH 30 ns SCLK Pulse Width Low tCL 30 ns CS Fall to SCLK Rise Setup Time tCSS 30 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns DIN Setup Time tDS 30 ns DIN Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay Time tDO1 SCLK Fall to DOUT Valid Propagation Delay Time tDO2 CLOAD = 200pF 45 CLOAD = 100pF 30 CLOAD = 200pF 45 CLOAD = 100pF 30 100 100 ns ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 30 ns CS Pulse Width High tCSW 75 ns LDAC Pulse Width Low tLDL 30 ns 40 ns CS Rise to LDAC Rise Hold Time tCSLD (Note 8) _______________________________________________________________________________________ 5 MAX5232/MAX5233 ELECTRICAL CHARACTERISTICS—MAX5232 (continued) TIMING CHARACTERISTICS—MAX5232 (VDD = +2.7V to +3.6V, VAGND = VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figures 1 and 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Clock Period tCP 74 ns SCLK Pulse Width High tCH 30 ns SCLK Pulse Width Low tCL 30 ns CS Fall to SCLK Rise Setup Time tCSS 30 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns DIN Setup Time tDS 30 ns DIN Hold Time tDH 0 ns CLOAD = 200pF 60 CLOAD = 100pF 45 CLOAD = 200pF 60 CLOAD = 100pF 45 200 SCLK Rise to DOUT Valid Propagation Delay Time tDO1 SCLK Fall to DOUT Valid Propagation Delay Time tDO2 SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 30 ns CS Pulse Width High tCSW 75 ns 30 ns 75 ns LDAC Pulse Width Low CS Rise to LDAC Rise Hold Time tLDL tCSLD (Note 8) 200 ns ns Note 8: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register contents. Typical Operating Characteristics (VDD = +3V (MAX5232), VDD = +5V (MAX5233), RL = 5kΩ, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25°C, unless otherwise noted.) 0.025 INL (LSB) 0.025 0.050 0 0 -0.025 -0.025 -0.050 -0.050 -0.075 -0.075 0.025 DNL (LSB) 0.050 0.050 MAX5232/MAX5233 toc02 0.075 MAX5232/MAX5233 toc01 0.075 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5232) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5233) MAX5232/MAX5233 toc03 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5232) INL (LSB) MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference 0 -0.025 -0.050 0 125 250 375 500 625 750 875 1000 DIGITAL INPUT CODE 6 0 125 250 375 500 625 750 875 1000 DIGITAL INPUT CODE 0 125 250 375 500 625 750 875 1000 DIGITAL INPUT CODE _______________________________________________________________________________________ 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference 0 -0.025 430 420 450 440 -0.075 -40 125 250 375 500 625 750 875 1000 420 400 400 0 430 410 410 -0.050 MAX5232/MAX5233 toc06 440 -15 10 35 60 -40 85 -15 10 35 60 85 DIGITAL INPUT CODE TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5232) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5233) FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5232) 415 410 480 475 470 MAX5232/MAX5233 toc09 420 485 0.80 0.75 SUPPLY CURRENT (μA) 425 490 SUPPLY CURRENT (μA) MAX5232/MAX5233 toc07 430 MAX5232/MAX5233 toc08 DNL (LSB) 0.025 MAX5232/MAX5233 toc05 0.050 450 SUPPLY CURRENT (μA) MAX5232/MAX5233 toc04 0.075 SUPPLY CURRENT (μA) SUPPLY CURRENT vs. TEMPERATURE (MAX5233) SUPPLY CURRENT vs. TEMPERATURE (MAX5232) SUPPLY CURRENT (μA) DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (MAX5233) 0.70 0.65 0.60 0.55 0.50 405 465 400 460 2.7 3.0 3.6 3.3 NO LOAD 0.40 4.50 4.75 5.00 5.25 -40 5.50 -15 10 35 60 85 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C) TWO-DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5232) ONE-DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5232) FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5233) 215 210 320 315 310 MAX5232/MAX5233 toc12 325 1.2 1.1 SUPPLY CURRENT (μA) 220 MAX5232/MAX5233 toc11 225 330 SUPPLY CURRENT (μA) MAX5232/MAX5233 toc10 230 SUPPLY CURRENT (μA) 0.45 1.0 0.9 0.8 0.7 0.6 205 305 0.5 NO LOAD NO LOAD 200 NO LOAD 0.4 300 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX5232/MAX5233 Typical Operating Characteristics (continued) (VDD = +3V (MAX5232), VDD = +5V (MAX5233), RL = 5kΩ, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25°C, unless otherwise noted Typical Operating Characteristics (continued) (VDD = +3V (MAX5232), VDD = +5V (MAX5233), RL = 5kΩ, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25°C, unless otherwise noted 240 235 375 230 370 365 360 355 -15 2.0470 2.0465 NO LOAD 2.0460 350 10 35 60 85 -40 -15 10 35 60 -40 85 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) FULL-SCALE OUTPUT VOLTAGE vs. TEMPERATURE (MAX5233) FULL-SCALE ERROR vs. RESISTIVE LOAD (MAX5232) FULL-SCALE ERROR vs. RESISTIVE LOAD (MAX5233) 4.0925 4.0920 0.08 0.07 0.06 MAX5232/MAX5233 toc18 4.0930 0.06 0.05 FULL-SCALE ERROR (LSB) 4.0935 0.09 MAX5232/MAX5233 toc17 MAX5232/MAX5233 toc16 4.0940 FULL-SCALE ERROR (LSB) -40 2.0475 NO LOAD NO LOAD 225 0.05 0.04 0.03 0.04 0.03 0.02 0.02 4.0915 4.0910 0.01 CHANGE FROM NO LOAD 0.01 NO LOAD -15 10 35 60 85 CHANGE FROM NO LOAD 0 0 -40 2.5 3.5 4.5 5.5 6.5 TEMPERATURE (°C) RESISTIVE LOAD (kΩ) DYNAMIC RESPONSE RISE TIME (MAX5232) DYNAMIC RESPONSE RISE TIME (MAX5233) MAX5232/MAX5233 toc19 2.5 7.5 3.5 4.5 6.5 7.5 DYNAMIC RESPONSE FALL TIME (MAX5232) MAX5232/MAX5233 toc21 MAX5232/MAX5233 toc20 3V VCS 2V/div 5V VCS 5V/div 0 0 0 2.048V 4.096V 2.048V VOUT 500mV/div VOUT 500mV/div VOUT 1V/div 10mV 2μs/div 5.5 RESISTIVE LOAD (kΩ) 3V VCS 2V/div 8 2.0480 MAX5232/MAX5233 toc15 245 MAX5232/MAX5233 toc14 SUPPLY CURRENT (μA) 250 380 SUPPLY CURRENT (μA) MAX5232/MAX5233 toc13 255 FULL-SCALE OUTPUT VOLTAGE vs. TEMPERATURE (MAX5232) ONE-DAC SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5233) FULL-SCALE OUTPUT VOLTAGE (V) TWO-DACs SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5233) FULL-SCALE OUTPUT VOLTAGE (V) MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference 10mV 10mV 2μs/div 2μs/div _______________________________________________________________________________________ 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5232/MAX5233 Typical Operating Characteristics (continued) (VDD = +3V (MAX5232), VDD = +5V (MAX5233), RL = 5kΩ, CL = 100pF, OS_ = AGND, both DACs enabled with full-scale output code, TA = +25°C, unless otherwise noted DYNAMIC RESPONSE FALL TIME (MAX5233) MAX5232/MAX5233 toc22 MAX5232/MAX5233 toc24 MAX5232/MAX5233 toc23 5V VCS 5V/div ANALOG CROSSTALK (MAX5233) ANALOG CROSSTALK (MAX5232) OUTA 2V/div OUTA 5V/div OUTB 5mV/div AC-COUPLED OUTB 5mV/div AC-COUPLED 0 4.096V VOUT 1V/div 10mV 2μs/div 400μs/div 400μs/div DIGITAL FEEDTHROUGH (MAX5232) DIGITAL FEEDTHROUGH (MAX5233) MAJOR-CARRY TRANSITION (MAX5232) MAX5232/MAX5233 toc25 MAX5232/MAX5233 toc27 MAX5232/MAX5233 toc26 SCLK 2V/div SCLK 5V/div OUTA 1mV/div AC-COUPLED OUTA 1mV/div AC-COUPLED CS 5V/div OUTA 100mV/div AC-COUPLED 10μs/div 10μs/div 2μs/div MAJOR-CARRY TRANSITION (MAX5233) REFERENCE VOLTAGE vs. TEMPERATURE (MAX5232) REFERENCE VOLTAGE vs. TEMPERATURE (MAX5233) OUTA 100mV/div AC-COUPLED 1.2345 1.2340 1.2335 2.4630 MAX5232/MAX5233 toc30 MAX5232/MAX5233 toc29 REFERENCE VOLTAGE (V) CS 5V/div 1.2350 REFERENCE VOLTAGE (V) MAX5232/MAX5233 toc28 2.4625 2.4620 2.4615 NO LOAD NO LOAD 2.4610 1.2330 2μs/div -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 9 MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference Pin Description PIN NAME 1 OSA FUNCTION 2 OUTA DAC A Output 3 RSTV Reset Value Input 1: Connect to VDD to select midscale as the reset value. 0: Connect to DGND to select zero as the reset value. 4 LDAC Load DACs A and B 5 CLR Clear Input. Both DAC outputs go to zero or midscale. Clears both DAC internal registers (input register and DAC register) to its predetermined (RSTV) state. 6 CS Chip-Select Input 7 DIN Serial Data Input. Data is clocked in on the rising edge of SCLK. 8 SCLK DAC A Offset Adjust Serial Clock Input 9 DGND Digital Ground 10 DOUT Serial Data Output 11 PDL Power-Down Lockout. Disables shutdown of both DACs when low. 12 REF Reference Output. Reference provides a 2.465V (MAX5233) or 1.234V (MAX5232) nominal output. 13 AGND 14 VDD 15 OUTB 16 OSB Analog Ground Positive Power Supply. Bypass VDD with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND, and bypass VDD with a 0.1µF capacitor to DGND. DAC B Output DAC B Offset Adjust COMMAND EXECUTED CS SCLK 1 DIN C2 8 C1 DOUT (MODE 0) DOUT (MODE 1) C0 D9 D8 D7 D6 D5 9 D4 16 D3 D2 D1 D0 S2 S1 (1) S0 C2 C2 C1 C1 Figure 1. Serial Interface Timing 10 ______________________________________________________________________________________ 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference MAX5232/MAX5233 tLDL tCSLD LDAC tCSW CS tCSO tCSS tCSH tCS1 SCLK tCH tCL tCP DIN tDS tD01 tDH tD02 DOUT Figure 2. Detailed Serial Interface Timing Detailed Description The MAX5232/MAX5233 10-bit, voltage-output DACs are easily configured with a 3-wire SPI-, QSPI-, MICROWIRE-compatible serial interface. The devices include a 16-bit data-in/data-out shift register and have an input consisting of an input register and a DAC register. In addition, these devices employ precision trimmed internal resistors to produce a gain of 1.6384V/V, maximizing the output voltage swing, and a programmable-shutdown output impedance of 1kΩ or 200kΩ The full-scale output voltage is 4.092V for the MAX5233 and 2.046V for the MAX5232. These devices produce a weighted output voltage proportional to the digital input code with an inverted rail-to-rail ladder network (Figure 3). 0.6V/µs and settle to 1/2LSB within 10µs with a load of 5kΩ in parallel with 100pF. Use the serial interface to set the shutdown output impedance of the amplifiers to 1kΩ or 200kΩ. OS_ can be used to produce an offset voltage at the output. For instance, to achieve a 1V offset, apply -1V to OS_ to produce an output range from 1V to (1V + VFS/VREF). Note that the DAC’s output range is still limited by the maximum output voltage specification. OS_ 121kΩ 77.25kΩ Internal Reference The MAX5232/MAX5233 use an on-board precision bandgap reference to generate an output voltage of 1.234V (MAX5232) or 2.465V (MAX5233). With a low temperature coefficient of only 10ppm/°C, REF can source up to 100µA and is stable for capacitive loads less than 200pF. Output Amplifiers The output amplifiers have internal resistors that provide for a gain of 1.6384V/V when OS_ is connected to AGND. The output amplifiers have a typical slew rate of R 2R R OUT_ R 2R 2R 2R 2R D0 D7 D8 D9 1kΩ REF AGND SHOWN FOR ALL ONES ON DAC Figure 3. Simplified DAC Circuit Diagram ______________________________________________________________________________________ 11 MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference ously. The control bits and D9–D6 allow the DACs to operate independently. Table 1. Serial Data Format MSB <------------16-bits of serial data ------------> LSB 3 Control Bits MSB .. 10 Data Bits ... LSB Sub-Bit C2…C0 D9 ................................D0 S2, S1, S0 Serial Interface The 3-wire serial interface (SPI, QSPI, MICROWIRE compatible) used in the MAX5232/MAX5233 allows for complete control of DAC operations (Figures 4 and 5). Figures 1 and 2 show the timing for the serial interface. The serial word consists of 3 control bits followed by 10 data bits (MSB first) and 1 sub-bit as described in Tables 1, 2, and 3. When the three control bits are all zeros or all 1, D9–D6 are used as additional control bits, allowing for greater DAC functionality. The digital inputs allow any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC register(s) simultane- Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, MICROWIRE), with CS low during this period. The control bits and D9–D6 determine which registers update and the state of the registers when exiting shutdown. The 3-bit control and D9–D6 determine the following: • Registers to be updated • Selection of the power-down and shutdown modes The general timing diagram of Figure 1 illustrates data acquisition. Driving CS low enables the device to receive data. Otherwise the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers, depending on the control bits and D9–D6. The maximum clock frequency guaranteed for proper operation is 13.5MHz. Figure 2 depicts a more detailed timing diagram of the serial interface. Table 2. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION C2 C1 C0 D9..............D0 S2–S0 0 0 1 10-bit DAC data 000 Load input register A; DAC registers are unchanged. 0 1 0 10-bit DAC data 000 Load input register A; all DAC registers are updated. 0 1 1 10-bit DAC data 000 Load all DAC registers from the shift register (start up both DACs with new data, and load the input registers). 1 0 0 XXXXXXXXXX 000 Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). 1 0 1 10-bit DAC data 000 Load input register B; DAC registers are unchanged. 1 1 0 10-bit DAC data 000 Load input register B; all DAC registers are updated. 1 1 1 P1A P1B X X X X X X X X 000 Shut down both DACs, respectively, according to bits P1A and P1B (see Table 3). Internal bias and reference remain active. 0 0 0 001XXXXXXX 000 Update DAC register A from input register A (start up DAC A with data previously stored in input register A). 0 0 0 0 1 1 P1A P1B X X X X X 000 Full Power-Down. Power down the main bias generator and shut down both DACs, respectively, according to bits P1A and P1B (see Table 3). 0 0 0 101XXXXXXX 000 Update DAC register B from input register B (start up DAC B with data previously stored in input register B). 0 0 0 1 1 0 P1A X X X X X X 000 Shut down DAC A according to bit P1A (see Table 3). 0 0 0 1 1 1 P1B X X X X X X 000 Shut down DAC B according to bit P1B (see Table 3). 0 0 0 1000XXXXXX 000 Mode 0. DOUT clocked out on SCLK falling edge (default). 0 0 0 1001XXXXXX 000 Mode 1. DOUT clocked out on SCLK rising edge. X = Don’t care. * S0 must be zero for proper operation. 12 ______________________________________________________________________________________ 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference Full power-down mode shuts down the main bias generator, reference, and both DACs. The shutdown impedance of the DAC outputs can still be controlled independently, as described in Tables 2 and 3. A serial interface command exits shutdown mode and updates a DAC register. Each DAC can exit shutdown at the same time or independently (see Tables 2 and 3). For example, if both DACs are shut down, updating the DAC A register causes DAC A to power up, while DAC B remains shutdown. In full power-down mode, powering up either DAC also powers up the main bias generator and reference. To change from full powerdown to both DACs shutdown requires the waking of at least one DAC between states. When powering up the MAX5232/MAX5233 (powering VDD), allow 400µs (max) for the output to stabilize. When exiting full power-down mode, also allow 400µs (max) for the output to stabilize. When exiting DAC shutdown mode, allow 160µs (max) for the output to stabilize. Reset Value (RSTV) and Clear (CLR) Inputs Driving CLR low asynchronously forces both DAC outputs and all the internal registers (input registers and DAC registers) for both DACs to either zero or midscale, depending on the level at RSTV. RSTV = DGND sets the zero value, and RSTV = VDD sets the midscale value. The internal power-on reset circuit sets the DAC outputs and internal registers to either zero or midscale when power is first applied to the device, depending on the level at RSTV as described in the preceding paragraph. The DAC outputs are enabled after power is first applied. In order to obtain the midscale value on power-up (RSTV = VDD), the voltage on RSTV must rise simultaneously with the VDD supply. Table 3. P1 Shutdown Modes P1 (A/B) SHUTDOWN MODE 0 Shut down with internal 1kΩ load to GND 1 Shut down with internal 200kΩ load to GND MAX5232/MAX5233 Power-Down and Shutdown Modes As described in Tables 2 and 3, several serial interface commands put one or both of the DACs into shutdown mode. Shutdown modes are completely independent for each DAC. In shutdown, the amplifier output becomes high impedance, and OUT_ terminates to OS_ through the 200kΩ (typ) gain resistors. Optionally (see Tables 2 and 3), OUT_ can have an additional termination of 1kΩ to AGND. 5V SS DIN MAX5232 MAX5233 MOSI SCLK SCK CS I/O SPI/QSPI PORT Figure 4. SPI/QSPI Interface Connections MAX5232 MAX5233 SCLK SK DIN SO CS I/O MICROWIRE PORT Figure 5. Connections for MICROWIRE Load DAC Input (LDAC) Asserting LDAC asynchronously loads the DAC registers from their corresponding input registers (DACs that are shut down remain shut down). The LDAC input is totally asynchronous and does not require any activity on CS, SCLK, or DIN in order to take effect. If LDAC is asserted coincident with a rising edge of CS, which executes a serial command modifying the value of either DAC input register, then LDAC must remain asserted for at least 30ns following the CS rising edge. This requirement applies only for serial commands that modify the value of the DAC input registers. Power-Down Lockout Input (PDL) Driving PDL low disables shutdown of either DAC. When PDL is low, serial commands to shut down either DAC are ignored. When either DAC is in shutdown mode, a highto-low transition on PDL brings the DACs and the reference out of shutdown with DAC outputs set to the state prior to shutdown. ______________________________________________________________________________________ 13 Applications Information Definitions Integral Nonlinearity (INL) Integral nonlinearity (Figure 6a) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every single step. Differential Nonlinearity (DNL) Differential nonlinearity (Figure 6b) is the difference between an actual step height and the ideal value of 1LSB. If the magnitude of the DNL is less than 1LSB, the DAC guarantees no missing codes and is monotonic. Offset Error The offset error (Figure 6c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated for by trimming. Gain Error Gain error (Figure 6d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Settling Time The settling time is the amount of time required from the start of a transition, until the DAC output settles to its new output value within the converter’s specified accuracy. 7 6 ANALOG OUTPUT VALUE (LSB) ANALOG OUTPUT VALUE (LSB) 6 5 4 AT STEP 011 (1/2LSB ) 3 2 AT STEP 001 (1/4LSB ) 1 1LSB 5 DIFFERENTIAL LINEARITY ERROR (-1/4LSB) 4 3 1LSB 2 DIFFERENTIAL LINEARITY ERROR (+1/4LSB) 1 0 0 000 001 010 011 100 101 110 111 000 001 DIGITAL INPUT CODE ACTUAL OFFSET OFFSET ERROR POINT (+1 1/4LSB) IDEAL OFFSET POINT 000 001 010 ANALOG OUTPUT VALUE (LSB) IDEAL DIAGRAM 0 14 101 GAIN ERROR (-1 1/4LSB) 6 IDEAL DIAGRAM ACTUAL FULL-SCALE OUTPUT 5 4 0 011 000 100 101 110 DIGITAL INPUT CODE DIGITAL INPUT CODE Figure 6c. Offset Error 100 IDEAL FULL-SCALE OUTPUT 7 2 1 011 Figure 6b. Differential Nonlinearity ACTUAL DIAGRAM 3 010 DIGITAL INPUT CODE Figure 6a. Integral Nonlinearity ANALOG OUTPUT VALUE (LSB) MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference Figure 6d. Gain Error ______________________________________________________________________________________ 111 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference DAC CONTENTS V+ ANALOG OUTPUT (V) MSB LSB MAX5232 MAX5233 1111 1111 11 (000) 2.046 4.092 1000 0000 01 (000) 1.025 2.050 1000 0000 00 (000) 1.023 2.046 0111 1111 11 (000) 1.021 2.042 0000 0000 01 (000) 0.002 0.004 0000 0000 00 (000) 0 0 5V/3V REF PHOTODIODE VDD REF OS_ 121kΩ V+ 77.25kΩ VOUT OUT_ DAC_ V- Digital Feedthrough Digital feedthrough is noise generated on the DAC’s output when any digital input transitions. Proper board layout and grounding significantly reduce this noise, but there is always some feedthrough caused by the DAC itself. MAX5232 MAX5233 AGND 1kΩ RPULLDOWN DGND Unipolar Output Figure 7 shows the MAX5232/MAX5233 configured for unipolar, rail-to-rail operation. The MAX5233 produces a 0 to 4.092V output, while the MAX5232 produces 0 to 2.046V output. Table 4 lists the unipolar output codes. 5V/3V REF VDD REF OS_ 121kΩ 77.25kΩ MAX5232 MAX5233 AGND 1kΩ DGND Digital Calibration and Threshold Selection Figure 8 shows the MAX5232/MAX5233 in a digital calibration application. With a bright light value applied to the photodiode (on), the DAC is digitally ramped until it trips the comparator. The microprocessor (µP) stores this high calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The µP then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis. Sharing a Common DIN Line OUT_ DAC_ Figure 8. Digital Calibration Several MAX5232/MAX5233s may share one common DIN signal line (Figure 9). In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. The SCLK and DIN lines are shared by all devices, but each IC needs its own dedicated CS line. Daisy-Chaining Devices Any number of MAX5232/MAX5233s can be daisychained by connecting the serial data output (DOUT) of one device to the digital input (DIN) of the following device in the chain (Figure 10). Figure 7. Unipolar Output Circuit (Rail-to-Rail) ______________________________________________________________________________________ 15 MAX5232/MAX5233 Table 4. Unipolar Code Table MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS MAX5232 MAX5233 CS MAX5232 MAX5233 MAX5232 MAX5233 SCLK SCLK SCLK DIN DIN DIN Figure 9. Multiple MAX5232/MAX5233s Sharing a Common DIN Line SCLK CS CS CS MAX5232 MAX5233 SCLK DIN DIN CS MAX5232 MAX5233 SCLK DOUT DIN TO OTHER SERIAL DEVICES MAX5232 MAX5233 SCLK DOUT DIN DOUT Figure 10. Daisy-Chaining MAX5232/MAX5233 Devices Power-Supply and Bypassing Considerations On power-up, the input and DAC registers are cleared to either zero (RSTV = DGND) or midscale (RSTV = VDD). Bypass VDD with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND, and bypass VDD with a 0.1µF capacitor to DGND. Minimize lead lengths to reduce lead inductance. Grounding and Layout Considerations Digital and AC transient signals on AGND or DGND can create noise at the output. Connect AGND and DGND to the highest quality ground available. Use proper 16 grounding techniques, such as a multilayer board with a low-inductance ground plane or star connect all ground return paths back to the MAX5232/MAX5233 AGND. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. Chip Information TRANSISTOR COUNT: 4745 PROCESS: BiCMOS ______________________________________________________________________________________ 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference CS DOUT DIN SCLK VDD AGND DGND 121kΩ OSA 77.25kΩ AMP A DAC A PDL SR CONTROL OUTA 16-BIT SHIFT REGISTER 1kΩ 1kΩ SHUTDOWN LDAC RSTV CLR DECODE CONTROL 121kΩ OSB 12 77.25kΩ INPUT REGISTERS DAC REGISTER AMP B DAC B OUTB 1kΩ SHUTDOWN BANDGAP REFERENCE 1.25V 2X (1X) 2.5V (1.25V) REFERENCE BUFFER ( ) FOR MAX5232 ONLY MAX5232 MAX5233 REF Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 16 QSOP E16+5 21-0055 ______________________________________________________________________________________ 17 MAX5232/MAX5233 Functional Diagram MAX5232/MAX5233 3V/5V, 10-Bit, Serial Voltage-Output Dual DACs with Internal Reference Revision History REVISION NUMBER REVISION DATE 0 1/02 Initial release 2 5/09 Added lead-free packaging and changed spec DESCRIPTION PAGES CHANGED — 1, 2. 3 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.