SHARP LH28F020SU-N

LH28F020SU-N
FEATURES
• 256K × 8 Bit Configuration
• 5 V Write/Erase Operation (5 V VPP)
– No Requirement for DC/DC Converter to
Write Erase
•
•
•
•
2M (256K × 8) Flash Memory
32-PIN TSOP
TOP VIEW
A11
1
32
A9
2
31
A10
A8
3
30
CE
OE
A13
4
29
DQ7
80 ns Maximum Access Time
A14
5
28
DQ6
16 Independently Lockable Blocks (16K)
A17
6
27
DQ5
100,000 Erase Cycles per Block
Automated Byte Write/Block Erase
– Command User Interface
– Status Register
• System Performance Enhancement
– Erase Suspend for Read
– Two-Byte Write
– Full Chip Erase
WE
7
26
DQ4
VCC
8
25
DQ3
VPP
9
24
GND
A16
10
23
DQ2
A15
11
22
DQ1
A12
12
21
DQ0
A7
13
20
A0
A6
14
19
A1
A5
15
18
A2
A4
16
17
A3
• Data Protection
28F020SUN80-1
– Hardware Erase/Write Lockout during
Power Transitions
– Software Erase/Write Lockout
• Independently Lockable for Write/Erase on
Each Block (Lock Block and Protect
Set/Reset)
• 5 µA (TYP.) ICC in CMOS Standby
• State-of-the-Art 0.55 µm ETOX™ Flash
Technology
• Packages
– 32-Pin, 525 mil. SOP Package
– 32-Pin, 1.2 mm × 8 mm × 20 mm
TSOP (Type I) Package
Figure 1. TSOP Configuration
32-PIN SOP
TOP VIEW
VPP
1
32
VCC
A16
2
31
WE
A15
3
30
A17
A12
4
29
A14
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A11
A4
8
25
A3
9
24
OE
A2
10
23
A10
22
CE
A1
11
A0
12
21
DQ7
DQ0
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
GND
16
17
DQ3
28F020SUN80-20
Figure 2. SOP Configuration
1
LH28F020SU-N
2M (256K × 8) Flash Memory
DQ0 - DQ7
OUTPUT
BUFFER
INPUT
BUFFER
DATA
QUEUE
REGISTER
ID
REGISTER
I/O
LOGIC
CSR
OUTPUT
MULTIPLEXER
REGISTER
ESRs
CE
OE
CUI
WE
DATA
COMPARATOR
ADDRESS
COUNTER
16KB BLOCK 15
...
16KB BLOCK 14
X-DECODER
16KB BLOCK 1
ADDRESS
QUEUE
LATCH
Y GATING/SENSING
Y-DECODER
16KB BLOCK 0
INPUT
BUFFER
...
A0 - A17
...
WSM
PROGRAM/
ERASE
VOLTAGE
SWITCH
VPP
VCC
GND
28F020SUN80-2
Figure 3. LH28F020SU-N Block Diagram
2
2M (256K × 8) Flash Memory
LH28F020SU-N
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A0 - A13
INPUT
BYTE-SELECT ADDRESSES: Select a byte within one 16K block. These
addresses are latched during Data Writes.
A14 - A17
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 16 Erase Blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
DQ0 - DQ7
INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.
CE »
INPUT
CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders
and sense amplifiers. CE » must be low to select the device.
OE »
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE » is high.
WE
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
VPP
SUPPLY
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks
or writing words/bytes/pages into the flash array.
VCC
SUPPLY
DEVICE POWER SUPPLY (5.0 V ±0.5 V): Do not leave any power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
INTRODUCTION
Description
Sharp’s LH28F020SU-N 2M Flash Memory is a revolutionary architecture which enables the design of truly
mobile, high performance, personal computing and communication products. With innovative capabilities, 5.0 V
single voltage operations and very high read/write performance, the LH28F020SU-N is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F020SU-N is a high performance 2M
(2,097,152 bit) block erasable non-volatile random
access memor y organized as 256K × 8. The
LH28F020SU-N includes sixteen 16K (16,384) blocks.
A chip memory map is shown in Figure 4.
The LH28F020SU-N is a very high density, highest
performance non-volatile read/write solution for solidstate storage applications. Its independently lockable
16 symmetrical blocked architecture (16K each)
extended cycling, low power operation, very fast write
and read performance and selective block locking provide a highly flexible memory component suitable for
high density memory cards, Resident Flash Arrays and
PCMCIA-ATA Flash Drives. The LH28F020SU-N single
voltage power supply operation enables the design of
memory cards which can be read/written in 5.0 V systems. Its x8 architecture allows the optimization of
memory to processor interface. The flexible block locking option enables bundling of executable application
software in a Resident Flash Array or memory card.
Manufactured on Sharp’s 0.55 µm ETOX™ process
technology, the LH28F020SU-N is the most costeffective, high density 5.0 V flash memory.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F020SU-N80:
• 5 V Read, Write/Erase Operation
(5 V VCC, 5.0 V VPP)
•
•
•
•
Lower Power Capability
Improved Write Performance
Dedicated Block Write/Erase Protection
Command-Controlled Memory Protection
Set/Reset Capability
The LH28F020SU-N will be available in a 32-pin,
525 mil. SOP package. This form factor and pinout allow for very high board layout densities.
3
LH28F020SU-N
The LH28F020SU-N will be available in a 32-pin, 1.2
mm thick, 8 mm × 20 mm TSOP (Type I) package. This
form factor and pinout allow for very high board layout
densities.
A Command User Interface (CUI) serves as the system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a TwoWrite command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Software Locking of Memory Blocks
• Memory Protection Set/Reset Capability
• Two-Byte Serial Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed typically within
13 µs. A Block Erase operation erases one of the 16
blocks in typically 0.6 seconds, independent of the other
blocks.
LH28F020SU-N allows to erase all unlocked blocks.
It is desirable in case you have to implement Erase
operation maximum 16 times.
LH28F020SU-N enables two-byte serial Write
which is operated by three times command input. This
feature can improve system write performance by up to
typically 10 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) provide information on the progress of the
requested operation.
Same as the LH28F008SA, LH28F020SU-N
requires an operation to complete before the next
operation can be requested, also it allows to suspend
block erase to read data from any other block, and allow to resume erase operation.
The LH28F020SU-N provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or
Application Code. Each block has an associated
non-volatile lock-bit which determines the lock status of
the block. In addition, the LH28F020SU-N has a software controlled master Write Protect circuit which prevents any modifications to memory blocks whose
lock-bits are set.
4
2M (256K × 8) Flash Memory
When the device power-up, Write Protect Set/
Confirm command must be written. Otherwise, all lock
bits in the device remain being locked, can’t perform
the Write to each block and single Block Erase. Write
Protect Set/Confirm command must be written to
reflect the actual lock status. However, when the device
power-on, Erase All Unlocked Blocks can be used. If
used, Erase is performed with reflecting actual lock status, and after that Write and Block Erase can be used.
The LH28F020SU-N contains Status Register to
accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capability to the LH28F020SU-N from a LH28F008SA
based design.
The LH28F020SU-N is specified for a maximum
access time of 80 ns (tACC) at 5 V operation (4.5 to
5.5 V) over the commercial temperature range (0 to
+70°C).
The LH28F020SU-N incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 2 mA at 5.0 V.
A chip reset mode of operation is enabled when CE »,
WE » and OE » hold low more than 5 µs. In this mode, all
operations are aborted, WSM is reset and CSR register is cleared. If CE » and or WE » and or OE » and or goes
high, chip reset mode will be finished. It needs more
than 500 ns from one of the CE », WE » or OE » goes high
until output data are valid.
A CMOS Standby mode of operations is enabled
when CE » transitions high will all input control pins at
CMOS levels. In this mode, the device draws an ICC
standby current of 10 µA.
2M (256K × 8) Flash Memory
LH28F020SU-N
MEMORY MAP
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
16KB BLOCK
15
16KB BLOCK
14
16KB BLOCK
13
16KB BLOCK
12
16KB BLOCK
11
16KB BLOCK
10
16KB BLOCK
9
16KB BLOCK
8
16KB BLOCK
7
16KB BLOCK
6
16KB BLOCK
5
16KB BLOCK
4
16KB BLOCK
3
16KB BLOCK
2
16KB BLOCK
1
16KB BLOCK
0
28F020SUN80-3
Figure 4. Chip Memory Map
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations
CE »
OE »
WE
A0
DQ0-7
NOTE
Read
VIL
VIL
VIH
X
DOUT
1
Output Disable
VIL
VIH
VIH
X
High-Z
1
Standby
VIH
X
X
X
High-Z
1
Manufacturer ID
VIL
VIL
VIH
VIL
B0H
2
Device ID
VIL
VIL
VIH
VIH
ID
2
Write
VIL
VIH
VIL
X
DIN
1, 3
MODE
NOTES:
1. X can be VIH or VIL for address or control pins, which is either VOL or VOH.
2. A0 at VIL provide manufacturer ID codes. A0 at VIH provide device ID codes.
Device ID Code = 30H. All other addresses are set to zero.
3. Commands for different Erase operations, Data Write operations of Lock-Block
operations can only be successfully completed when VPP = VPPH.
5
LH28F020SU-N
2M (256K × 8) Flash Memory
LH28F008SA - Compatible Mode Command Bus Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
NOTE
OPER.
ADDRESS
DATA
OPER.
ADDRESS
DATA
Read Array
Write
X
FFH
Read
AA
AD
Intelligent Identifier
Write
X
90H
Read
IA
ID
1
Read Compatible Status
Register
Write
X
70H
Read
X
CSRD
2
Clear Status Register
Write
X
50H
Byte Write
Write
X
40H
Write
WA
WD
Alternate Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
4
Erase Suspend/Resume
Write
X
B0H
Write
X
D0H
4
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
3
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions.
4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is
set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure
to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while
the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed.
6
2M (256K × 8) Flash Memory
LH28F020SU-N
LH28F020SUT-N Performance Enhancement Command Bus Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
THIRD BUS CYCLE
COMMAND
NOTE
OPER.
ADD.
DATA
OPER.
ADD.
DATA
Protect Set/Confirm
Write
X
57H
Write
0FFH
D0H
1, 2, 6
Protect
Reset/Confirm
Write
X
47H
Write
0FFH
D0H
3, 6
Lock Block/Confirm
Write
X
77H
Write
BA
D0H
1, 2, 4
Erase All Unlocked
Blocks
Write
X
A7H
Write
X
D0H
1, 2
Two-Byte Write
Write
X
FBH
Write
A0
WD (L, H)
ADDRESS
BA = Block Address
WA = Write Address
X = Don’t Care
OPER.
Write
ADD.
DATA
WA
WD (H, L)
1, 2, 5
DATA
AD = Array Data
WD (L, H) = Write Data (Low, High)
WD (H, L) = Write Data (High, Low)
NOTES:
1. After initial device power-up, or chip reset is completed, the block lock status bits default to the locked state independent of the data in
the corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command.
2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command.
3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits.
4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written.
5. A0 is automatically complemented to load second byte of data A0 value determines which WD is supplied first: A0 = 0 looks at the
WDL, A0 = 1 looks at the WDH.
6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A9 - A8 = 0, A7 - A0 = 1,
others are don’t care.
Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
CSR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
CSR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
NOTES:
1. WSMS bit must be checked to determine completion of
an operation (Erase Suspend, Erase or Data Write) before
the appropriate Status bit (ESS, ES or DWS) is checked for
success.
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPL and VPPH.
4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
7
LH28F020SU-N
2M (256K × 8) Flash Memory
2M FLASH MEMORY
SOFTWARE ALGORITHMS
Reset Write Protect command must be written
before Write Block Lock command. To reflect actual block
lock status, Set Write Protect command is succeeded.
Overview
The Compatible Status Register (CSR) is used to
determine which blocks are locked. In order to see Lock
Status of certain block, a Byte Write command (WA =
Block Address, WD = FFH) is written to the CUI, after
issuing Set Write Protect command. If CSR.7, CSR.5,
and CSR.4 (WSMS, ES and DWS) are set to ‘1’s, the
block is locked. If CSR.7 is set to ‘1’, the block is not
locked.
With the advanced Command User Interface, its Performance Enhancement commands and Status Registers, the software code required to perform a given
operation may become more intensive but it will result
in much higher write/erase performance compared with
current flash memory architectures.
The software flow charts describing how a given
operation proceeds are shown here Figure 5 through
Figure 7 depict flowcharts using the second generation
flash device in the LH28F008SA compatible mode.
Figure 8 through Figure 14 depict flowcharts using the
second generation flash device’s performance enhancement commands mode.
When the device power-up or reset is completed, all
blocks come up locked. Therefore, Byte Write, Two Byte
Serial Write and Block Erase cannot be performed in
each block. However, at that time, Erase All Unlocked
Block is performed normally, if used, and reflect actual
lock status, also the unlocked block data is erased. When
the device power-up or reset is completed, Set Write
Protect command must be written to reflect actual block
lock status.
8
Reset Write Protect command enables Write/Erase
operation to each block.
In the case of Block Erase is performed, the block
lock information is also erased. Block Lock command
and Set Write Protect command must be written to
prohibit Write/Erase operation to each block.
There are unassigned commands. It is not recommended that the customer use any command other than
the valid commands specified in “Command Bus Definitions”. Sharp reserves the right to redefine these codes
for future functions.
2M (256K × 8) Flash Memory
LH28F020SU-N
2M Flash Memory Algorithm Flowcharts
START
WRITE 40H or 10H
BUS
OPERATION
COMMAND
Write
Byte Write
D = 40H or 10H
A=X
Write
D = WD
A = WA
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
COMMENTS
0
Repeat for subsequent Byte Writes.
CSR Full Status Check can be done after each Byte Write,
or after a sequence of Byte Writes.
Write FFH after the last operation to reset device
to read array mode.
See Command Bus Cycle notes for description of codes.
1
CSR FULL STATUS
CHECK IF DESIRED
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
DATA WRITE
SUCCESSFUL
1
CSR.3 =
1
VPP LOW
DETECT
COMMENTS
COMMAND
Standby
Check CSR.4, 5
1 = Data Write Unsuccessful
0 = Data Write Successful
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F020SUN80-4
Figure 5. Byte Writes with Compatible Status Register
9
LH28F020SU-N
2M (256K × 8) Flash Memory
START
WRITE 20H
BUS
OPERATION
COMMAND
Write
Block Erase
D = 20H
A=X
Write
Confirm
D = D0H
A = BA
WRITE D0H AND
BLOCK ADDRESS
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
CSR.7 =
0
SUSPEND YES
ERASE
1
CSR FULL STATUS
CHECK IF DESIRED
COMMENTS
Repeat for subsequent Block Erasures.
CSR Full Status Check can be done after each Block Erase,
or after a sequence of Block Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
CSR.3 =
1
VPP LOW
DETECT
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
ERASE
SUCCESSFUL
1
COMMAND
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F020SUN80-5
Figure 6. Block Erase with Compatible Status Register
10
2M (256K × 8) Flash Memory
LH28F020SU-N
START
WRITE B0H
BUS
OPERATION
COMMAND
Write
Erase
Suspend
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check CSR.6
1 = Erase Suspended
0 = Erase Completed
0
1
CSR.6 =
0
Write
ERASE COMPLETED
Read
Array
Read
1
Write
D = FFH
A=X
Q = AD
Read must be from
block other than the
one suspended.
WRITE FFH
READ ARRAY DATA
D = B0H
A=X
Read
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
COMMENTS
Erase
Resume
D = D0H
A=X
See Command Bus Cycle notes for description of codes.
DONE
READING
NO
YES
WRITE D0H
WRITE FFH
ERASE RESUMED
READ ARRAY DATA
28F020SUN80-6
Figure 7. Erase Suspend to Read Array with Compatible Status Register
11
LH28F020SU-N
2M (256K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
Write
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Reset
Write Protect
Read
1
CSR.7 =
After Write D = 47H A = X,
Write D = D0H A = 0FFH
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
RESET WP
READ COMPATIBLE
STATUS REGISTER
COMMENTS
Write
Lock Block
D = 77H
A=X
Write
Confirm
D = D0H
A = BA
0
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Read
1
WRITE 77H
Write
WRITE D0H AND
BLOCK ADDRESS
Set
Write Protect
After Write D = 57H A = X,
Write D = D0H A = 0FFH
NOTE:
See CSR Full Status Check for Data-Write operation.
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Write FFH after the last operation to reset device to read
array mode.
READ COMPATIBLE
STATUS REGISTER
See Command Bus Definitions for description of codes.
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
0
LOCK
YES
ANOTHER
BLOCK
NO
SET WP
OPERATION COMPLETE
28F020SUN80-7
Figure 8. Block Locking
12
2M (256K × 8) Flash Memory
LH28F020SU-N
START
START
RESET WP
(NOTE 1)
RESET WP
(NOTE 1)
ERASE BLOCK
(NOTE 2)
WRITE MORE
DATA TO BLOCK
(NOTE 4)
SET WP
(NOTE 3)
WRITE NEW DATA
TO BLOCK
(NOTE 4)
SET WP
(NOTE 3)
OPERATION
COMPLETE
FLOW TO ADD DATA
RELOCK BLOCK
(NOTE 5)
OPERATION
COMPLETE
FLOW TO REWRITE DATA
NOTES:
1. Use Reset-Write-Protect flowchart. Enable Write/Erase operation to all blocks.
2. Use Block-Erase flowchart. Erasing a block clears any previously established lockout for that block.
3. Use Set-Write-Protect flowchart. This step re-implements protection to locked blocks.
4. Use Byte-Write or 2-Byte-Write flowchart sequences to write data.
5. Use Block-Lock flowchart to write lock bit if desired.
28F020SUN80-8
Figure 9. Updating Data in a Locked Block
13
LH28F020SU-N
2M (256K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
Write
1
COMMENTS
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
2-Byte
Write
D = FBH
A=X
Write
D = WD
A0 = 0 loads low byte
of Data Register.
A0 = 1 loads high byte
of Data Register.
Other Addresses = X
Write
D = WD
A = WA
Internally, A0 is automatically
complemented to load the
alternate byte location of the
Data Register.
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
WRITE FBH
WRITE DATA/A0
WRITE
DATA/ADDRESS
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
CSR Full Status Check can be done after each 2-Byte Write,
or after a sequence of 2-Byte Writes.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Cycle notes for description of codes.
0
ANOTHER
2-BYTE
WRITE
YES
NO
OPERATION COMPLETE
28F020SUN80-9
Figure 10. Two-Byte Serial Writes with Compatible Status Registers
14
2M (256K × 8) Flash Memory
LH28F020SU-N
START
BUS
OPERATION
COMMAND
Write
Erase All
Unlocked
Blocks
D = A7H
A=X
Write
Confirm
D = D0H
A=X
WRITE A7H
WRITE D0H
Read
Q = CSRD
Toggle CE or OE
to update CSRD
A=X
Standby
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
SUSPEND
NO ERASE LOOP
0
CSR.7 =
SUSPEND
ERASE
COMMENTS
YES
CSR Full Status Check can be done after Erase All Unlocked
Block, or after a sequence of Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
1
CSR FULL STATUS
CHECK IF DESIRED
OPERATION
COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD
(see above)
CSR.4, 5 =
BUS
OPERATION
0
CSR.3 =
1
VPP LOW
DETECT
COMMENTS
Standby
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Standby
Check CSR.3
1 = VPP Low Detect
0 = VPP OK
ERASE
SUCCESSFUL
1
COMMAND
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
0
CLEAR CSRD
RETRY/ERROR
RECOVERY
28F020SUN80-10
Figure 11. Erase All Unlocked Blocks with Compatible Status Register
15
LH28F020SU-N
2M (256K × 8) Flash Memory
BUS
COMMAND
OPERATION
START
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
COMMENTS
Write
Set
Write Protect
D = 57H
A=X
Write
Set Confirm
D = D0H
A = 0FFH
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Read
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE 57H
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Upon device power-up or reset is completed, Set Write
Protect command must be written to reflect the actual
lock-bit status.
Write FFH after the last operation to reset device to
Read Array Mode.
See Command Bus Cycle notes for description of codes.
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
0
OPERATION
COMPLETE
28F020SUN80-11
Figure 12. Set Write Protect
16
2M (256K × 8) Flash Memory
LH28F020SU-N
BUS
COMMAND
OPERATION
START
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
COMMENTS
Write
Reset
Write Protect
Write
Reset
Confirm
D = 47H
A=X
D = D0H
A = 0FFH
(A9 - A8 = 0, A7 - A0 = 1,
Others = X)
1
Read
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Read
Check CSR.4, 5
1 = Unsuccesful
0 = Successful
WRITE 47H
WRITE CONFIRM
DATA/ADDRESS
NOTE:
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Reset Write Protect command enables Write/Erase
operation to all blocks.
Write FFH after the last operation to reset device to
Read Array Mode.
See Command Bus Cycle notes for description of codes.
READ COMPATIBLE
STATUS REGISTER
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
0
OPERATION
COMPLETE
28F020SUN80-12
Figure 13. Reset Write Protect
17
LH28F020SU-N
2M (256K × 8) Flash Memory
*WARNING: Stressing the device beyond
ELECTRICAL SPECIFICATIONS
the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
Absolute Maximum Ratings*
Temperature Under Bias ....................... 0°C to + 80°C
Storage Temperature ........................ -65°C to + 125°C
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
TA
Operating Temperature, Commercial
0
70.0
°C
Ambient Temperature
1
VCC
VCC with Respect to GND
-0.2
7.0
V
2
VPP
VPP Supply Voltage with
Respect to GND
-0.2
7.0
V
2
V
Voltage on any Pin (Except VCC,
VPP) with Respect to GND
-0.5
7.0
V
2
I
Current into any Non-Supply Pin
±30
mA
100.0
mA
IOUT
Output Short Circuit Current
3
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods
< 20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V
for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
Capacitance
SYMBOL
TYP.
MAX.
UNITS
Capacitance Looking into an
Address/Control Pin
7
10
pF
TA = 25°C, f = 1.0 MHz
1
COUT
Capacitance Looking into an Output Pin
9
12
pF
TA = 25°C, f = 1.0 MHz
1
CLOAD
Load Capacitance Driven by Outputs for
Timing Specifications
100
pF
For VCC = 5.0 V ±0.5 V
1
Equivalent Testing Load Circuit VCC ± 10%
2.5
ns
25 Ω transmission line delay
CIN
PARAMETER
NOTE:
1. Sampled, not 100% tested.
18
TEST CONDITIONS
NOTE
2M (256K × 8) Flash Memory
LH28F020SU-N
Timing Nomenclature
For 3.3 V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tELQV
time (t) from CE » (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV
time (t) from OE » (G) going low (L) to the outputs (Q) becoming valid (V)
tACC tAVQV
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS
tAVWH time (t) from address (A) valid (V) to WE » (W) going high (H)
tDH
tWHDX time (t) from WE » (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
PIN STATES
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE » (Chip Enable)
X
Driven, but not necessarily valid
G
OE » (Output Enable)
Z
High Impedance
W
WE (Write Enable)
V
Any Voltage Level
3V
VCC at 3.0 V MIN.
2.4
INPUT
0.45
2.0
0.8
TEST POINTS
2.0
0.8
2.5 ns OF 25 Ω TRANSMISSION LINE
OUTPUT
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise
and fall times (10% to 90%) < 10 ns.
FROM OUTPUT
UNDER TEST
TEST
POINT
TOTAL CAPACITANCE = 100 pF
28F020SUN80-14
28F020SUN80-13
Figure 14. Transient Input/Output
Reference Waveform (VCC = 5.0 V)
Figure 15. Transient Equivalent Testing
Load Circuit (VCC = 5.0 V)
19
LH28F020SU-N
2M (256K × 8) Flash Memory
DC Characteristics
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
IIL
Input Load Current
ILO
Output Leakage
Current
TYP.
5
ICCS
20
MAX.
UNITS
TEST CONDITIONS
NOTE
±1
µA
VCC = VCC MAX., VIN = VCC or GND
1
±10
µA
VCC = VCC MAX., VIN = VCC or GND
1
10
µA
VCC = VCC MAX.,
CE » = VCC ±0.2V
mA
VCC = VCC MAX.,
CE » = VIH
mA
VCC = VCC MAX.,
CMOS: CE » = GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
1, 3, 4
TTL: CE » = VIL
Inputs = VIL or VIH
f = 10 MHz, IOUT = 0 mA
VCC Standby Current
1
ICCR1
MIN.
VCC Read Current
4
60
1,4
ICCR2
VCC Read Current
13
30
mA
VCC = VCC MAX.,
CMOS: CE » = GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
1, 3, 4
TTL: CE » = VIL
Inputs = VIL or VIH
f = 5 MHz, IOUT = 0 mA
ICCW
VCC Write Current
18
35
mA
Byte/Two-Byte Serial Write in
Progress
1
ICCE
VCC Block Erase
Current
18
25
mA
Block Erase in Progress
1
ICCES
VCC Erase Suspend
Current
5
10
mA
CE » = VIH
Block Erase Suspended
1, 2
IPPS
VPP Standby Current
±10
µA
VPP ≤ VCC
1
2M (256K × 8) Flash Memory
LH28F020SU-N
DC Characteristics (Continued)
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IPPR
VPP Read Current
65
200
µA
VPP > VCC
1
IPPW
VPP Write Current
15
35
mA
VPP = VPPH, Byte/Two-Byte
Serial Write in Progress
1
IPPE
VPP Erase Current
20
40
mA
VPP = VPPH,
Block Erase in Progress
1
IPPES
VPP Erase Suspend
Current
65
200
µA
VPP = VPPH,
Block Erase Suspended
1
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
0.45
V
VCC = VCC MIN. and
IOL = 5.8 mA
0.85
VCC
V
IOH = -2.5 mA
VCC = VCC MIN.
VCC
- 0.4
V
IOH = -100 µA
VCC = VCC MIN.
VOH1
Output High Voltage
VOH
2
VPPL
VPP during Normal
Operations
VPPH
VPP during Write/Erase
Operations
VLKO
VCC Erase/Write
Lock Voltage
5.0
0.0
5.5
V
4.5
5.5
V
1.4
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 5.0 V, T = 25°C.
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current
draw is the sum of ICCES and ICCR.
3. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation.
4. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.
21
LH28F020SU-N
2M (256K × 8) Flash Memory
AC Characteristics - Read Only Operations1
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
tAVAV
Read Cycle Time
80
ns
tAVGL
Address Setup to OE » Going Low
0
ns
tAVQV
Address to Output Delay
80
ns
tELQV
CE » to Output Delay
80
ns
2
tGLQV
OE » to Output Delay
35
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
tOH
Output Hold from Address, CE » or
OE » change, whichever occurs first
0
30
0
30
0
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figure 4.
2. OE » may be delayed up to t ELQV - tGLQV after the falling edge of CE » without impact on tELQV.
3. Sampled, not 100% tested.
22
NOTE
3
2M (256K × 8) Flash Memory
VCC
POWER-UP
ADDRESSES (A)
LH28F020SU-N
STANDBY
DEVICE AND
ADDRESS
SELECTION
VIH
OUTPUTS ENABLED
DATA VALID
...
ADDRESSES STABLE
VIL
VCC
STANDBY POWER-DOWN
...
tAVAV
CE (E)
VIH
...
VIL
tEHQZ
OE (G)
VIH
...
VIL
tAVGL
WE (W)
tGHQZ
...
VIH
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
DATA (D/Q)
VOH
...
HIGH-Z
VALID OUTPUT
HIGH-Z
...
VOL
tAVQV
5.0 V
VCC
GND
28F020SUN80-15
Figure 16. Read Timing Waveforms
23
LH28F020SU-N
2M (256K × 8) Flash Memory
POWER-UP AND RESET TIMINGS
SYMBOL
PARAMETER
MIN.
MAX.
5
UNITS
NOTE
µs
1
tWLPL
WE Low to VCC at 4.5 V MIN.
tAVQV
Address Valid to Data Valid for VCC 5.0 V ± 10%
80
ns
2
tPHQV
WE High to Data Valid for VCC 5.0 V ± 10%
500
ns
2
tELRS
CE » Setup to WE Going Low
100
ns
tGLRS
OE » Setup to WE Going Low
100
ns
tEHRS
CE » Hold from WE Going High
100
ns
tGHRS
OE » Hold from WE Going High
100
ns
NOTES:
CE » and OE » are switched low after Power-Up.
1. Chip reset is enabled when the low state of all CE », OE », and WE » exceeds 5 µs. This state should be used only for chip reset.
2. These values are shown for 3.5 V VCC operation. Refer to the AC Characteristics Read Only Operations also.
VCC POWER UP
tEHRS
tELRS
CE (E)
OE (G)
tGLRS
tGHRS
WE (W)
5.0 V
5.0 V
4.5 V
VCC (5 V)
0V
tWLPL
ADDRESS (A)
VALID
tAVQV
VALID
5.0 V OUTPUTS
DATA (Q)
tPHQV
28F020SUN80-16
Figure 17. VCC Power-Up and Reset Waveforms
24
2M (256K × 8) Flash Memory
LH28F020SU-N
AC Characteristics for WE » - Controlled Command Write Operations1
VCC = 5.0 ± 0.5 V, TA = 0° to 70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
tAVAV
Write Cycle Time
80
ns
tVPWH
VPP Setup to WE Going High
100
ns
tELWL
CE » Setup to WE Going Low
0
ns
tAVWH
Address Setup to WE Going High
55
ns
2, 6
tDVWH
Data Setup to WE Going High
55
ns
2, 6
tWLWH
WE Pulse Width
55
ns
tWHDX
Data Hold from WE High
0
ns
2
tWHAX
Address Hold from WE High
10
ns
2
tWHEH
CE » Hold from WE High
10
ns
tWHWL
WE Pulse Width High
30
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
65
ns
tQVVL
VPP Hold from Valid Status Register Data
0
µs
4.5
µs
4, 5
0.3
s
4
tWHQV1
Duration of Byte Write Operation
tWHQV2
Duration of Block Erase Operations
13
3
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE » for all Command Write operations.
25
LH28F020SU-N
2M (256K × 8) Flash Memory
WRITE VALID
ADDRESS AND DATA
WRITE DATA-WRITE (DATA-WRITE) OR
OR ERASE
ERASE CONFIRM
SETUP COMMAND
COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
AIN
(NOTE 2)
tAVWH tWHAX
tAVAV
CE (E)
READ
COMPATIBLE
STATUS
REGISTER DATA
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
VIH
VIL
tWHEH
tWHGL
tELWL
OE (G)
VIH
VIL
tWHWL
WE (W)
tWHQV 1, 2
tGHWL
VIH
VIL
tWLWH
tWHDX
tDVWH
DATA (D/Q)
VIH
VIL
HIGH-Z
DIN
DIN
DIN
tVPWH
VPP (V)
DOUT
tQVVL
VPPH
VPPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
2. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
Figure 18. AC Waveforms for Command Write Operations
26
DIN
28F020SUN80-17
2M (256K × 8) Flash Memory
LH28F020SU-N
AC Characteristics for CE » - Controlled Command Write Operations1
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
NOTE
tAVAV
Write Cycle Time
80
ns
tVPEH
VPP Setup to CE » Going High
100
ns
tWLEL
WE Setup to CE » Going Low
0
ns
tAVEH
Address Setup to CE » Going High
55
ns
2, 6
tDVEH
Data Setup to CE » Going High
55
ns
2, 6
tELEH
CE » Pulse Width
55
ns
tEHDX
Data Hold from CE » High
0
ns
2
tEHAX
Address Hold from CE » High
10
ns
2
tEHWH
WE Hold from CE » High
10
ns
tEHEL
CE » Pulse Width High
30
ns
tGHEL
Read Recovery before Write
0
ns
tEHGL
Write Recovery before Read
65
ns
tQVVL
VPP Hold from Valid Status Register Data
0
µs
tEHQV1
Duration of Byte Write Operation
4.5
µs
4, 5
tEHQV2
Duration of Block Erase Operations
0.3
s
4
13
3
NOTES:
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE » for all Command Write Operations.
27
LH28F020SU-N
2M (256K × 8) Flash Memory
WRITE VALID
ADDRESS AND DATA
WRITE DATA-WRITE (DATA-WRITE) OR
OR ERASE
ERASE CONFIRM
SETUP COMMAND
COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
WE (W)
(NOTE 2)
AIN
tAVAV
tAVEH
READ
COMPATIBLE
STATUS
REGISTER DATA
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
tEHAX
VIH
VIL
tEHWH
tEHGL
tWLEL
OE (G)
VIH
VIL
tEHEL
CE (E)
tEHQV 1, 2
tGHEL
VIH
VIL
tELEH
tEHDX
tDVEH
DATA (D/Q)
VIH
VIL
HIGH-Z
DIN
DIN
DIN
tVPEH
DOUT
DIN
tQVVL
VPPH
VPP (V) V
PPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
2. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
Figure 19. Alternate AC Waveforms for Command Write Operations
28
28F020SUN80-18
2M (256K × 8) Flash Memory
LH28F020SU-N
Erase and Byte Write Performance
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
TYP.1
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
tWHRH1
Byte Write Time
13
µs
2
tWHRH2
Two-Byte Serial Write Time
20
µs
2
tWHRH3
16KB Block Write Time
0.22
1.0
s
Byte Write Mode
2
tWHRH4
16KB Block Write Time
0.17
1.0
s
Two-Byte Serial Write Mode
2
Block Erase Time (16K)
0.6
10.0
s
2
s
2, 3
Full Chip Erase Time
4.4 - 7.2
NOTES:
1. 25°C, VPP = 5.0 V
2. Excludes System-Level Overhead.
3. Depends on the number of protected blocks.
32SOP (SOP032-P-0525)
0.15 [0.006] M
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
1.40 [0.055]
32
17
11.50 [0.453] 14.50 [0.571]
11.10 [0.437] 13.70 [0.539]
1
16
12.50 [0.492]
SEE DETAIL
1.40 [0.055]
0.20 [0.008]
0.10 [0.004]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
2.90 [0.114]
2.50 [0.098]
0.10 [0.004]
DIMENSIONS IN MM [INCHES]
DETAIL
1.27 [0.050]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
2.00 [0.079]
0.00 [0.000]
0 - 10°
0.80 [0.031]
MAXIMUM LIMIT
MINIMUM LIMIT
FL32SOP
Figure 20. 32-Pin SOP
29
LH28F020SU-N
2M (256K × 8) Flash Memory
32TSOP (TSOP032-P-0820)
0.10 [0.004] M
0.30 [0.012]
0.10 [0.004]
0.50 [0.020]
TYP.
32
17
18.60 [0.732]
18.20 [0.717]
1
20.30 [0.799]
19.70 [0.776]
19.00 [0.748]
16
8.20 [0.323]
7.80 [0.307]
0.20 [0.008]
0.10 [0.004]
0.15 [0.006]
1.10 [0.043]
0.90 [0.035]
0.425 [0.017]
DETAIL
1.20 [0.047] MAX.
0.10 [0.004]
DIMENSIONS IN MM [INCHES]
0.425 [0.017] 0.20 [0.008]
0.00 [0.000]
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.00 [0.000]
MAXIMUM LIMIT
MINIMUM LIMIT
0 - 10°
FL32TSOP
Figure 21. 32-Pin TSOP
ORDERING INFORMATION
LH28F020SU
Device Type
X
-N80
Package Speed
80 (VCC = 5.0 V) Access Time (ns)
N 32-pin, 525-mil SOP (SOP32-P-0525)
T 32-pin, 2.7 mm x 8 mm x 20 mm TSOP (Type I) (TSOP032-P-0820)
2M (256K x 8) Flash Memory
Example: LH28F0020SUT-N80 (2M (256K x 8) Flash Memory, 80 ns, 32-pin TSOP)
28F020SUN80-19
30
2M (256K × 8) Flash Memory
LH28F020SU-N
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Issued September 1995
Reference Code SMT96104