SHARP LH28F800SUT-70

LH28F800SU
FEATURES
• User-Configurable x8 or x16 Operation
• User-Selectable 3.3 V or 5 V VCC
• 5 V Write/Erase Operations (5 V VPP)
– No Requirement for DC/DC
Converter to Write/Erase
• 70 ns Maximum Access Time
• Minimum 2.7 V Read capability
– 160 ns Maximum Access Time
(VCC = 2.7 V)
•
•
•
•
16 Independently Lockable Blocks
0.32 MB/sec Write Transfer Rate
100,000 Erase Cycles per Block
Revolutionary Architecture
– Pipelined Command Execution
– Write During Erase
– Command Superset of
Sharp LH28F008SA
• 5 µA (TYP.) ICC in CMOS Standby
• 1 µA (TYP.) Deep Power-Down
• State-of-the-Art 0.55 µm ETOX™
Flash Technology
• 56-Pin, 1.2 mm × 14 mm × 20 mm
TSOP (Type I) Package
8M (512K × 16, 1M × 8) Flash Memory
56-PIN TSOP
TOP VIEW
WP
56
1
3/5
WE
55
2
CE1
OE
54
3
NC
RY/BY
53
4
NC
DQ15
52
5
A19
DQ7
51
6
A18
DQ14
50
7
A17
DQ6
49
8
A16
GND
48
9
VCC
DQ13
47
10
A15
DQ5
46
11
A14
DQ12
45
12
A13
DQ4
44
13
A12
VCC
43
14
CE0
GND
42
15
VPP
DQ11
41
16
RP
DQ3
40
17
A11
DQ10
39
18
A10
DQ2
38
19
A9
VCC
37
20
A8
DQ9
36
21
GND
DQ1
35
22
A7
DQ8
34
23
A6
DQ0
33
24
A5
A4
A0
32
25
BYTE
31
26
A3
NC
30
27
A2
NC
29
28
A1
28F800SUR-1
Figure 1. TSOP Reverse Bend Configuration
1
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
56-PIN TSOP
TOP VIEW
3/5
1
56
CE1
2
55
WE
NC
3
54
OE
NC
4
53
RY/BY
A19
5
52
DQ15
A18
6
51
DQ7
A17
7
50
DQ14
A16
8
49
DQ6
VCC
9
48
GND
A15
10
47
DQ13
A14
11
46
DQ5
A13
12
45
DQ12
A12
13
44
DQ4
CE0
14
43
VCC
VPP
15
42
GND
WP
RP
16
41
DQ11
A11
17
40
DQ3
A10
18
39
DQ10
A9
19
38
DQ2
A8
20
37
VCC
GND
21
36
DQ9
A7
22
35
DQ1
A6
23
34
DQ8
A5
24
33
DQ0
A4
25
32
A0
A3
26
31
BYTE
A2
27
30
NC
A1
28
29
NC
28F800SUR-17
Figure 2. TSOP Configuration
INTRODUCTION
Sharp’s LH28F800SU 8M Flash Memory is a revolutionary architecture which enables the design of truly
mobile, high performance, personal computing and communication products. With innovative capabilities, 5 V
single voltage operation and very high read/write performance, the LH28F800SU is also the ideal choice for
designing embedded mass storage flash memory systems.
The LH28F800SU is a very high density, highest performance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked architecture (100% compatible with the LH28F008SA 8M
Flash memory, the LH28F016SA 16M Flash memory
and the LH28F016SU 16M 5 V single voltage Flash
memory), extended cycling, low power 3.3 V operation,
very fast write and read performance and selective block
locking provide a highly flexible memory component suitable for high density memory cards, Resident Flash
Arrays and PCMCIA-ATA Flash Drives. The
LH28F800SU’s dual read voltage enables the design of
memory cards which can interchangeably be read/written in 3.3 V and 5.0 V systems. Its x8/x16 architecture
allows the optimization of memory to processor interface. The flexible block locking option enables bundling
of executable application software in a Resident Flash
Array or memory card. Manufactured on Sharp’s 0.55
µm ETOX™ process technology, the LH28F800SU is
the most cost-effective, high-density 3.3 V flash memory.
DESCRIPTION
The LH28F800SU is a high performance 8M
(8,388,608 bit) block erasable non-volatile random
access memory organized as either 512K × 16 or
1M × 8. The LH28F800SU includes sixteen 64K (65,536)
blocks or sixteen 32-KW (32,768) blocks. A chip memory
map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F800SU:
•
•
•
•
5 V Write/Erase Operation (5 V VPP)
3.3 V Low Power Capability (2.7 V VCC Read)
Improved Write Performance
Dedicated Block Write/Erase Protection
A 3/5 » input pin reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.
2
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
DQ8 - DQ15
DQ0 - DQ7
OUTPUT
BUFFER
OUTPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
DATA
QUEUE
REGISTERS
ID
REGISTER
I/O
LOGIC
CSR
OUTPUT
MULTIPLEXER
3/5
BYTE
PAGE
BUFFERS
CE0
CE1
ESRs
OE
WE
WP
RP
CUI
DATA
COMPARATOR
ADDRESS
COUNTER
...
64KB BLOCK 15
...
64KB BLOCK 14
X-DECODER
64KB BLOCK 1
ADDRESS
QUEUE
LATCHES
Y GATING/SENSING
Y-DECODER
64KB BLOCK 0
INPUT
BUFFER
...
A0 - A19
WSM
PROGRAM/
ERASE
VOLTAGE
SWITCH
RY/BY
VPP
3/5
VCC
GND
28F800SUR-2
Figure 3. LH28F800SU Block Diagram (Architectural Evolution Includes Page Buffers,
Queue Registers and Extended Status Registers)
3
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8
mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the
A0 input buffer is turned off when BYTE is high).
A1 - A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64K block. A6 - A15 selects
1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are
latched during Data Writes.
A16 - A19
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 16 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.
DQ0 - DQ7
DQ8 - DQ15 INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
CE »0, CE »1
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers, decoders and
sense amplifiers. With either CE »0 or CE »1 high, the device is de-selected and power
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE » 0, CE »1 must be low to select the device. All timing
specifications are the same for both signals. Device Selection occurs with the latter
falling edge of CE »0 or CE »1. The first rising edge of CE »0 or CE »1 disables the device.
RP »
INPUT
RESET/POWER-DOWN: With RP » low, the device is reset, any current operation is
aborted and device is put into the deep power down mode. When the power is turned
on, RP » pin is turned to low in order to return the device to default configuration. When
the 3/5 » pin is switched, or when the power transition is occurred, or at the power on/off,
RP » is required to stay low in order to protect data from noise. When returning from
Deep Power-Down, a recovery time of 400 ns (VCC +5.0 V ±0.25 V) is required to allow
these circuits to power-up. When RP » goes low, any current or pending WSM
operation(s) are terminated, and the device is reset. All Status registers return to ready
(with all status flags cleared). After returning, the device is in read array mode.
OE »
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE » is high.
NOTE: CE »X overrides OE », and OE » overrides WE.
WE
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
OPEN DRAIN
OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. RY »/BY » high indicates that the WSM is ready
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE » or CE »0, CE »1 are high), except if a RY »/BY »
Pin Disable command is issued.
RY »/BY »
4
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
PIN DESCRIPTION (Continued)
SYMBOL
TYPE
NAME AND FUNCTION
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP is low, those locked blocks as reflected by the Block-Lock Status
bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high,
all blocks can be Written or Erased regardless of the state of the lock-bits. The WP
input buffer is disabled when RP » transitions low (deep power-down mode).
INPUT
BYTE ENABLE: BYTE low places device x8 mode. All data is then input or output
on DQ0 - DQ7, and DQ8 - DQ15 float. Address A0 selects between the high and low
byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer.
Address A1, then becomes the lowest order address.
3/5 »
INPUT
3.3/5.0 VOLT SELECT: 3/5 » high configures internal circuits for 3.3 V operation.
3/5 » low configures internal circuits for 5.0 V operation.
NOTES: Reading the array with 3/5 » high in a 5.0 V system could damage the
device. There is a significant delay from 3/5 » switching to valid data.
VPP
SUPPLY
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V): For erasing memory array blocks or
writing words/bytes/pages into the flash array.
VCC
SUPPLY
DEVICE POWER SUPPLY (3.3 V ±0.3 V, 5.0 V ±0.5 V) (2.7 ~ 3.6 at Read Operation):
Do not leave any power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
WP
BYTE
NC
NO CONNECT: No internal connection to die, lead may be driven or left floating.
5
LH28F800SU
The LH28F800SU will be available in a 56-pin,
1.2 mm thick × 14 mm × 20 mm TSOP (Type I) package. This form factor and pinout allow for very high board
layout densities.
A Command User Interface (CUI) serves as the system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Page Buffer Writes to Flash
• Command Queuing Capability
• Automatic Data Writes During Erase
• Software Locking of Memory Blocks
• Two-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments typically within 8 µs, a 25% improvement over the LH28F008SA. A Block Erase operation
erases one of the 16 blocks in typically 0.7 seconds,
independent of the other blocks, which is about 55%
improvement over the LH28F008SA.
The LH28F800SU incorporates two Page Buffers of
256 Bytes (128 Words) each to allow page data writes.
This feature can improve a system write performance
over previous flash memory devices.
All operations are started by a sequence of Write
commands to the device. Three Status Registers (described in detail later) and a RY »/BY » output pin provide
information on the progress of the requested operation.
While the LH28F008SA requires an operation to complete before the next operation can be requested, the
LH28F800SU allows queuing of the next operation while
the memory executes the current operation. This eliminates system overhead when writing several bytes in a
row to the array or erasing several blocks at the same
time. The LH28F800SU can also perform write operations to one block of memory while performing erase of
another block.
The LH28F800SU provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the
block. In addition, the LH28F800SU has a master Write
Protect pin (WP ») which prevents any modification to
memory blocks whose lock-bits are set.
6
8M (512K × 16, 1M × 8) Flash Memory
The LH28F800SU contains three types of Status
Registers to accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capability to the LH28F800SU from a LH28F008SA
based design.
• A Global Status Register (GSR) which informs the
system of command Queue status. Page Buffer status, and overall Write State Machine (WSM) status.
• 16 Block Status Register (BSRs) which provide
block-specific status information such as the block
lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 5 and 6.
The LH28F800SU incorporates an open drain
RY /» BY » output pin. This feature allows the user to ORtie many RY /» BY » pins together in a multiple memory configuration such as a Resident Flash Array.
The LH28F800SU also incorporates a dual chip-enable function with two input pins. CE 0» and CE 1» . These
pins have exactly the same functionality as the regular
chip-enable pin CE » on the LH28F008SA. For minimum
chip designs, CE 1» may be tied to ground and use CE »0
as the chip enable input. The LH28F800SU uses the
logical combination of these two signals to enable or
disable the entire chip. Both CE »0 and CE 1» must be active low to enable the device and if either one
becomes inactive, the chip will be disabled. This feature, along with the open drain RY /» BY » pin, allows the
system designer to reduce the number of control pins
used in a large array of 8M devices.
The BY T
» E » pin allows either x8 or x16 read/writes to
the LH28F800SU. BY T
» E » at logic low selects 8-bit mode
with address A0 selecting between low byte and high
byte. On the other hand, BY »TE » at logic high enables
16-bit operation with address A1 becoming the lowest
order address and address A0 is not used (don’t care).
A block diagram is shown in Figure 3.
The LH28F800SU is specified for a maximum
access time of each version, as follows:
OPERATING
TEMPERATURE
VCC SUPPLY
MAX. ACCESS
(TACC)
0 - 70°C
4.75 - 5.25 V
70 ns
0 - 70°C
4.5 - 5.5 V
80 ns
0 - 70°C
3.0 - 3.6 V
120 ns
0 - 70°C
2.7 - 3.6 V
160 ns
8M (512K × 16, 1M × 8) Flash Memory
The LH28F800SU incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 2 mA at 5.0 V
(1 mA at 3.3 V).
A Deep Power-Down mode of operation is invoked
when the RP » (called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power-down mode. This mode
brings the device power consumption to less than 5 µA,
typically, and provides additional write protection by
acting as a device reset pin during power transitions.
When the power is turned on, RP » pin turned to low order to return the device to default configuration. When
the 3/5 » pin is switched, or when the power transition is
occurred, or at the power on/off, RP » is required to stay
low in order to protect data from noise. A recovery time
of 400 ns (VCC = 5.0 V ± 0.5 V) is required from RP »
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR registers are cleared.
A CMOS Standby mode of operation is enabled when
either CE »0 or CE »1 transitions high and RP » stays
high with all input control pins at CMOS levels. In this
mode, the device typically draws an ICC standby current of 10 µA.
LH28F800SU
MEMORY MAP
FFFFFH
F0000H
EFFFFH
E0000H
DFFFFH
D0000H
CFFFFH
C0000H
BFFFFH
B0000H
AFFFFH
A0000H
9FFFFH
90000H
8FFFFH
80000H
7FFFFH
70000H
6FFFFH
60000H
5FFFFH
50000H
4FFFFH
40000H
3FFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
00000H
64KB BLOCK
15
64KB BLOCK
14
64KB BLOCK
13
64KB BLOCK
12
64KB BLOCK
11
64KB BLOCK
10
64KB BLOCK
9
64KB BLOCK
8
64KB BLOCK
7
64KB BLOCK
6
64KB BLOCK
5
64KB BLOCK
4
64KB BLOCK
3
64KB BLOCK
2
64KB BLOCK
1
64KB BLOCK
0
28F800SUR-3
Figure 4. LH28F800SU Memory Map
(Byte-Wide Mode)
7
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
x8 MODE
x16 MODE
A[19:0]
RESERVED
GSR
RESERVED
BSR15
RESERVED
RESERVED
.
.
.
A[19:1] (NOTE)
F0006H
RESERVED
F0005H
GSR
F0004H
RESERVED
F0003H
BSR15
F0002H
RESERVED
F0001H
RESERVED
F0000H
.
.
.
10002H
RESERVED
BSR0
RESERVED
RESERVED
78001H
78000H
RESERVED
00006H
GSR
78002H
08001H
RESERVED
RESERVED
78003H
RESERVED
00005H
GSR
00004H
RESERVED
00003H
BSR0
00002H
RESERVED
00001H
RESERVED
00000H
00003H
00002H
00001H
00000H
28F800SUR-4
Figure 5. Extended Status Register
Memory Map (Byte-Wide Mode)
8
NOTE: In word-wide mode A0 don't care, address values
are ignored A0.
28F800SUR-5
Figure 6. Extended Status Register
Memory Map (Word-Wide Mode)
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
Bus Operations for Word-Wide Mode (BYT
» E » = VIH)
RP »
CE »1
CE »0
OE »
WE
A1
DQ0 - DQ15
RY »/BY »
NOTE
Read
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
1, 2, 7
Output Disable
VIH
VIL
VIL
VIH
VIH
X
High-Z
X
1, 6, 7
Standby
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High-Z
X
1, 6, 7
Deep Power-Down
VIL
X
X
X
X
X
High-Z
VOH
1, 3
Manufacturer ID
VIH
VIL
VIL
VIL
VIH
VIL
00B0H
VOH
4
Device ID
VIH
VIL
VIL
VIL
VIH
VIH
66A8H
VOH
4
Write
VIH
VIL
VIL
VIH
VIL
X
DIN
X
1, 5, 6
MODE
Bus Operations For Byte-Wide Mode (BYT
» E » = VIL)
RP »
CE »1
CE »0
OE »
WE
A0
DQ0 - DQ7
RY »/BY »
NOTE
Read
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
1, 2, 7
Output Disable
VIH
VIL
VIL
VIH
VIH
X
High-Z
X
1, 6, 7
Standby
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
High-Z
X
1, 6, 7
Deep Power-Down
VIL
X
X
X
X
X
High-Z
VOH
1, 3
Manufacturer ID
VIH
VIL
VIL
VIL
VIH
VIL
B0H
VOH
4
Device ID
VIH
VIL
VIL
VIL
VIH
VIH
A8H
VOH
4
Write
VIH
VIL
VIL
VIH
VIL
X
DIN
X
1, 5, 6
MODE
NOTES:
1. X can be VIH or VIL for address or control pins except for RY »/BY », which is either VOL or VOH .
2. RY »/BY » output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode,
RY »/BY » will be at VOH if it is tied to VCC through a resistor. When the RY /» BY » at VOH is independent of OE » while a WSM
operation is in progress.
3. RP » at GND ± 0.2 V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. A 0 and A1, at VIH provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully
completed when VPP = VPPH.
6. While the WSM is running, RY »/BY » in Level-Mode (default) stays at VOL until all operations are complete. RY »/BY » goes to
VOH when the WSM is not busy or in erase suspend mode.
7. RY »/BY » may be at VOL while the WSM is busy performing various operations. For example, a status register read during a
write operations.
9
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
LH28F008SA-Compatible Mode Command Bus Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
NOTE
OPER.
ADDRESS
DATA
OPER.
ADDRESS
DATA
Read Array
Write
X
FFH
Read
AA
AD
Intelligent Identifier
Write
X
90H
Read
IA
ID
1
Read Compatible Status Register
Write
X
70H
Read
X
CSRD
2
Clear Status Register
Write
X
50H
Word/Byte Write
Write
X
40H
Write
WA
WD
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
Erase Suspend/Resume
Write
X
B0H
Write
X
D0H
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
3
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.
10
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
LH28F800SU Performance Enhancement Command Bus Definitions
FIRST BUS CYCLE
COMMAND
SECOND BUS CYCLE
THIRD BUS CYCLE
MODE
NOTE
OPER. ADDR.
DATA
OPER. ADDR.
DATA
Read
GSRD
BSRD
OPER.
ADDR.
DATA
Read Extended
Status Register
Write
X
71H
Page Buffer Swap
Write
X
72H
Read Page Buffer
Write
X
75H
Read
PA
PD
Single Load to
Page Buffer
Write
X
74H
Write
PA
PD
x8
Write
X
E0H
Write
X
BCL
Write
X
BCH
4, 6, 10
x16
Write
X
E0H
Write
X
WCL
Write
X
WCH
4, 5,
6, 10
x8
Write
X
0CH
Write
A0
BC
(L, H)
Write
WA
BC (H, L)
3, 4,
9, 10
x16
Write
X
0CH
Write
X
WCL
Write
WA
WCH
4, 5, 10
x8
Write
X
FBH
Write
A0
WD
(L, H)
Write
WA
WD (H, L)
3
Block
Erase/Confirm
Write
X
20H
Write
BA
D0H
Lock Block/Confirm
Write
X
77H
Write
BA
D0H
Upload Status
Bits/Confirm
Write
X
97H
Write
X
D0H
Upload Device
Information
Write
X
99H
Write
X
D0H
Erase All Unlocked
Blocks/Confirm
Write
X
A7H
Write
X
D0H
RY »/BY » Enable to
Level-Mode
Write
X
96H
Write
X
01H
8
RY »/BY » Pulse-OnWrite
Write
X
96H
Write
X
02H
8
RY »/BY » Pulse-OnErase
Write
X
96H
Write
X
03H
8
RY »/BY » Disable
Write
X
96H
Write
X
04H
8
Sleep
Write
X
F0H
Abort
Write
X
80H
Sequential Load to
Page Buffer
Page Buffer Write
to Flash
Two-Byte Write
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don’t Care
RA
1
7
2
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
WC (L, H) = Word Count (Low, High)
BC (L, H) = Byte Count (Low, High)
WD (L, H) = Write Data (Low, High)
11
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 5 and 6 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lockbit status.
3. A0 is automatically complemented to load second byte of data. BY T
» E » must be at VIL. A0 value determines which WD/BC is supplied
first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.
5. In x16 mode, only the lower byte DQ0 - DQ 7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.
6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY »/BY » output to one of two pulse-modes or enable and disable the RY »/BY » function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the
LH28F800SU User’s Manual.
10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.
Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
CSR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
CSR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
12
NOTES:
1. RY »/BY » output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPL and VPPH.
4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
GLOBAL STATUS REGISTER
WSMS
OSS
DOS
DSS
QS
PBAS
PBS
PBSS
7
6
5
4
3
2
1
0
GSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
GSR.6 = OPERATION SUSPEND STATUS (OSS)
1 = Operation Suspended
0 = Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS (DOS)
1 = Operation Unsuccessful
0 = Operation Successful or Currently Running
GSR.4 = DEVICE SLEEP STATUS(DSS)
1 = Device in Sleep
0 = Device Not in Sleep
MATRIX 5/4
00
01
10
11
= Operation Successful or Currently Running
= Device in Sleep Mode or Pending Sleep
= Operation Unsuccessful
= Operation Unsuccessful or Aborted
NOTES:
1. RY »/BY » output or WSMS bit must be checked to determine
completion of an operation (Block Lock, Suspend, any
RY »/BY » reconfiguration, Upload Status Bits, Erase or Data
Write) before the appropriate Status bit (OSS or DOS) is
checked for success.
2. If operation currently running, then GSR.7 = 0.
3. If device pending sleep, then GSR.7 = 0.
4. Operation aborted: Unsucccessful due to Abort command.
5. The device contains two Page Buffers.
6. Selected Page Buffer is currently busy with WSM operation.
7. When multiple operations are queued, checking BSR.7
only provides indication of completion for that particular
block. GSR.7 provides indication when all queued operations are completed.
GSR.3 = QUEUE STATUS (QS)
1 = Queue Full
0 = Queue Available
GSR.2 = PAGE BUFFER AVAILABLE STATUS (PBAS)
1 = One or Two Page Buffers Available
0 = No Page Buffer Available
GSR.1 = PAGE BUFFER STATUS (PBS)
1 = Selected Page Buffer Ready
0 = Selected Page Buffer Busy
GSR.0 = PAGE BUFFER SELECT STATUS (PBSS)
1 = Page Buffer 1 Selected
0 = Page Buffer 0 Selected
13
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
BLOCK STATUS REGISTER
BS
BLS
BOS
BOAS
QS
VPPS
R
R
7
6
5
4
3
2
1
0
BSR.7 = BLOCK STATUS (BS)
1 = Ready
0 = Busy
NOTES:
1. RY »/BY » output or BS bit must be checked to determine
completion of an operation (Block Lock, Suspend, Erase or
Data Write) before the appropriate Status bits (BOS, BLS)
is checked for success.
BSR.6 = BLOCK-LOCK STATUS (BLS)
1 = Block Unlocked for Write/Erase
0 = Block Locked for Write/Erase
2. The BOAS bit will not be set until BSR.7 = 1.
BSR.5 = BLOCK OPERATION STATUS (BOS)
1 = Operation Unsuccessful
0 = Operation Successful or Currently Running
4. BSR.1-0 = Reserved for future enhancements. These bits
are reserved for future use; mask them out when polling
the BSRs.
BSR.4 = BLOCK OPERATION ABORT STATUS (BOAS)
1 = Operation Aborted
0 = Operation Not Aborted
5. When multiple operations are queued, checking BSR.7
only provides indication of completion for that particular
block. GSR.7 provides indication when all queued operations are completed.
MATRIX 5/4
00
01
10
11
= Operation Successful or Currently Running
= Not a valid Combination
= Operation Unsuccessful
= Operation Aborted
BSR.3 = QUEUE STATUS (QS)
1 = Queue Full
0 = Queue Available
BSR.2 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
14
3. Operation halted via Abort command.
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
ELECTRICAL SPECIFICATIONS1
*WARNING: Stressing the device beyond
the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond
the “Operating Conditions” is not recommended and
extended exposure beyond the “Operating Conditions”
may affect device reliability.
Absolute Maximum Ratings*
Temperature under bias ......................... 0°C to +80°C
Storage temperature ......................... -65°C to +125°C
VCC = 3.3 V ± 0.3 V Systems4
SYMBOL
TA
PARAMETER
Operating Temperature, Commercial
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
0
70
°C
Ambient Temperature
1
VCC
VCC with Respect to GND
-0.2
7.0
V
2
VPP
VPP Supply Voltage with Respect to GND
-0.2
7.0
V
2
V
Voltage on any Pin (Except VCC, VPP)
with Respect to GND
-0.5
VCC + 0.5
V
2
I
Current into any Non-Supply Pin
±30
mA
100.0
mA
IOUT
Output Short Circuit Current
3
VCC = 5.0 V ± 0.5 V Systems4
SYMBOL
TA
PARAMETER
Operating Temperature, Commercial
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
0
70
°C
Ambient Temperature
1
VCC
VCC with Respect to GND
-0.2
7.0
V
2
VPP
VPP Supply Voltage with Respect to GND
-0.2
7.0
V
2
V
Voltage on any Pin (Except VCC, VPP)
with Respect to GND
-0.5
7.0
V
2
I
Current into any Non-Supply Pin
±30
mA
100.0
mA
IOUT
Output Short Circuit Current
3
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns.
Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
15
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
Capacitance
For 3.3 V Systems
SYMBOL
TYP.
MAX.
UNITS
Capacitance Looking into an
Address/Control Pin
6
8
pF
TA = 25°C, f = 1.0 MHz
1
COUT
Capacitance Looking into an Output Pin
8
12
pF
TA = 25°C, f = 1.0 MHz
1
CLOAD
Load Capacitance Driven by Outputs for
Timing Specifications
50
pF
For VCC = 3.3 V ±0.3 V
1
Equivalent Testing Load Circuit
2.5
ns
50 Ω transmission line delay
TYP.
MAX.
UNITS
TEST CONDITIONS
Capacitance Looking into an
Address/Control Pin
6
8
pF
TA = 25°C, f = 1.0 MHz
1
COUT
Capacitance Looking into an Output Pin
8
12
pF
TA = 25°C, f = 1.0 MHz
1
CLOAD
Load Capacitance Driven by Outputs for
Timing Specifications
100
pF
For VCC = 5.0 V ±05 V
1
Equivalent Testing Load Circuit VCC ± 10%
2.5
ns
25 Ω transmission line delay
Equivalent Testing Load Circuit VCC ± 5%
2.5
ns
83 Ω transmission line delay
CIN
PARAMETER
TEST CONDITIONS
NOTE
Capacitance
For 5.0 V Systems
SYMBOL
CIN
PARAMETER
NOTE:
1. Sampled, not 100% tested.
16
NOTE
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
Timing Nomenclature
All 3.3 V systems are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC cross
point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below:
tCE
tELQV
time (t) from CE » (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV
time (t) from OE » (G) going low (L) to the outputs (Q) becoming valid (V)
tACC tAVQV
time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAS
tAVWH time (t) from address (A) valid (V) to WE » (W) going high (H)
tDH
tWHDX time (t) from WE » (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
PIN STATES
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE » (Chip Enable)
X
Driven, but not necessarily valid
G
OE » (Output Enable)
Z
High Impedance
W
WE (Write Enable)
P
RP » (Deep Power-Down Pin)
R
RY »/BY » (Ready/Busy)
V
Any Voltage Level
Y
3/5 » Pin
5V
VCC at 4.5 V Min.
3V
VCC at 3.0 V Min.
17
LH28F800SU
2.4
INPUT
0.45
8M (512K × 16, 1M × 8) Flash Memory
2.0
0.8
TEST POINTS
2.0
0.8
2.5 ns OF 50 Ω TRANSMISSION LINE
OUTPUT
FROM OUTPUT
UNDER TEST
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise
and fall times (10% to 90%) < 10 ns.
TEST
POINT
TOTAL CAPACITANCE = 50 pF
28F800SUR-8
28F800SUR-6
Figure 7. Transient Input/Output
Reference Waveform (VCC = 5.0 V)
Figure 9. Transient Equivalent Testing
Load Circuit (VCC = 3.3 V)
2.5 ns OF 25 Ω TRANSMISSION LINE
3.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
0.0
FROM OUTPUT
UNDER TEST
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
Logic '0'. Input timing begins and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns.
28F800SUR-7
TEST
POINT
TOTAL CAPACITANCE = 100 pF
28F800SUR-9
Figure 8. Transient Input/Output
Reference Waveform (VCC = 3.3 V)
Figure 10. Transient Equivalent Testing
Load Circuit (VCC = 5.0 V)
2.5 ns OF 83W TRANSMISSION LINE
FROM OUTPUT
UNDER TEST
TEST
POINT
TOTAL CAPACITANCE = 30 pF
28F800SUR-18
Figure 11. High Speed Transient Equivalent
Testing Load Circuit (VCC = 5.0 V ± 5%)
18
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
DC Characteristics
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
3/5 » = Pin Set High for 3.3 V Operations
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IIL
Input Load Current
±1
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±10
µA
VCC = VCC MAX., VIN = VCC or GND
1
µA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VCC ±0.2 V
BYTE, WP, 3/5 » = VCC ±0.2 V or GND
±0.2 V
1,4
4
ICCS
ICCD
ICCR1
8
VCC Standby Current
VCC Deep Power-Down
Current
VCC Read Current
1
4
mA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VIH
BYTE, WP, 3/5 » = VIH or VIL
1
5
µA
RP » = GND ±0.2 V
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = GND ±0.2 V or VCC ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE »0, CE »1 = VIL,
BYTE = VIL or VIH
Inputs = VIL or VIH
f = 8 MHz, IOUT = 0 mA
30
35
1
1, 3, 4
ICCR2
VCC Read Current
15
20
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = VCC ±0.2 V or GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
1, 3, 4
TTL: CE »0, CE »1 = VIL,
BYTE = VIH or VIL
Inputs = VIL or VIH
f = 4 MHz, IOUT = 0 mA
ICCW
VCC Write Current
8
12
mA
Word/Byte Write in Progress
1
ICCE
VCC Block Erase Current
6
12
mA
Block Erase in Progress
1
ICCES
VCC Erase Suspend
Current
3
6
mA
CE »0, CE »1 = VIH
Block Erase Suspended
1, 2
IPPS
VPP Standby Current
±1
±10
µA
VPP ≤ VCC
1
IPPD
VPP Deep Power-Down
Current
0.2
5
µA
RP » = GND ±0.2 V
1
19
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
DC Characteristics (Continued)
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
3/5 » = Pin Set High for 3.3 V Operations
SYMBOL
PARAMETER
TYPE
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
200
µA
VPP > VCC
1
IPPR
VPP Read Current
IPPW
VPP Write Current
40
60
mA
VPP = VPPH, Word/Byte
Write in Progress
1
IPPE
VPP Erase Current
20
40
mA
VPP = VPPH,
Block Erase in Progress
1
IPPES
VPP Erase Suspend
Current
200
µA
VPP = VPPH,
Block Erase Suspended
1
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.3
V
VOL
Output Low Voltage
0.4
V
VCC = VCC MIN. and
IOL = 4 mA
2.4
V
IOH = -2.0 mA
VCC = VCC MIN.
VCC - 0.2
V
IOH = -100 µA
VCC = VCC MIN.
VOH1
Output High Voltage
VOH
2
VPPL
VPP during Normal
Operations
VPPH
VPP during Write/Erase
Operations
VLKO
VCC Erase/Write
Lock Voltage
5.0
0.0
5.5
V
4.5
5.5
V
2.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3 V, VPP = 5.0 V, T = 25°C. These currents are valid for all
product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Automatic Power Saving (APS) reduces ICCR to less than 1 mA in Static operation.
4. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.
20
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
DC Characteristics
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
3/5 » Pin Set Low for 5 V Operations
SYMBOL
PARAMETER
TYP.
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IIL
Input Load Current
±1
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±10
µA
VCC = VCC MAX., VIN = VCC or GND
1
µA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VCC ±0.2 V
BYTE, WP, 3/5 » = V CC ±0.2 V or GND
±0.2 V
1,4
5
ICCS
ICCD
ICCR1
10
VCC Standby Current
VCC Deep Power-Down
Current
VCC Read Current
2
4
mA
VCC = VCC MAX.,
CE »0, CE »1, RP » = VIH
BYTE, WP, 3/5 » = V IH or V IL
1
5
µA
RP » = GND ±0.2 V
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = GND ±0.2 V or VCC ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
TTL: CE »0, CE »1 = VIL,
BYTE = VIL or VIH
Inputs = VIL or VIH
f = 10 MHz, IOUT = 0 mA
50
60
1
1, 3, 4
ICCR2
VCC Read Current
30
35
mA
VCC = VCC MAX.,
CMOS: CE »0, CE »1 = GND ±0.2 V
BYTE = VCC ±0.2 V or GND ±0.2 V
Inputs = GND ±0.2 V or VCC ±0.2 V
1, 3, 4
TTL: CE »0, CE »1 = VIL,
BYTE = VIH or VIL
Inputs = VIL or VIH
f = 5 MHz, IOUT = 0 mA
ICCW
VCC Write Current
25
35
mA
Word/Byte Write in Progress
1
ICCE
VCC Block Erase Current
18
25
mA
Block Erase in Progress
1
ICCES
VCC Erase Suspend
Current
5
10
mA
CE »0, CE »1 = VIH
Block Erase Suspended
1, 2
IPPS
VPP Standby Current
±10
µA
VPP ≤ VCC
1
IPPD
VPP Deep Power-Down
Current
5
µA
RP » = GND ±0.2 V
1
0.2
21
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
DC Characteristics (Continued)
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
3/5 » Pin Set Low for 5 V Operations
SYMBOL
PARAMETER
TYPE
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
IPPR
VPP Read Current
65
200
µA
VPP > VCC
1
IPPW
VPP Write Current
40
60
mA
VPP = VPPH, Word/Byte
Write in Progress
1
IPPE
VPP Erase Current
20
40
mA
VPP = VPPH,
Block Erase in Progress
1
IPPES
VPP Erase Suspend
Current
65
200
µA
VPP = VPPH,
Block Erase Suspended
1
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.5
V
VOL
Output Low Voltage
0.45
V
VCC = VCC MIN. and
IOL = 5.8 mA
0.85 VCC
V
IOH = -2.5 mA
VCC = VCC MIN.
VCC - 0.4
V
IOH = -100 µA
VCC = VCC MIN.
VOH1
Output High Voltage
VOH
2
VPPL
VPP during Normal
Operations
VPPH
VPP during Write/Erase
Operations
VLKO
VCC Erase/Write
Lock Voltage
5.0
0.0
5.5
V
4.5
5.5
V
2.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 5.0 V, T = 25°C. These currents are valid for all
product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation.
4. CMOS Inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL Inputs are either VIL or VIH.
22
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
AC Characteristics - Read Only Operations1
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 3.3 V ± 0.3V
MIN.
MAX.
VCC = 2.7 - 3.6 V
MIN.
UNITS
NOTE
MAX.
tAVAV
Read Cycle Time
120
160
ns
tAVEL
Address Setup to CE » Going Low
10
10
ns
3, 4
tAVGL
Address Setup to OE » Going Low
0
0
ns
3, 4
tAVQV
Address to Output Delay
120
160
ns
tELQV
CE » to Output Delay
120
160
ns
tPHQV
RP » High to Output Delay
620
650
ns
tGLQV
OE » to Output Delay
45
45
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
tOH
Output Hold from Address, CE » or
OE » change, whichever occurs first
0
0
50
0
50
0
30
0
30
0
2
tFLQV
tFHQV
BYTE to Output Delay
120
160
ns
3
tFLQZ
BYTE Low to Output in High Z
30
30
ns
3
tELFL
tELFH
CE » Low to BYTE High or Low
5
5
ns
3
23
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
AC Characteristics - Read Only Operations1 (Continued)
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 5.0 V ± 0.25V
MIN.
MAX.
VCC = 5.0 V ± 0.5V
MIN.
NOTE
tAVAV
Read Cycle Time
70
80
ns
tAVEL
Address Setup to CE » Going Low
10
10
ns
3, 4
tAVGL
Address Setup to OE » Going Low
0
0
ns
3, 4
tAVQV
Address to Output Delay
70
80
ns
tELQV
CE » to Output Delay
70
80
ns
tPHQV
RP » High to Output Delay
400
480
ns
tGLQV
OE » to Output Delay
30
35
ns
2
tELQX
CE » to Output in Low Z
ns
3
tEHQZ
CE » to Output in High Z
ns
3
tGLQX
OE » to Output in Low Z
ns
3
tGHQZ
OE » to Output in High Z
ns
3
ns
3
tOH
Output Hold from Address, CE » or
OE » change, whichever occurs first
0
0
25
0
30
0
25
0
30
0
2
tFLQV
tFHQV
BYTE to Output Delay
70
80
ns
3
tFLQZ
BYTE Low to Output in High Z
25
30
ns
3
tELFL
tELFH
CE » Low to BYTE High or Low
5
5
ns
3
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements.
2. OE » may be delayed up to t ELQV - tGLQV after the falling edge of CE » without impact on tELQV.
3. Sampled, not 100% tested.
4. This timing parameter is used to latch the correct BSR data onto the outputs.
24
UNITS
MAX.
8M (512K × 16, 1M × 8) Flash Memory
VCC POWER-UP
ADDRESSES (A)
STANDBY
LH28F800SU
DEVICE AND
ADDRESS
SELECTION
VIH
VIL
OUTPUTS ENABLED
DATA VALID
ADDRESSES STABLE
...
...
STANDBY
VCC
POWER-DOWN
tAVAV
CEX (E)
(NOTE)
VIH
...
VIL
tAVEL
OE (G)
tEHQZ
VIH
...
VIL
tAVGL
WE (W)
tGHQZ
...
VIH
VIL
tGLQV
tELQV
tOH
tGLQX
tELQX
DATA (D/Q)
VOH
...
HIGH-Z
VALID OUTPUT
HIGH-Z
...
VOL
tAVQV
VCC
5.0 V
GND
tPHQV
RP (P)
VIH
VIL
NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
28F800SUR-10
Figure 12. Read Timing Waveforms
25
LH28F800SU
ADDRESSES (A)
8M (512K × 16, 1M × 8) Flash Memory
...
VIH
VIL
ADDRESSES STABLE
...
tAVAV
CEX (E)
(NOTE)
VIH
VIL
...
tEHQZ
tAVFL = tELFL
OE (G)
VIH
VIL
tAVEL
tELFL
...
tGHQZ
tAVGL
tFLQV = tAVQV
tGLQV
BYTE (F)
VIH
VIL
...
tELQV
tOH
tGLQX
tELQX
DATA (DQ0 - DQ7)
VOH
...
...
HIGH-Z
DATA OUTPUT
VOL
DATA
OUTPUT
HIGH-Z
tAVQV
tFLQZ
DATA (DQ8 - DQ15)
VOH
VOL
HIGH-Z
DATA
OUTPUT
NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
Figure 13. BY T
» E » Timing Waveforms
26
HIGH-Z
28F800SUR-11
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
tPLPH
RP (P)
ADDRESS (A)
VALID
tAVQV
DATA (Q)
VALID
tPHQV
tPLPH
RP (P)
tYHPH
tYLPH
3/5 (Y)
tPLYL
5.0 V
3.3 V
VCC (3 V, 5 V)
4.5 V
3.0 V
0V
t3VPH
tPL5V
ADDRESS (A)
VALID
tAVQV
DATA (Q)
t5VPH
VALID
tAVQV
VALID
tPHQV
VALID
tPHQV
28F800SUR-12
Figure 14. VCC Power-Up and RP » Reset Waveforms
27
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
NOTE
tPLYL
tPLYH
RP » Low to 3/5 » Low (High)
0
µs
tYLPH
tYHPH
3/5 » Low (High) to RP » High
2
µs
1
tPL5V
tPL3V
RP » Low to VCC at 4.5 V MIN.
(to VCC at 3.0 V min or 3.6 V MAX.)
0
µs
2
tPLPH
RP » 'Low'
100
ns
t5VPH
VCC at 4.5 V to RP » High
100
ns
3
t3VPH
VCC at 3.0 V to RP » High
100
ns
3
tAVQV
Address Valid to Data Valid for VCC = 5 V ± 10%
100
ns
4
tPHQV
RP » High to Data Valid for VCC = 5 V ± 10%
480
ns
4
NOTES:
CE »0, CE »1 and OE » are switched low after Power-Up.
1. Minimum of 2 µs is required to meet the specified tPHQV times.
2. The power supply may start to switch concurrently with RP » going Low. RP » is required to stay low, until VCC stays at recommended
operating voltage.
3. The address access time and RP » high to data valid time are shown for 5 V VCC operation. Refer to the AC Characteristics Read Only
Operations 3.3 V VCC operation and all other speed options.
28
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
AC Characteristics for WE » - Controlled Command Write Operations1
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 3.3 ± 0.3 V
TYP.
MIN.
MAX.
NOTE
UNITS
tAVAV
Write Cycle Time
120
ns
tVPWH
VPP Setup to WE Going High
100
ns
tPHEL
RP » Setup to CE » Going Low
480
ns
tELWL
CE » Setup to WE Going Low
10
ns
tAVWH
Address Setup to WE Going High
75
ns
2, 6
tDVWH
Data Setup to WE Going High
75
ns
2, 6
tWLWH
WE Pulse Width
75
ns
tWHDX
Data Hold from WE High
10
ns
2
tWHAX
Address Hold from WE High
10
ns
2
tWHEH
CE » Hold from WE High
10
ns
tWHWL
WE Pulse Width High
45
ns
tGHWL
Read Recovery before Write
0
ns
tWHRL
WE High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
ns
tPHWL
RP » High Recovery to WE Going Low
1
µs
tWHGL
Write Recovery before Read
95
ns
tQVVL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
µs
5
µs
4, 5
0.3
s
4
tWHQV1
Duration of Word/Byte Write Operation
tWHQV2
Duration of Block Erase Operation
100
12
3
ns
3
29
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
AC Characteristics for WE » - Controlled Command Write Operations1 (Continued)
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 5.0 ± 0.25 V
TYP.
MIN.
MAX.
VCC = 5.0 ± 0.5 V
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
70
80
ns
tVPWH
VPP Setup to WE Going High
100
100
ns
tPHEL
RP » Setup to CE » Going Low
480
480
ns
tELWL
CE » Setup to WE Going Low
0
0
ns
tAVWH
Address Setup to WE Going High
50
50
ns
2, 6
tDVWH
Data Setup to WE Going High
50
50
ns
2, 6
tWLWH
WE Pulse Width
40
50
ns
tWHDX
Data Hold from WE High
0
0
ns
2
tWHAX
Address Hold from WE High
10
10
ns
2
tWHEH
CE » Hold from WE High
10
10
ns
tWHWL
WE Pulse Width High
30
30
ns
tGHWL
Read Recovery before Write
0
0
ns
tWHRL
WE High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
0
ns
tPHWL
RP » High Recovery to WE Going Low
1
1
µs
tWHGL
Write Recovery before Read
60
65
ns
tQVVL
VPP Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY »/BY » High
0
0
µs
4.5
µs
4, 5
0.3
s
4
tWHQV1
Duration of Word/Byte Write Operation
tWHQV2
Duration of Block Erase Operation
100
8
4.5
0.3
NOTES:
CE » is defined as the latter of CE »0 or CE »1 going Low or the first of CE »0 or CE »1 going High.
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE » for all Command Write Operations.
30
100
8
3
ns
3
8M (512K × 16, 1M × 8) Flash Memory
DEEP
POWER-DOWN
LH28F800SU
WRITE VALID
WRITE
ADDRESS AND DATA
DATA-WRITE
(DATA-WRITE) OR
OR ERASE
ERASE CONFIRM
SETUP COMMAND
COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
WRITE READ
EXTENDED
REGISTER
COMMAND
READ
EXTENDED
STATUS
REGISTER DATA
AIN
tAVAV
A = RA
tAVWH
ADDRESSES (A) VIH
(NOTE 2)
VIL
READ
COMPATIBLE
STATUS
REGISTER DATA
tWHAX
(NOTE 3)
AIN
A = RA
tAVWH tWHAX
tAVAV
CEX (E) VIH
(NOTE 4) V
IL
tWHGL
tWHEH
tELWL
OE (G)
VIH
VIL
tWHWL
tWHQV1, 2
tGHWL
VIH
VIL
WE (W)
tWLWH
tWHDX
tDVWH
DATA (D/Q)
VIH
VIL
HIGH-Z
DIN
DIN
tPHWL
RY/BY (R)
DIN
DOUT
DIN
tWHRL
VOH
VOL
tRHPL
RP (P)
VIH
VIL
(NOTE 5)
tVPWH
VPP (V)
tQVVL
VPPH
VPPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
5. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F800SUR-13
Figure 15. AC Waveforms for Command Write Operations
31
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
AC Characteristics for CE » - Controlled Command Write Operations1
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 3.3 V ±0.3 V
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
120
ns
tPHWL
RP » Setup to WE Going Low
480
ns
3
tVPEH
VPP Setup to CE » Going High
100
ns
3
tWLEL
WE Setup to CE » Going Low
0
ns
tAVEH
Address Setup to CE » Going High
75
ns
2, 6
tDVEH
Data Setup to CE » Going High
75
ns
2, 6
tELEH
CE » Pulse Width
75
ns
tEHDX
Data Hold from CE » High
10
ns
2
tEHAX
Address Hold from CE » High
10
ns
2
tEHWH
WE Hold from CE » High
10
ns
tEHEL
CE » Pulse Width High
45
ns
tGHEL
Read Recovery before Write
0
ns
tEHRL
CE » High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
ns
tPHEL
RP » High Recovery to CE » Going Low
1
µs
tEHGL
Write Recovery before Read
95
ns
tQVVL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
µs
tEHQV1
Duration of Word/Byte Write Operation
5
µs
4, 5
tEHQV2
Duration of Block Erase Operation
0.3
s
4
32
100
12
ns
3
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
AC Characteristics for CE » - Controlled Command Write Operations1 (Continued)
TA = 0°C to +70°C
SYMBOL
PARAMETER
VCC = 5.0 V ± 0.25 V
VCC = 5.0 V ± 0.5 V
TYP.
TYP.
MIN.
MAX.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
70
80
ns
tPHWL
RP » Setup to WE Going Low
480
480
ns
3
tVPEH
VPP Setup to CE » Going High
100
100
ns
3
tWLEL
WE Setup to CE » Going Low
0
0
ns
tAVEH
Address Setup to CE » Going High
50
50
ns
2, 6
tDVEH
Data Setup to CE » Going High
50
50
ns
2, 6
tELEH
CE » Pulse Width
40
50
ns
tEHDX
Data Hold from CE » High
0
0
ns
2
tEHAX
Address Hold from CE » High
10
10
ns
2
tEHWH
WE Hold from CE » High
10
10
ns
tEHEL
CE » Pulse Width High
30
30
ns
tGHEL
Read Recovery before Write
0
tEHRL
CE » High to RY »/BY » Going Low
tRHPL
RP » Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
0
ns
tPHEL
RP » High Recovery to CE » Going Low
1
1
µs
tEHGL
Write Recovery before Read
60
65
ns
tQVVL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY »/BY » High
0
0
µs
tEHQV1
Duration of Word/Byte Write Operation
4.5
4.5
µs
4, 5
tEHQV2
Duration of Block Erase Operation
0.3
0.3
s
4
ns
100
8
100
ns
3
NOTES:
CE » is defined as the latter of CE »0 or CE »1 going Low or the first of CE »0 or CE »1 going High.
1. Read timing during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE » for all Command Write Operations.
33
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
DEEP
POWER-DOWN
WRITE VALID
ADDRESS AND DATA
WRITE
(DATA-WRITE) OR
DATA-WRITE
ERASE CONFIRM
OR ERASE
COMMAND
SETUP COMMAND
ADDRESSES (A) VIH
(NOTE 1)
VIL
AUTOMATED
DATA-WRITE
OR ERASE
DELAY
WRITE READ
EXTENDED
REGISTER
COMMAND
READ
EXTENDED
STATUS
REGISTER DATA
AIN
tAVAV
A = RA
tAVEH
ADDRESSES (A) VIH
(NOTE 2)
VIL
(NOTE 3)
AIN
tAVEH
tAVAV
READ
COMPATIBLE
STATUS
REGISTER DATA
tEHAX
tEHAX
VIH
VIL
WE (W)
tEHWH
tWLEL
OE (G)
tEHGL
VIH
VIL
tEHEL
tEHQV1, 2
tGHEL
CEX (E) VIH
(NOTE 4) VIL
tELEH
tEHDX
tDVEH
DATA (D/Q)
VIH
VIL
HIGH-Z
DIN
DIN
tPHEL
RY/BY (R)
DIN
DOUT
DIN
tEHRL
VOH
VOL
tRHPL
RP (P)
VIH
VIL
(NOTE 5)
tVPEH
VPP (V)
tQVVL
VPPH
VPPL
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
5. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 16. Alternate AC Waveforms for Command Write Operations
34
28F800SUR-14
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
AC Characteristics for Page Buffer Write Operations1
TA = 0°C to +70°C
SYMBOL
VCC = 3.3 V ± 0.3 V
PARAMETER
TYP.
tAVAV
Write Cycle Time
tELWL
MIN.
UNITS
NOTE
MAX.
120
ns
CE » Setup to WE Going Low
10
ns
tAVWL
Address Setup to WE Going Low
0
ns
3
tDVWH
Data Setup to WE Going High
75
ns
2
tWLWH
WE Pulse Width
75
ns
tWHDX
Data Hold from WE High
10
ns
2
tWHAX
Address Hold from WE High
10
ns
2
tWHEH
CE » Hold from WE High
10
ns
tWHWL
WE Pulse Width High
45
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
95
ns
SYMBOL
PARAMETER
VCC = 5.0 V ± 0.25 V
TYP.
MIN.
MAX.
VCC = 5.0 V ± 0.5 V
TYP.
MIN.
UNITS
NOTE
MAX.
tAVAV
Write Cycle Time
70
80
ns
tELWL
CE » Setup to WE Going Low
0
0
ns
tAVWL
Address Setup to WE Going Low
0
0
ns
3
tDVWH
Data Setup to WE Going High
50
50
ns
2
tWLWH
WE Pulse Width
40
50
ns
tWHDX
Data Hold from WE High
0
0
ns
2
tWHAX
Address Hold from WE High
10
10
ns
2
tWHEH
CE » Hold from WE High
10
10
ns
tWHWL
WE Pulse Width High
30
30
ns
tGHWL
Read Recovery before Write
0
0
ns
tWHGL
Write Recovery before Read
60
65
ns
NOTES:
CE » is defined as the latter of CE »0 or CE »1 going Low or the first of CE »0 or CE »1 going High.
1. These are WE » controlled write timings, equivalent CE » controlled write timings apply.
2. Sampled, but not 100% tested.
3. Address must be valid during the entire WE » Low pulse.
35
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
tWHEH
CEX (E)
tELWL
WE (W)
tAVWL
tWLWH
tWHWL
tWHAX
ADDRESSES (A)
VALID
tDVWH
DATA (D/Q)
HIGH-Z
tWHDX
DIN
28F800SUR-15
Figuer 17. Page Buffer Write Timing Waveforms
Erase and Word/Byte Write Performance
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.(1)
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
tWHRH1
Word/Byte Write Time
12
tWHRH2
Block Write Time
0.8
2.1
s
Byte Write Mode
2
tWHRH3
Block Write Time
0.4
1.0
s
Word Write Mode
2
Block Erase Time
0.9
10
s
2
Full Chip Erase Time
14.4
s
2
µs
2
VCC = 5.0 V ± 0.5 V, TA = 0°C to +70°C
SYMBOL
PARAMETER
TYP.(1)
MIN.
MAX.
UNITS
TEST CONDITIONS
NOTE
tWHRH1
Word/Byte Write Time
tWHRH2
Block Write Time
0.54
2.1
s
Byte Write Mode
2
tWHRH3
Block Write Time
0.27
1.0
s
Word Write Mode
2
Block Erase Time
0.7
10
s
2
Full Chip Erase Time
11.2
s
2
NOTES:
1. 25°C, VPP = 5.0 V.
2. Excludes System-Level Overhead.
36
8
µs
2
8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
56TSOP (TSOP056-P-1420)
56
1
14.20 [0.559]
13.80 [0.543]
0.50 [0.020] TYP.
0.28 [0.011]
0.12 [0.005]
29
28
0.13 [0.005]
0.49 [0.019]
0.39 [0.015]
20.30 [0.799]
19.70 [0.776]
18.60 [0.732]
18.20 [0.717]
0.22 [0.009]
0.02 [0.001]
1.10 [0.043]
0.90 [0.035]
1.19 [0.047] MAX.
0.18 [0.007]
0.08 [0.003]
PACKAGE BASE PLANE
19.30 [0.760]
18.70 [0.736]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
56TSOP
ORDERING INFORMATION
LH28F800SU
Device Type
T
Package
-##
Speed
70 Access Time (ns)
56-pin, 1.2 mm x 14 mm x 20 mm TSOP (Type I) (TSOP056-P-1420)
8M (512K x 16, 1M x 8) Flash Memory
Example: LH28F800SUT-70 (8M (512K x 16, 1M x 8) Flash Memory, 70 ns, 56-pin TSOP)
28F800SUR-16
37
LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications
where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
WARRANTY
SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for
a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair
or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the
failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its
return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or
which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The
warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY
EXCLUDED.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
®
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation
Microelectronics Group
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Telex: 2161867 (HEEG D)
Facsimile: (49) 40 2376-2232
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1997 by SHARP Corporation
Issued May 1996
Reference Code SMT96107