SHARP LRS1338A

LRS1338A
Data Sheet
Stacked Chip
8M Flash Memory and 2M SRAM
FEATURES
PIN CONFIGURATION
• Flash memory and SRAM
• Stacked die chip scale package
• 48-pin TSOP (TSOP48-P-1014) plastic package
48-PIN TSOP
TOP VIEW
S-A16/F-A15
1
48
S-A17/F-A16
S-A15/F-A14
2
47
I/O15
• Operating temperature: -40°C to +85°C
S-A14/F-A13
3
46
I/O7
• Access time (MAX.):
– Flash memory: 120 ns
– SRAM: 85 ns
S-A13/F-A12
4
45
I/O14
• Power supply: 2.7 V to 3.6 V
• Operating current (MAX.):
– Flash memory
– Read: 25 mA (tCYCLE = 200 ns)
– Word write: 57 mA (F-VCC ≥ 3.0 V)
– Block erase: 42 mA (F-VCC ≥ 3.0 V)
– SRAM: 25 mA (tCYCLE = 200 ns)
• Standby current2
– Flash memory: 20 µA MAX. (F-CE ≥ F-VCC - 0.2 V,
F-RP ≤ 0.2 V, F-VPP ≤ 0.2 V)
– SRAM:
– 40 µA MAX. (S-CE ≥ S-VCC - 0.2 V)
– 0.6 µA TYP. (TA = 25°C, S-VCC = 3 V,
S-CE ≥ S-VCC - 0.2 V)
• Fully static operation
• Three-state output
NOTES:
1. Block erase and word write operations of flash memory with
TA < -30°C are not supported.
2. Total standby current is the summation of flash’s memory standby
current and SRAM’s one.
DESCRIPTION
The LRS1338A is a combination memory organized
as 524,288 × 16-bit flash memory and 262,144 × 8-bit
static RAM in one package. It is fabricated using silicongate CMOS process technology.
Data Sheet
S-A12/F-A11
5
44
S-CE
S-A11/F-A10
6
43
I/O6
S-A10/F-A9
7
42
I/O13
S-A9/F-A8
8
41
I/O5
S-OE
9
40
I/O12
F-WE
10
39
I/O4
F-RP
11
38
F-VCC
F-VPP
12
37
I/O11
S-VCC
13
36
I/O3
F-WP
14
35
I/O10
F-A18
15
34
I/O2
F-A17
16
33
I/O9
S-A8/F-A7
17
32
I/O1
S-A7/F-A6
18
31
S-WE
S-A6/F-A5
19
30
I/O8
S-A5/F-A4
20
29
I/O0
S-A4/F-A3
21
28
F-OE
S-A3/F-A2
22
27
GND
S-A2/F-A1
23
26
F-CE
S-A0
24
25
S-A1/F-A0
LRS1338A-1
Figure 1. LRS1338A Pin Configuration
1
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
F-VCC
F-VPP
F-CE
I/O8 to
I/O15
F-OE
F-WE
F-RP
524,288 x 16 BIT
FLASH MEMORY
I/O0 to
I/O7
F-WP
F-A17, F-A18
GND
S-A1 to S-A17,
F-A0 to F-A16
S-A0
S-CE
262,144 x 8 BIT
SRAM
S-OE
S-WE
S-VCC
LRS1338A-2
Figure 2. LRS1338A Block Diagram
Table 1. Pin Descriptions
PIN
S-A1 to S-A17
F-A0 to F-A16
Common Address Input Pins
S-A0
Address Input Pin for SRAM
F-A17 to F-A18
Address Input Pin for Flash Memory
F-CE
Chip Enable Input Pin for Flash Memory
S-CE
Chip Enable Input Pin for SRAM
F-WE
Write Enable Input Pin for Flash Memory
S-WE
Write Enable Input Pin for SRAM
F-OE
Output Enable Input Pin for Flash Memory
S-OE
Output Enable Input Pin for SRAM
I/O0 to I/07
I/O8 to I/O15
Common Data Input/Output Pins
Data Input/Output Pins for Flash Memory
F-RP
Reset/Deep Power Down Input Pin for Flash Memory
F-WP
Write Protect Pin for Flash Memory’s Boot Block
F-VCC
Power Supply Pin for Flash Memory
F-VPP
Power Supply Pin for Flash Memory Write/Erase
S-VCC
Power Supply Pin for SRAM
GND
2
DESCRIPTION
Common Ground
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
CASE 2: FLASH MEMORY IS IN DEEP POWER
DOWN MODE (F-VCC = 2.7 V TO 3.6 V)
• SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-VCC + 0.3 V or to be open.
GENERAL DESIGN GUIDELINES
Supply Power
Maximum difference (between F-VCC and S-VCC) of
the voltage is less than 0.3 V.
• Flash Memory inputs and input/outputs except RP
need to be applied with voltages in the range of -0.3 V
to S-VCC + 0.3 V or to be open (HIGH-Z). RP needs to
be at the same level as F-VCC or to be open.
Power Supply and Chip Enable of Flash
Memory and SRAM
It is forbidden that both F-CE and S-CE should be
LOW simultaneously. If the two memories are active
together, they many not operate normally due to interference noises or data collision on I/O bus. Both F-VCC
and S-VCC need to be applied by the recommended
supply voltage at the same time except SRAM data
retention mode.
CASE 3: FLASH MEMORY POWER SUPPLY IS
TURNED OFF (F-VCC = 0 V)
• Fix RP LOW level before turning off Flash memory
power supply.
• SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-VCC + 0.3 V or to be open (HIGH-Z).
SRAM Data Retention
SRAM data retention is capable in three ways.
SRAM power switching between a system battery and
a backup battery needs careful device decoupling from
Flash Memory to prevent SRAM supply voltage from
falling lower than 2.0 V by a Flash Memory peak current caused by transition of Flash Memory supply voltage or of control signals (F-CE, F-OE, and RP).
• Flash Memory inputs and input/outputs except RP
need to be applied with voltages in the range of
-0.3 V to S-VCC + 0.3 V or to be open (HIGH-Z).
Power Up Sequence
When turning on Flash memory power supply, keep
RP LOW. After F-VCC reaches over 2.7 V, keep RP
LOW for more than 100 ns.
CASE 1: FLASH MEMORY IS IN STANDBY MODE
(F-VCC = 2.7 V TO 3.6 V)
• SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-VCC + 0.3 V or to be open (HIGH-Z).
Device Decoupling
The power supply needs to be designed carefully
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE).
• Flash Memory inputs and input/outputs except F-CE
and RP need to be applied with voltages in the range
of -0.3 V to S-VCC + 0.3 V or to be open (HIGH-Z).
Table 2. Truth Table1,2
F-CE
F-OE
F-WE
F-RP
S-CE
S-OE
S-WE
ADDRESS
MODE
I/O0 to
I/O15
CURRENT
NOTE
L
L
H
H
H
X
X
X
Flash read
Output
ICC
3, 4
L
H
H
H
H
X
X
X
Flash read
HIGH-Z
ICC
5
L
H
L
H
H
X
X
X
Flash write
Input
ICC
4, 6, 7
H
X
X
X
L
L
H
X
SRAM read
Output
ICC
H
X
X
X
L
H
H
X
SRAM read
HIGH-Z
ICC
H
X
X
X
L
X
L
X
SRAM write
Input
ICC
H
X
X
H
H
X
X
X
Standby
HIGH-Z
ISB
X
X
X
L
H
X
X
X
Deep power down
HIGH-Z
ISB
NOTES:
1. F-CE should not be LOW when S-CE is LOW simultaneously.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH
for F-VPP. See DC Characteristics for VPPLK and VPPH voltages.
3. Refer to DC Characteristics. When F-VPP ≤ VPPLK, memory contents can be read, but not altered.
4. Do not use in a timing that both F-OE and F-WE is LOW level.
Data Sheet
5
5. F-RP at GND ± 0.2 V ensures the lowest deep power down current.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when F-VPP = VPPH and F-VCC = VCC1
block erase or word write operations with VIH < F-RP < VHH or
TA < -30°C produce spurious results and should not be attempted.
7. Refer to Table 6 for valid DIN during a write operation.
3
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATINGS
UNIT
NOTES
Supply voltage
VCC
-0.2 to +4.6
V
1, 2
Input voltage
VIN
-0.3 to VCC +0.3
V
1, 3, 4
Operating temperature
TOPR
-40 to +85
°C
Storage temperature
TSTG
-65 to +125
°C
VPP voltage
VPP
-0.2 to +12.6
V
1, 5
Input voltage
RP
-0.5 to +12.6
V
1, 4, 5
NOTES:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except VPP.
3. Except RP.
4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
5. +14.0 V overshoot is allowed when the pulse width is less than 20 ns.
RECOMMENDED DC OPERATING CONDITIONS
TA = -40°C to +85°C
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
VCC
2.7
3.0
3.6
V
VIH
2.0
VCC + 0.3
V
1
VIL
-0.3
0.8
V
2
VHH
11.4
12.6
Input voltage
NOTES
3
NOTES:
1. VCC is the lower one of S-VCC and F-VCC.
2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
3. This voltage is applicable to F-RP pin only.
PIN CAPACITANCE
TA = 25°C, f = 1 MHz
PARAMETER
SYMBOL
CONDITION
Input capacitance*
CIN
I/O capacitance*
CI/O
MIN.
TYP.
MAX.
UNIT
VIN = 0 V
20
pF
VI/O = 0 V
22
pF
NOTE: *Sampled by not 100% tested.
4
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to + 85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
CONDITION
MIN.
TYP.
MAX. UNIT NOTES
ILI
VIN = 0V to VCC
-1.5
1.5
µA
Output leakage current
ILO
F-CE, S-CE = VIH or F-OE, S-OE = VIH or
F-WE, S-WE = VIH, VI/O = 0 V to VCC
-1.5
1.5
µA
Read current, F-VPP ≤ F-VCC,
F-CE ≤ 0.2 V, VIN ≥ VCC – 0.2 V or
VIN ≤ 0.2 V
tCYCLE = 200 ns, II/O = 0 mA
25
mA
1
Summation of VCC Byte Write or set lock-bit current, and VPP Byte Write or set lock-bit current.
F-VCC ≥ 3.0 V
57
mA
2, 3
Summation of VCC Block Erase or Clear Block
lock-bits current, and VPP Block Erase or Clear
Block lock-bits current. F-VCC ≥ 3.0 V
42
mA
2, 4
S-CE = 0.2 V, VIN ≥ VCC – 0.2 V or VIN ≥ 0.2 V
tCYCLE = 200 ns, II/O = 0 mA
25
mA
5
F-CE = VIH, RP = VIH
2.0
mA
6
Standby current
Output voltage
SRAM Flash SRAM
Operating supply
current
Flash
Input leakage current
ICC
ICC
ISB
ISB
VOL,
VOH
F-CE ≥ VCC – 0.2 V, RP ≤ 0.2 V
20
µA
7
S-CE = VIH
3.0
mA
8
40
µA
9, 10
0.4
V
S-CE ≥ VCC – 0.2 V
IOL = 2.0 mA
IOH = 1.0 mA
NOTES:
1. This value is read current (ICCR + IPPR) of flash memory.
2. Sampled but not 100% tested.
3. This value is operation current (ICCW + IPPW) of flash memory.
4. This value is operation current (ICCE + IPPE) of flash memory.
5. This value is operation current (ICC1) of SRAM.
Data Sheet
0.6
2.4
V
6. This value is standby current (ICCS + IPPS) of flash memory.
7. This value is deep power down current (ICCD + IPPD) of
flash memory.
8. This value is standby current (ISB1) of SRAM
9. This value is standby current (ISB) of SRAM.
10. Reference values at VCC = 3.0 V and TA = +25°C
5
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
FLASH MEMORY*
New Features
The LRS1388A flash memory maintains backwards
compatibility with SHARP’s LH28F800BG-L.
• SmartVoltage technology
• Enhanced suspend capabilities
• Boot block architecture
Please note the following important differences:
• VPPLK has been lowered to 1.5 V to support 3.0 V
block erase and word write operations. Designs that
switch VPP off during read operations should make
sure that the VPP voltage transitions to GND.
• Allow VPP connection to 3.0 V.
Product Overview
The LRS1338A is a high-performance 8M SmartVoltage flash memory organized as 512K-word of 16
bits. The 512K-word of data is arranged in two 4K-word
boot blocks, six 4K-word parameter blocks and fifteen
32K-word main blocks which are individually erasable
in-system. The memory map is shown in Figure 4.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 3, to meet
system performance and power expectations. In addition to flexible erase and program voltages, the dedicated V PP pin gives complete data protection when
VPP ≤ VPPLK.
Table 3. VCC and VPP Voltage Combinations
VCC Voltage
VPP Voltage
2.7 V to 3.6 V
2.7 V to 3.6 V
Internal VCC and VPP detection circuitry automatically configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes
the algorithms and timings necessary for block erase
and word write operations.
A block erase operation erases on e of the device’s
32K-word blocks typically within 1.14 seconds, 4Kword blocks typically within 0.38 seconds independent
of other blocks. Each block can be independently
erased 100,000 times. Block erase suspend mode
allows system software to suspend block erase to read
or write data from any other block.
Writing memory data is performed in word increments
of the device’s 32K-word blocks typically within 44.6 µs,
4K-word blocks typically within 45.9 µs. Word write suspend mode enables the system to read data or execute
code from any other flash memory array location.
The boot blocks can be locked for the WP pin. Block
erase or word write for boot block must not be carried
out by WP to LOW and RP to VIH.
The status register indicates when the WSM’s block
erase or word write operation is finished.
The access time is 120 ns (tAVQV) over the commercial temperature range (-40°C to +85°C) and VCC supply voltage range of 2.7 V to 3.6 V.
The Automatic Power Savings (APS) feature substantially reduces active current when the device is in
static mode (addresses not switching). In APS mode,
the typical ICCR current is 1 mA at 3.3 V VCC.
When CE and RP pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (t PHQV) is required from RP
switching HIGH until outputs are valid. Likewise, the
device has a wake time (tPHEL) from RP HIGH until
writes to the CUI are recognized. With RP at GND, the
WSM is reset and the status register is cleared.
NOTE: *In the Flash Memory section all reference to pins, commands, voltage, etc. refer only to the Flash portion of this chip.
6
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
I/O0 - I/O15
INPUT
BUFFER
OUTPUT
BUFFER
I/O
LOGIC
DATA
REGISTER
VCC
IDENTIFIER
REGISTER
OUTPUT
MULTIPLEXER
CE
WE
OE
RP
WP
COMMAND
USER
REGISTER
STATUS
REGISTER
PROGRAM/ERASE
VOLTAGE
SWITCH
WRITE
STATE
MACHINE
DATA
COMPARATOR
VPP
VCC
GND
MAIN BLOCK 14
15
32K-WORD
BLOCKS
MAIN BLOCK 13
MAIN BLOCK 1
MAIN BLOCK 0
PARAMETER BLOCK 5
PARAMETER BLOCK 4
PARAMETER BLOCK 3
PARAMETER BLOCK 2
PARAMETER BLOCK 1
BOOT BLOCK 1
ADDRESS
COUNTER
X
DECODER
Y GATING
PARAMETER BLOCK 0
ADDRESS
LATCH
Y
DECODER
BOOT BLOCK 0
INPUT
BUFFER
...
A0 - A18
...
LRS1338A-3
Figure 3. Flash Memory Block Diagram
Data Sheet
7
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
Table 4. Flash Pin Descriptions
SYMBOL
TYPE
A0 - A18
Input
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during the write cycle.
I/O0 - I/O15
Input/Output
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data
pins float to HIGH-impedance when the chip is deselected or outputs are disabled.
Data is internally latched during a write cycle.
CE
Input
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE-HIGH deselects the device and reduces power consumption
to standby levels.
RP
Input
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and
resets internal automation. RP-HIGH enables normal operation. When driven
LOW, RP inhibits write operations which provides data protection during power
transitions. Exit from deep power-down sets the device to read array mode. With
RP = VHH, block erase or word write can operate to all blocks without WP state.
Block erase or word write with VIH < RP < VHH produce spurious results and should
not be attempted.
OE
Input
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE
Input
WRITE ENABLE: Controls writes to the CIU and array blocks. Addresses and data
are latched on the rising edge of the WE pulse.
WP
Input
WRITE PROTECT: Master control for boot blocks locking. When VIL, locked boot
blocks cannot be erased and programmed.
Supply
BLOCK ERASE and WORD WRITE POWER SUPPLY: For erasing array blocks or
writing words. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase
and word write with an invalid VPP (see ‘DC Characteristics’) produce spurious
results and should not be attempted.
VCC
Supply
DEVICE POWER SUPPLY: Do not float any power pins. With VCC ≤ VLKO, all
write attempts to the flash memory are inhibited. Device operations at invalid
VCC voltage (see ‘DC Characteristics’) produce spurious results and should not
be attempted.
GND
Supply
GROUND: Do not float any ground pins.
VPP
8
NAME AND FUNCTION
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
Principles of Operation
The LRS1388A SmartVoltage flash memory
includes an on-chip WSM to manage block erase and
word write functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure,
word write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see ‘Bus Operation’), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the F-V PP voltage.
High voltage on F-VPP enables successful block erasure and word writing. All functions associated with
altering memory contents — block erase, word write,
status, and identifier codes — are accessed via the CUI
and verified through the status register.
Commands are written using standard microprocessor write timings. The CUI contents serve as input to
the WSM, which controls the block erase and word
write. The internal algorithms are regulated by the
WSM including pulse repetition, internal verification,
and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the
identifier codes or outputs status register data.
Interface software that initiates and polls progress of
block erase and word write can be stored in any block.
This code is copied to and executed from system RAM
during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to
suspend a block erase to read/write data from/to blocks
other than that which is suspended. Word write suspend allows system software to suspend a word write to
read data from any other flash memory array location.
DATA PROTECTION
Depending on the application, the system designer
may choose to make the VPP power supply switchable
(available only when memory block erases or word
writes are required) or hardwired to VPPH. The device
accommodates either design practice and encourages
optimization of the processor-memory interface.
Data Sheet
LRS1338A
When V PP ≤ V PPLK, memory contents cannot be
altered. The CUI, with two-step block erase or word
write command sequences, provides protection from
unwanted operations even when high voltage is
applied to VPP. All write functions are disabled when
VCC is below the write lockout voltage VLKO or when
RP is at VIL. The device’s boot blocks locking capability for WP provides additional protection from inadvertent code or data alteration by block erase and
word write operations.
TOP BOOT
7FFFF
7F000
7EFFF
FE000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
4K-WORD BOOT BLOCK
0
4K-WORD BOOT BLOCK
1
4K-WORD PARAMETER BLOCK
0
4K-WORD PARAMETER BLOCK
1
4K-WORD PARAMETER BLOCK
2
4K-WORD PARAMETER BLOCK
3
4K-WORD PARAMETER BLOCK
4
4K-WORD PARAMETER BLOCK
5
32K-WORD MAIN BLOCK
0
32K-WORD MAIN BLOCK
1
32K-WORD MAIN BLOCK
2
32K-WORD MAIN BLOCK
3
32K-WORD MAIN BLOCK
4
32K-WORD MAIN BLOCK
5
32K-WORD MAIN BLOCK
6
32K-WORD MAIN BLOCK
7
32K-WORD MAIN BLOCK
8
32K-WORD MAIN BLOCK
9
32K-WORD MAIN BLOCK
10
32K-WORD MAIN BLOCK
11
32K-WORD MAIN BLOCK
12
32K-WORD MAIN BLOCK
13
32K-WORD MAIN BLOCK
14
LRS1338A-4
Figure 4. Memory Map
9
LRS1338A
Bus Operation
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
READ
Information can be read from any block, identifier
codes or status register independent of the VPP voltage. RP can be either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or Read
Status Register) to the CUI. Upon initial device powerup or after exit from deep power-down mode, the device
automatically resets to read array mode. Five control
pins dictate the data flow in and out of the component:
CE, OE, WE, RP and WP. CE and OE must be driven
active to obtain data at the outputs. CE is the device
selection control, and when active enables the selected
memory device. OE is the data output (I/O0 - I/O15) control and when active drives the selected memory data
onto the I/O bus. WE must be at VIH and RP must be at
VIH or VHH. Figure 12 illustrates a read cycle.
OUTPUT DISABLE
With OE at a logic-HIGH level (VIH), the device outputs are disabled. Output pins (I/O0 - I/O15) are placed
in a HIGH impedance state.
STANDBY
CE at a logic HIGH level (VIH) places the device in
standby mode which substantially reduces device
power consumption. I/O0 - I/O15 outputs are placed in
a HIGH-impedance state independent of OE. If deselected during block erase or word write, the device continues functioning, and consuming active power until
the operation completes.
DEEP POWER-DOWN
RP at VIL initiates the deep power down mode.
In read modes, RP-LOW deselects the memory,
places output drivers in a HIGH-impedance state and
turns off all internal circuits. RP must be held LOW for
a minimum of 100 ns. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase or word write modes, RP-LOW
will abort the operation. Memory contents being altered
are no longer valid; the data may be partially erased or
written. Time tPHWL is required after RP goes to logic
HIGH (VIH) before another command can be written.
10
Stacked Chip (8M Flash & 2M SRAM)
As with any automated device, it is important to
assert RP during system reset. When the system
comes out of reset, it expects to read from flash memory. Automated flash memories provide status information when accessed during block erase or word write
modes. If a CPU reset occurs with no flash memory
reset, proper CPU initialization may not occur because
the flash memory may be providing status information
instead of array data. SHARP’s flash memories allow
proper CPU initialization following a system reset
through the use of RP input. In this application, RP is
controlled by the same RESET signal that resets the
system CPU.
READ IDENTIFIER CODES OPERATION
The read identifier codes operation outputs the manufacturer code and device codes, the system CPU can
automatically match the device with its proper algorithms.
7FFFF
RESERVED FOR
FUTURE IMPLEMENTATION
00001
DEVICE CODE
00000
MANUFACTURER CODE
1338A-5
Figure 5. Device Identifier Code Memory Map
WRITE
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register.
When VCC = VCC1 and VPP = VPPH, the CUI additionally controls block erasure and word write. The
Block Erase command requires appropriate command
data and an address within the block to be erased. The
Word Write command requires the command and
address of the location to be written.
The CUI does not occupy an addressable memory
location. It is written when WE and CE are active. The
address and data needed to execute a command are
latched on the rising edge of WE or CE (whichever
goes HIGH first). Standard microprocessor write timings are used. Figure 13 and 14 illustrate WE and CE
controlled write operations.
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
Device operations are selected by writing specific commands into the CUI. Table 6 defines these commands.
COMMAND DEFINITIONS
When VPP ≤ VPPLK, Read operations from the status
register, identifier codes or blocks are enabled. Placing
VPPH on VPP enables successful block erase and word
write operations.
Table 5. Bus Operations
RP
CE
OE
WE
ADDRESS
VPP
I/O0 - I/O15
NOTES
Read
VIH or VHH
VIL
VIL
VIH
X
X
DOUT
1, 2, 3
Output Disable
VIH or VHH
VIL
VIH
VIH
X
X
HIGH Z
Standby
VIH or VHH
VIH
X
X
X
X
HIGH Z
VIL
X
X
X
X
X
HIGH Z
Read Identifier Codes
VIH or VHH
VIL
VIL
VIH
See Figure 3
X
Write
VIH or VHH
VIL
VIH
VIL
X
X
MODE
Deep Power-Down
4
5
DIN
3, 6, 7
NOTES:
1. Refer to ‘DC Characteristics’. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be V IL or VIH for control pins and addresses, and VPPLK or VPPH for VPP.
See ‘DC Characteristics’ for VPPLK and VPPH voltages.
3. Never hold OE LOW and WE LOW at the same time.
4. RP at GND ± 0.2 V ensures the lowest deep power-down current.
5. See ‘Read Identifier Codes Command’ for read identifier code data.
6. Command writes involving block erase or word write are reliably executed when VPP = VPPH and VCC = VCC1.
Block erase or word write with VIH < RP < VHH produce spurious results and should not be attempted.
7. Refer to Table 6 for valid DIN during a write operations.
Table 6. Command Definitions1
COMMAND
FIRST BUS CYCLE
BUS CYCLES
REQUIRED
OPER.
2
ADDR.
3
SECOND BUS CYCLE
4
DATA
OPER.2
ADDR.3
DATA4
1
Write
X
FFH
Read Identifier Codes
≥2
Write
X
90H
Read
IA
ID
Read Status Register
2
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Read Array/Reset
NOTES
5
Block Erase
2
Write
BA
20H
Write
BA
D0H
6
Word Write
2
Write
WA
40H or 10H
Write
WA
WD
6, 7
Block Erase and Word
Write Suspend
1
Write
X
B0H
6
Block Erase and Word
Write Resume
1
Write
X
D0H
6
NOTES:
1. Commands other than those shown in table are reserved by SHARP for
future device implementations and should not be used.
2. BUS operations are defined in Table 5.
3. X = Any valid address within the device; IA = Identifier Code Address, see Figure 5.
BA = Address within the block being erased; WA = Address of memory location to be written.
4. SRD = Data read from status register. See Table 9 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE or CE (whichever goes HIGH first).
ID = Data read from identifier codes.
5. Following the Read Identifier Codes command, read operations access manufacturer and device codes.
See ‘Read Identifier Codes Command’ for read identifier code data.
6. When WP = VIL, RP must beat VHH to enable block erase or word write operations.
Attempts to issue a block erase or word write to a locked boot block while RP = VIH.
7. Either 40H or 10H are recognized by the WSM as the word write setup.
Data Sheet
11
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
READ ARRAY COMMAND
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by writing
the Read Array command. The device remains
enabled for reads until another command is written.
Once the internal WSM has started a block erase or
word write, the device will not recognize the Read Array
command until the WSM completes its operation
unless the WSM is suspended via an Erase Suspend
or Word Write Suspend command. The Read Array
command functions independently of VPP voltage and
RP can be VIH or VHH.
READ IDENTIFIER CODES COMMAND
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 5 retrieve the manufacturer and device codes (see
Table 7 for identifier code values). To terminate the
operation, write another valid command. Like the Read
Array command, the Read Identifier Codes command
functions independently of the VPP voltage and RP can
be VIH or V HH. Following the Read Identifier Codes
command, the following information can be read.
Table 7. Identifier Codes
CODE
ADDRESS
DATA
Manufacture Code
00000H
00B0H
Device Code (Top Boot)
00001H
0060H
READ STATUS REGISTER COMMAND
The status register may be read to determine when
a block erase or word write is complete and whether
the operation completed successfully. It may be read at
any time by writing the Read Status Register command. After writing this command, all subsequent read
operations output data from the status register until
another valid command is written. The status register
contents are latched on the falling edge of OE or CE,
whichever occurs. OE or CE must toggle to VIH before
further reads to update the status register latch. The
Read Status Register command functions independently of the VPP voltage. RP can be VIH or VHH.
12
CLEAR STATUS REGISTER COMMAND
Status register bits SR.5, SR.4, SR.3 or SR.1 are set
to ‘1’s by the WSM and can only be reset by the Clear
Status Register command. These bits indicate various
failure conditions (see Table x). By allowing system
software to reset these bits, several operations (such
as cumulatively erasing multiple blocks or writing several words in sequence) may be performed. The status
register may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP can be VIH or
V HH. This command is not functional during block
erase or word write suspend modes.
BLOCK ERASE COMMAND
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is first
written, followed by a block erase confirm. This command sequence requires appropriate sequencing and
an address within the block to be erased (erase
changes all block data to FFFFH). Block preconditioning, erase, and verify are handled internally by the
WSM (invisible to the system). After the two-cycle block
erase sequence is written, the device automatically
outputs status register data when read (see Figure 6).
The CPU can detect block erase completion by analyzing the output data of the status register bit SR.7.
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective action. The CUI
remains in read status register mode until a new command is issued.
This two-step command sequence of set-up followed by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to ‘1’. Also, reliable block erasure
can only occur when VCC = VCC1 and VPP = VPPH. In
the absence of this high voltage, block contents are
protected against erasure. If block erase is attempted
while VPP ≤ VPPLK, SR.3 and SR.5 will be set to ‘1’.
Successful block erase for boot blocks requires that if
set WP = VIH or RP = VHH. If block erase is attempted
to boot block when the corresponding WP = V IL or
RP = VIH, SR.1 and SR.5 will be set to ‘1’. Block erase
operations with V IH < RP < V HH produce spurious
results and should not be attempted.
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
Start
Write 20H
Block Address
Write D0H
Block Address
LRS1338A
BUS
OPERATION
COMMAND
Write
Erase Setup
Data = 20H
Addr = Within Block to be Erased
Write
Erase
Confirm
Data = D0H
Addr = Within Block to be Erased
Status Register Data
Read
Read
Status Register
Suspend Block
No
Erase Loop
Suspend
Block
Erase
0
SR.7 =
Yes
COMMENTS
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent block erasures.
Full status check can be done after each block erase
or after a sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
1
Full Status
Check If Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION
VPP
Range Error
COMMAND
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Standby
Check SR.4, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
0
SR.1 =
1
Device
Protect Error
0
SR.4, 5 =
1
Command
Sequence Error
SR.5, SR.4, SR.3, and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
SR.5 =
1
Block
Erase Error
0
Block Erase
Successful
LRS1338A-6
Figure 6. Automated Block Erase Flowchart
Data Sheet
13
LRS1338A
WORD WRITE COMMAND
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or alternate
10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of
WE). The WSM then takes over, controlling the word
write and write verify algorithms internally. After the
word write sequence is written, the device automatically outputs status register data when read (see Figure 7). The CPU can detect the completion of the word
write event by analyzing the status register bit SR.7.
When word write is complete, status register bit
SR.4 should be checked. If word write error is detected,
the status register should be cleared. The internal
WSM verify only detects errors for ‘1’s that do not successfully write to ‘0’s. The CUI remains in read status
register mode until it receives another command.
Reliable word writes can only occur when VCC = VCC1
and VPP and VPPH. In the absence of this high voltage,
memory contents are protected against word writes. If
word write is attempted while VPP ≤ VPPLK, status register bits SR.3 and SR.4 will be set to ‘1’.
Successful word write for boot blocks requires that if
set, that WP = V IH or RP = V HH . If word write is
attempted to boot block when the corresponding WP =
VIL or RP = VIH, SR.1 and SR.4 will be set to ‘1’. Word
write operations with VIH < RP < VHH produce spurious
results and should not be attempted.
14
Stacked Chip (8M Flash & 2M SRAM)
BLOCK ERASE SUSPEND COMMAND
The Block Erase Suspend command allows blockerase interruption to read or word-write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests
that the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs status register data when read after the Block
Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be set
to ‘1’). Specification tWHRH2 defines the block erase
suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is suspended. A Word Write command sequence can also be
issued during erase suspend to program data in other
blocks. using the Word Write Suspend command (see
‘Word Write Suspend Command’ section), a word write
operation can also be suspended. During a word write
operation with block erase suspended, status register
bit SR.7 will return to ‘0’. However, SR.6 will remain ‘1’
to indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is
written to the flash memory, the WSM will continue the
block erase process. Status register bits SR.6 and
SR.7 will automatically clear. After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 8). VPP
must remain at V PPH (the same V PP level used for
block erase) while block erase is suspended. RP must
also remain at VIH or VHH (the same RP level used for
block erase). WP must also remain at VIL or VIH (the
same WP level used for block erase). Block erase cannot resume until word write operations initiated during
block erase suspend have completed.
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
Start
Write 40H or 10L
Address
Write Word
Data and Address
LRS1338A
BUS
OPERATION
COMMAND
Write
Setup
Word Write
Data = 40H or 10H
Addr = Location to be Written
Write
Word
Write
Data = Data to be Written
Addr = Location to be Written
Status Register Data
Read
Read
Status Register
Suspend Word
Write Loop
No
SR.7 =
0
Suspend
Word
Write
Yes
COMMENTS
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Repeat for subsequent byte writes.
SR full status check can be done after each byte write
or after a sequence of byte writes.
Write FFH after the last byte write operation to place
device in read array mode.
1
Full Status
Check If Desired
Word Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
SR.3 =
1
BUS
OPERATION
VPP
Range Error
COMMAND
COMMENTS
Standby
Check SR.3
1 = VPP Error Detect
Standby
Check SR.1
1 = Device Protect Detect
Standby
Check SR.4
1 = Data Write Error
0
SR.1 =
1
Device
Protect Error
0
SR.4, SR.3, and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple locations are written
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
SR.4 =
1
Word Write
Error
0
Word Write
Successful
LRS1338A-7
Figure 7. Automated Word Write Flowchart
Data Sheet
15
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
Start
BUS
OPERATION
COMMAND
Write B0H
Write
Erase
Suspend
Read
Status Register
Read
SR.7 =
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
1
Write
SR.6 =
Block
Erase Completed
Data = B0H
Addr = X
Status Register Data
Addr = X
0
0
COMMENTS
Erase
Resume
Data = D0H
Addr = X
1
Read
Read
Array Data
Read or
Word
Write?
No
Word Write
Word
Write Loop
Done?
Yes
Write D0H
Write FFH
Block Erase
Resumed
Read Array Data
LRS1338A-8
Figure 8. Block Erase Suspend/Resume Flowchart
16
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
WORD WRITE SUSPEND COMMAND
The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts, writing the
Word Write Suspend command requests that the WSM
suspend the word write sequence at a predetermined
point in the algorithm. The device continues to output
status register data when read after the Word Write Suspend command is written. Polling status register bits
SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to ‘1’). Specification tWHRH1 defines the word write suspend latency.
LRS1338A
At this point a Read Array command can be written
to read data from locations other than that which is suspended. The only other valid commands while word
write is suspended are Read Status Register and Word
Write Resume. After Word Write Resume command is
written to the flash memory, the WSM will continue the
word write process. Status register bits SR.2 and SR.7
will automatically clear. After the Word Write Resume
command is written, the device automatically outputs
status register data when read (see Figure 9). VPP
must remain at VPPH (the same VPP level used for word
write) while in word write suspend mode. RP must also
remain at VIH or VHH (the same RP level used for word
write). WP must also remain VIL or VIH (the same WP
level used for word write).
Start
BUS
OPERATION
COMMAND
Write B0H
Write
Word Write
Suspend
Read
Status Register
Read
SR.7 =
Standby
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
Check SR.2
1 = Word Write Suspended
0 = Word Write Completed
0
Write
0
Data = B0H
Addr = X
Status Register Data
Addr = X
1
SR.2 =
COMMENTS
Word
Write Completed
Read
Array
Data = FFH
Addr = X
Read Array locations other
than that being written
Read
1
Write
Write FFH
Word Write
Resume
Data = D0H
Addr = X
Read Array Data
Done
No
Reading?
Yes
Write D0H
Write FFH
Word Write
Resumed
Read Array Data
LRS1338A-9
Figure 9. Word Write Suspend/Resume Flowchart
Data Sheet
17
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
Table 8. Write Protection Alternatives
OPERATION
Word Write or
Block Erase
VPP
RP
WP
VIL
X
X
All blocks locked
VIL
X
All blocks locked
VHH
X
All blocks unlocked
> VPPLK
VIH
EFFECT
VIL
Two boot blocks locked
VIH
All blocks unlocked
Table 9. Status Register Definition
WSMS
ESS
ES
WWS
VPPS
WWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = Write State Machine Status (WSMS)
1 = Ready
0 = Busy
SR.6 = Erase Suspend Status (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = Erase(s)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = Word Write (WWS)
1 = Error in Word Write
0 = Successful Word Write
NOTES:
1. Check SR.7 to determine block erase or word write completion.
SR.6 - SR.0 are invalid while SR.7 = 0.
2. If both SR.5 and SR.4 are ‘1’s after a block erase attempt, an
improper command sequence was entered.
3. SR.3 does not provide a continuous indication of VPP level. The
WSM interrogates and indicates the VPP level only after Block
Erase or Word Write command sequences. SR.3 is not guaranteed to report accurate feedback only when VPP ≠ VPPH.
4. The WSM interrogates the WP and RP only after Block Erase or
Word Write command sequences. It informs the system, depending
on the attempted operation, if the WP is not VIH or RP is not VHH.
5. SR.0 is reserved for future use and should be masked out when
polling the status register.
SR.3 = VPP Status (VPPS)
1 = VPP LOW Detect, Operation Abort
0 = VPP Okay
SR.2 = Word Write Suspend Status (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = Device Protect Status (DPS)
1 = WP and/or RP Lock Detected, Operation Abort
0 = Unlock
SR.0 = Reserved for future enhancements (R)
18
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
Design Considerations
THREE-LINE OUTPUT CONTROL
The device will often be used in large memory
arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for:
• Lowest possible memory power dissipation.
• Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE while OE should be connected to all memory devices and the system’s READ
control line. This assures that only selected memory
devices have active outputs while deselected memory
devices are in standby mode. RP should be connected
to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
POWER SUPPLY DECOUPLING
Flash memory power switching characteristics
require careful device decoupling. System designers
are interested in three supply current issues: standby
current levels, active current levels and transient peaks
produced by falling and rising edges of CE and OE.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device should
have a 0.1 µF ceramic capacitor connected between its
VCC and GND and between its VPP and GND. These
high-frequency, low inductance capacitors should be
placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply
connection between VCC and GND. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductance.
VPP TRACE ON PRINTED CIRCUIT BOARDS
Updating flash memories that reside in the target
system requires that the printed circuit board designer
pay attention to the VPP power supply trace. The VPP
pin supplies the memory cell current for word writing
and block erasing. Use similar trace widths and layout
considerations given to the VCC power bus. Adequate
VPP supply traces and decoupling will decrease VPP
voltage spikes and overshoots.
VCC, VPP RP TRANSITIONS
Block erase and word write are not guaranteed if
VPP falls outside of a valid VPPH range, VCC falls outside of a valid VCC1 range, or RP ≠ VIH or VHH. If VPP
error is detected, status register bit SR.3 is set to ‘1’
Data Sheet
LRS1338A
along with SR.4 or SR.5, depending on the attempted
operation. If RP transitions to VIL during block erase or
word write, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP transitions to VIL clear
the status register.
The CIU latches commands issued by system software and is not altered by V PP or CE transitions or
WSM actions. Its state is read array mode upon powerup, after exit from deep power-down or after VCC transitions below VLKO.
After block erase or word write, even after VPP tarnation down to VPPLK, the CUI must be placed in read
array mode via the Read Array command if subsequent
access to the memory array is desired.
POWER-UP/DOWN PROTECTION
The device is designed to offer protection against
accidental block erasure or word writing during power
transitions. Upon power-up, the device is indifferent as
to which power supply (VPP or VCC) powers-up first.
Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is active.
Since both WE and CE must be LOW for a command
write, driving either to VHH will inhibit writes. The CUI’s
two-step command sequence architecture provides
added level of protection against data alteration.
WP provide additional protection from inadvertent
code or data alteration.
The device is disabled while RP = VIL regardless of
its control inputs state.
POWER DISSIPATION
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during system idle time. Flash memory’s non-volatility increases
usable battery life because data is retained when system power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can consume negligible power by lowering RP to VIL standby or
sleep modes. If access is again needed, the devices
can be read following the tPHQV and tPHWL wake-up
cycles required after RP is first raised to VIH. See ‘AC
Characteristics — Read Only and Write Operations’
and Figure 12, 13 and 14 for more information.
19
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
Electrical Specifications
AC Test Conditions
RATINGS*
ABSOLUTE MAXIMUM
• Commercial Operating Temperature
– During Read, Block Erase and Word Write:
-40°C to +85°C (Note 1)
– Temperature under Bias: -40°C to +85°C (Note 1)
• Storage Temperature: -65°C to +125°C
• Voltage on any pin except VCC, VPP and RP:
-2.0 V to +7.0 V (Note 2)
• VCC Supply Voltage: -2.0 V to +7.0 V (Note 2)
2.7
INPUT 1.35
0.0
1.35 OUTPUT
TEST POINTS
NOTE: AC test inputs are driven at 2.7 V for a Logic '1' and 0.0 V
for a Logic '0'. Input timing begins and output timing ends
at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns.
LRS1338A-10
Figure 10. Transient Input/Output Reference
Waveform for VCC = 2.7 V to 3.6 V
• VPP Update Voltage during Block Erase and Word
Write: -2.0 V to +14.0 V (Note 2 and 3)
1.3 V
• RP Voltage: -2.0 V to +14.0 V (Note 2 and 3)
• Output Short Circuit Current: 100 mA (Note 4)
1N914
WARNING: *Stressing the device beyond the ‘Absolute Maximum
Ratings’ may cause permanent damage. These are stress ratings
only. Operation beyond the ‘Operating Conditions’ is not recommended and extended exposure beyond the ‘Operating Conditions’
may affect device reliability.
NOTES:
1. Operating temperature is for commercial product defined by this
specification.
2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins.
During transitions, this level may undershoot to -2.0 V for periods
< 20 ns. Maximum DC voltage on input/output pins and VCC is VCC
+ 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for
periods < 20 ns.
3. Maximum DC voltage on VPP and RP may overshoot to +14.0 V
for periods <20 ns.
4. Output shorted for no more than one second. No more than one
output shorted at a time.
20
RL = 3.3 kΩ
DEVICE
UNDER
TEST
OUT
CL
NOTE: CL Includes Jig Capacitance
LRS1338A-11
Figure 11. Transient Equivalent
Testing Load Circuit
Table 10. Test Configuration
Capacitance Loading Value
TEST CONFIGURATION
CL (pF)
VCC = 2.7 V to 3.6 V
50
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
FLASH DC CHARACTERISTICS
SYMBOL
PARAMETER
VCC = 2.7 V to 3.6 V
MIN.
MAX.
TEST
CONDITIONS
UNIT
NOTES
ILI
Input Load Current
±0.5
µA
VCC = VCC MAX., VIN = VCC or GND
1
ILO
Output Leakage Current
±0.5
µA
VCC = VCC MAX., VOUT = VCC or GND
1
25
50
µA
CMOS Inputs, VCC = VCC MAX.,
CE = RP = VCC ± 0.2 V
1, 2
0.2
2
mA
TTL Inputs, VCC = VCC MAX.,
CE = RP = VIH
1, 2
4
20
µA
RP = GND ± 0.2 V
25
mA
CMOS Inputs, VCC = VCC MAX.,
CE = GND, f = 5 MHz, IOUT = 0 mA
1, 2, 3
30
mA
TTL Inputs, VCC = VCC MAX.,
CE = GND, f = 5 MHz, IOUT = 0 mA
1, 2, 3
ICCS
ICCD
VCC Standby Current
VCC Deep Power-Down Current
15
ICCR
VCC Read Current
1
ICCW
VCC Word Write Current
5
17
mA
VPP = VPPH
1, 4
ICCE
VCC Block Erase Current
4
17
mA
VPP = VPPH
1, 4
ICCWS
ICCES
VCC Word Write or Block
Erase Suspend Current
1
6
mA
CE = VIH
1, 5
±2
±15
µA
VPP ≤ VCC
1
10
20.0
µA
VPP > VCC
1
5
µA
RP = GND ± 0.2 V
1
IPPS
IPPR
VPP Standby or Read Current
IPPD
VPP Deep Power-Down Current
0.1
IPPW
VPP Word Write Current
12
40
mA
VPP = VPPH
1, 4
IPPE
VPP Block Erase Current
8
25
mA
VPP = VPPH
1, 4
VPP Word Write or Block Erase
Suspend Current
10
200
µA
VPP = VPPH
1
IPPWS
IPPES
VIL
Input LOW Voltage
-0.5
0.8
V
4
VIH
Input HIGH Voltage
2.0
VCC + 0.5
V
4
VOL
Output LOW Voltage
0.4
V
VCC = VCC MIN., IOL = 2.0 mA
4
VOH1
Output HIGH Voltage (TTL)
2.4
V
VCC = VCC MIN., IOH = 1.0 mA
4
VOH2
Output HIGH Voltage (CMOS)
0.85 VCC
V
VCC = VCC MIN., IOH = 2.5 mA
4
VCC -0.4
V
VCC = VCC MIN., IOH = -100 µA
4
VPPLK
VPP Lockout during
Normal Operations
VPPH
VPP during Word Write or Block
Erase Operations
2.7
VLKO
VCC Lockout Voltage
2.0
VHH
RP Unlock Voltage
11.4
NOTES:
1. All currents are in RMS unless otherwise noted.
2. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs
are either VIL or VIH.
3. Automatic Power Savings (APS) reduces typical ICCR to 3 mA at
3.3 V VCC in static operation.
4. Sampled, not 100% tested.
5. ICCWS and ICCES are specified with the device de-selected. If read
or word written while in erase suspend mode, the device’s current
draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
Data Sheet
1.5
V
3.6
V
4, 6
V
12.6
V
Unable WP
7, 8
6. Block erases and word writes are inhibited when VPP ≤ V PPLK,
and not guaranteed in the range between V PPLK (MAX.) and
VPPH (MIN.).
7. Block erases and word writes are inhibited when the corresponding RP = VIH or WP = VIL. Block erase and word write operations
are not guaranteed with V CC < 3.0 V or V IH < RP < V HH and
should not be attempted.
8. RP connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
21
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
FLASH AC CHARACTERISTICS — READ ONLY OPERATIONS1
VCC = 2.7 V to 3.6 V, TA = 40°C to +85°C
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
NOTES
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
120
ns
tELQV
CE to Output Delay
120
ns
tPHQV
RP HIGH to Output Delay
600
ns
tGLQV
OE to Output Delay
50
ns
2
tELQX
CE to Output in LOW Z
ns
3
tEHQZ
CE HIGH to Output in HIGH Z
ns
3
tGLQX
OE to Output in LOW Z
ns
3
tGHQZ
OE HIGH to Output in HIGH Z
ns
3
ns
3
tOH
120
ns
0
55
0
20
Output Hold from Address, CE or OE Change,
Whichever Occurs First
0
2
NOTES:
1. See ‘AC Input/Output Reference Waveform’ section for maximum allowable input slew rate.
2. OE may be delayed up to tELQV - tGLQV after the falling edge of CE without impact on tELQV.
3. Sampled, not 100% tested.
STANDBY
DEVICE
ADDRESS SELECTION
DATA VALID
VIH
ADDRESS STABLE
ADDRESSES (A)
VIL
tAVAV
VIH
CE (E)
VIL
tEHQZ
tAVEL
VIH
OE (G)
VIL
tGHQZ
VIH
WE (W)
tGLQV
VIL
tELQV
tGLQX
tOH
tELQX
VOH
DATA (D/Q)
(I/O0 - I/O15) VOL
HIGH Z
VALID OUTPUT
HIGH Z
tAVQV
VCC
tPHQV
VIH
RP (P)
VIL
LRS1338A-12
Figure 12. AC Waveforms for Read Operations
22
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
FLASH AC CHARACTERISTICS — WRITE OPERATIONS1
VCC = 2.7 V to 3.6 V, TA = -40°C to +85°C
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHWL
MIN.
MAX.
UNIT
120
ns
RP HIGH Recovery to WE Going LOW
1
µs
tELWL
CE Setup to WE Going LOW
10
ns
NOTES
2
tWLWH
WE Pulse Width
50
ns
tPHHWH
RP VHH to WE Going HIGH
100
ns
2
tSHWH
WP VIH Setup to WE Going HIGH
100
ns
2
tVPWH
VPP Setup to WE Going HIGH
100
ns
2
tAVWH
Address Setup to WE Going HIGH
50
ns
3
tDVWH
Data Setup to WE Going HIGH
50
ns
3
tWHDX
Data Hold from WE HIGH
5
ns
tWHAX
Address Hold from WE HIGH
5
ns
tWHEH
CE Hold from WE HIGH
10
ns
tWHWL
WE Pulse Width HIGH
30
ns
tWHGL
Write Recovery before Read
0
ns
tQVVL
VPP Hold from Valid SRD HIGH
0
ns
tQVPH
RP VHH Hold from Valid SRD HIGH
0
ns
2, 4
tQVSL
WP VIH Hold from Valid SRD HIGH
0
ns
2, 4
2, 4
NOTES:
1. Read timing characteristics during block erase and word write operations are the
same as during read-only operations. Refer to ‘AC Characteristics’ section for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 6 for valid AIN and DIN for block erase or word write.
4. VPP should be held at VPPH (and if necessary RP should be held at VHH) until
determination of block erase or word write success (SR.1, SR.3, SR.4, SR.5 = 0).
Data Sheet
23
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
1
ADDRESSES (A)
VIH
2
3
4
AIN
AIN
5
6
VIL
tAVAV
tAVWH
tWHAX
CE (E)
VIH
VIL
tELWL
tWHEH
tWHGL
VIH
OE (G)
VIL
tWHWL
tWHOV1, 2, 3, 4
VIH
WE (W)
VIL
tWLWH
tDVWH
tWHDX
DATA (I/O)
VIH HIGH Z
DIN
VALID
SRD
DIN
DIN
VIL
tPHWL
tSHWH
tQVSL
tPHHWH
tQVPH
tVPWH
tQVVL
VIH
WP (S)
VIL
VHH
VIH
RP (P)
VIL
VPPH
VPP (V)
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
LRS1338A-13
Figure 13. AC Waveform for WE Controlled Write Operations
24
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
ALTERNATIVE CE CONTROLLED WRITES1
VCC = 2.7 V to 3.6 V, TA = 40°C to +85°C
SYMBOL
PARAMETER
tAVAV
Write Cycle Time
tPHEL
MIN.
MAX.
UNIT
120
ns
RP HIGH Recovery to CE Going LOW
1
µs
tWLEL
WE Setup to CE Going LOW
0
ns
tELEH
NOTES
2
CE Pulse Width
70
ns
tPHHEH
RP VHH Setup to CE Going HIGH
100
ns
2
tSHEH
WP VIH Setup to CE Going HIGH
100
ns
2
tVPEH
VPP Setup to CE Going HIGH
100
ns
2
tAVEH
Address Setup to CE Going HIGH
50
ns
3
tDVEH
Data Setup to CE Going HIGH
50
ns
3
tEHDX
Data Hold from CE HIGH
5
ns
tEHAX
Address Hold from CE HIGH
5
ns
tEHWH
WE Hold from CE HIGH
0
ns
tEHEL
CE Pulse Width HIGH
25
ns
tEHGL
Write Recovery before Read
0
ns
tQVVL
VPP Hold from Valid SRD HIGH
0
ns
tQVPH
RP VHH Hold from Valid SRD HIGH
0
ns
2, 4
tQVSL
WP VIH Hold from Valid SRD HIGH
0
ns
2, 4
2, 4
NOTES:
1. In systems where CE defines the write pulse width (within a longer WE timing waveform),
all setup, hold, and inactive WE times should be measured relative to the CE waveform.
2. Sampled, not 100% tested.
3. Refer to Table 6 for valid AIN and DIN for block erase or word write.
4. VPP should be held at VPPH (and if necessary RP should be held at VHH) until
determination of block erase or word write success (SR.1, SR.3, SR.4, SR.5 = 0).
Data Sheet
25
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
1
ADDRESSES (A)
VIH
2
3
4
AIN
AIN
5
6
VIL
tAVAV
tAVEH
tEHAX
WE (W)
VIH
VIL
tWLEL
tEHWH
tEHGL
VIH
OE (G)
VIL
tEHEL
tEHQV1, 2, 3, 4
VIH
CE (E)
VIL
tELEH
tDVEH
tEHDX
DATA (D/Q)
VIH HIGH Z
DIN
VALID
SRD
DIN
DIN
VIL
tPHEL
tEHEH
tQVSL
tPHHEH
tQVPH
VIH
WP (S)
VIL
VHH
VIH
RP (P)
VIL
tVPEH
tQVVL
VPPH
VPP (V)
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
LRS1338A-14
Figure 14. Alternate AC Waveform for CE Controlled Write Operations
26
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
RESET OPERATIONS
VIH
RP (P)
VIL
tPLPH
A. Reset during Block Erase or Word Write or Read Array Mode
2.7 V - 3.6 V
VCC
VIL
tVPH
VIH
RP (P)
VIL
B. RP rising Timing
LRS1338A-15
Figure 15. AC Waveform for Reset Operation
Table 11. Reset AC Specifications
SYMBOL
VCC = 2.7 V to 3.6 V
PARAMETER
MIN.
MAX.
UNIT
NOTES
tPLPH
RP Pulse LOW Time (if RP is tied to VCC,
this specification is not applicable)
100
ns
1
tVPH
VCC 2.7 V to RP HIGH
100
ns
2
NOTES:
1. If RP is asserted while a block erase or word write operation is not executing,
the reset will complete within 100 ns.
2. When the device power-up holding RP LOW minimum 100 ns is required
after VCC has been in predefined range and also has been stable there.
BLOCK ERASE AND WORD WRITE PERFORMANCE1
VCC = 2.7 V to 3.6 V, TA = 40°C to +85°C
SYMBOL
tWHQV1
tEHQV1
tWHQV2
tEHQV2
PARAMETER
VPP = 2.7 V to 3.6 V
MIN.
MAX.
TYP.2
UNIT
NOTES
Word Write Time 32K-word Block
44.6
µs
3
Word Write Time 4K-word Block
45.9
µs
3
Block Write Time 32K-word Block
1.46
sec
3
Block Write Time 4K-word Block
0.19
sec
3
Block Erase Time 32K-word Block
1.14
sec
3
Block Erase Time 4K-word Block
0.38
sec
3
tWHRH1, tEHRH1
Word Write Suspend Latency Time to Read
7
8
µs
tWHRH2, tEHRH2
Erase Suspend Latency Time to Read
18
22
µs
NOTES:
1. Sampled, but not 100% tested.
2. Typical values measured at TA = +25°C and nominal voltages.
Subject to change based on device characterization.
3. Excludes system-level overhead.
Data Sheet
27
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
• Standby Current: 40 µA (MAX.)
SRAM*
Description
The LRS1388A is a 2M bit static RAM organized as
262,144 × 8 bit which provides low-power standby
mode.
• Data Retention Current: 0.6 µA (TYP. VCCDR = 3 V,
TA = 25°C)
• Single Power Supply: 2.7 V to 3.6 V
• Operating Temperature: -40°C to +85°C
• Fully Static Operation
Features
• Three-state Output
• Access Time: 85 ns (MAX.)
• Not Designed or Rated as Radiation Hardened
• Operating Current:
– 40 mA (MAX.)
– 25 mA (MAX.)
• P-Type Bulk Silicon
NOTE: *In the SRAM section all reference to pins, commands, voltage, etc. refer only to the SRAM portion of this chip.
Table 12. Truth Table
CE
WE
OE
MODE
I/O0 - I/O7
SUPPLY CURRENT
H
X
X
Standby
HIGH Impedance
Standby (ISB)
L
L
X
Write
Data Input
Active (ICC)
L
H
L
Read
Data Output
Active (ICC)
L
H
H
Output Disable HIGH Impedance
Active (ICC)
NOTE: X = Don’t care, L= LOW, H = HIGH.
28
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
A0
A1
A2
10
A3
ROW
DECODER
1024
MEMORY CELL ARRAY
(1024 x 256 x 8)
VCC
GND
A4
A5
A6
A7
A8
A9
256 x 8
ADDRESS
BUFFER
A10
A11
A12
8
A13
COLUMN
DECODER
COLUMN
GATE
256
A14
A15
A16
A17
8
CE
WE
OE
CE
CONTROL
LOGIC
OE, WE
CONTROL
LOGIC
I/O BUFFER
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
LRS1338A-16
Figure 16. SRAM Block Diagram
Data Sheet
29
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
SRAM Absolute Maximum Ratings
PARAMETER
SYMBOL
RATINGS
UNIT
NOTES
Supply voltage
VCC
-0.2 to +4.6
V
1
Input voltage
VIN
-0.3 to VCC +0.3
V
1, 2
Operating temperature
TOPR
-40 to +85
°C
Storage temperature
TSTG
-65 to +125
°C
NOTES:
1. The maximum applicable voltage on any pins with respect to GND.
2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
SRAM Recommended DC Operating Conditions
TA = -40°C to +85°C
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
VCC
2.7
3.0
3.6
V
VIH
2.0
VCC + 0.3
V
VIL
-0.3
0.8
V
Input voltage
NOTE
1
NOTES:
1. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
SRAM DC Electrical Characteristics
TA = -40°C to + 85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
CONDITION
MIN.
TYP.*
MAX.
UNIT
Input leakage current
ILI
VIN = 0V to VCC
-1.0
1.0
µA
Output leakage current
ILO
CE = VIH or OE = VIH or WE = VIL, VI/O = 0 V to VCC
-1.0
1.0
µA
Operating supply
current
ICC1
CE = VIL, VIN = VIL or VIH
tCYCLE = MIN., II/O = 0 mA
40
mA
ICC2
CE ≤ 0.2 V, VIN ≥ VCC – 0.2 V or ≤ 0.2 V
tCYCLE = 200 ns, II/O = 0 mA
25
mA
ISB
CE ≥ VCC – 0.2 V
40
µA
ISB1
CE = VIH
3.0
mA
VOL
IOL = 2.0 mA
VOH
IOH = -1.0 mA
Standby current
Output voltage
0.6
0.4
2.4
V
V
NOTES: *Reference value at TA = 25°C, VCC = 3.0 V.
SRAM AC Electrical Characteristics
AC TEST CONDITIONS
PARAMETER
Input pulse level
RATINGS
0.6 V to 2.2 V
Input rise and fall time
5 ns
Input and output timing
reference level
1.5 V
Output load*
1 TTL + CL (30 pF)
NOTE: *Including scope and jig capacitance.
30
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
READ CYCLE
TA = -40°C to + 85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read cycle time
tRC
85
Address access time
tAA
85
ns
CE access time
tACE
85
ns
Output enable to output valid
tOE
45
ns
Output hold from address change
tOH
10
ns
CE LOW to output active*
tLZ
10
ns
OE LOW to output active*
tOLZ
5
ns
CE HIGH to output in HIGH impedance*
tHZ
0
30
ns
OE HIGH to output in HIGH impedance*
tOHZ
0
30
ns
SYMBOL
MIN.
MAX.
UNIT
Write cycle time
tWC
85
ns
Chip enable to end of write
tCW
75
ns
Address valid to end of write
tAW
75
ns
Address setup time
tAS
0
ns
Write pulse width
tWP
65
ns
Write recovery time
tWR
0
ns
Input data setup time
tDW
35
ns
Input data hold time
tDH
0
ns
WE HIGH to output active*
tOW
5
ns
WE LOW to output in HIGH impedance*
tWZ
0
30
ns
OE HIGH to output in HIGH impedance*
tOHZ
0
30
ns
ns
NOTE: *Active output to HIGH impedance to output active tests specified for
a ±200 mV transition from steady state levels into the test load.
WRITE CYCLE
TA = -40°C to + 85°C, VCC = 2.7 V to 3.6 V
PARAMETER
NOTE: *Active output to HIGH impedance to output active tests specified for
a ±200 mV transition from steady state levels into the test load.
DATA RETENTION CHARACTERISTICS
TA = -40°C to + 85°C
PARAMETER
SYMBOL
Data retention supply voltage
VCCDR
CE ≥ VCCDR - 0.2 V
ICCDR
VCCDR = 3 V,
CE ≥ VCCDR – 0.2 V, TA = 25°C
Data retention supply voltage
CONDITIONS
MIN.
TYP.
2
0.6
VCCDR = 3 V, CE ≥ VCCDR – 0.2 V
MAX.
UNIT
3.6
V
1.0
µA
35
µA
Chip enable setup time
tCDR
0
ns
Chip enable hold time
tR
5
ms
Data Sheet
31
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
Timing Diagrams
tRC
ADDRESS
tAA
tACE
CE
tLZ
tHZ
tOE
OE
tOLZ
DOUT
tOHZ
Data Valid
tOH
NOTE: WE is HIGH for Read Cycle.
1338A-17
Figure 17. Read Cycle Timing Diagram
32
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
tWC
ADDRESS
OE
tAW
tWR
(NOTE 4)
tCWP
(NOTE 2)
CE
tWP
tAS
(NOTE 3)
(NOTE 1)
tWR
(NOTE 4)
WE
tOHZ
(NOTE 6)
DOUT
tDW
tDH
(NOTE 5)
DIN
Data Valid
NOTES:
1. A write occurs during the overlap of a LOW CE and a LOW WE.
A write begins at the latest transition among CE going LOW and WE going LOW.
A write ends at the earliest transition among CE going HIGH and WE going HIGH.
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of CE going LOW to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applies
in case a write ends at CE or WE going HIGH.
5. During this period, I/O pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
6. If CE goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in HIGH impedance state.
7. If CE goes HIGH simultaneously with WE going HIGH or before WE going HIGH,
the outputs remain in HIGH impedance state.
1338A-18
Figure 18. Write Cycle Timing Diagram (OE Controlled)
Data Sheet
33
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
tWC
ADDRESS
tAW
tWR
(NOTE 3)
tCW
CE
tAS
tWP
tWR
(NOTE 2)
(NOTE 1)
(NOTE 3)
WE
tWZ
tOW
(NOTE 6)
(NOTE 5)
DOUT
tDW
tDH
(NOTE 4)
DATA VALID
DIN
NOTES:
1. tCW is measured from the later of CE going LOW to the end of write.
2. tAS is measured from the address valid to the beginning of write.
3. tWR is measured from the end of write to the address change. tWR applies
in case a write ends at CE or WE going HIGH.
4. During this period, I/O pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
5. If CE goes LOW simultaneously with WE going LOW or after WE going LOW,
the outputs remain in HIGH impedance state.
6. If CE goes HIGH simultaneously with WE going HIGH or before WE going HIGH,
the outputs remain in HIGH impedance state.
1338A-19
Figure 19. Write Cycle Timing Diagram (OE LOW Fixed)
Data Retention Mode
VCC
2.7 V
tCDR
tR
2.0 V
VCCDR
CE ≥ VCCDR - 0.2 V
CE
0V
1338A-20
Figure 20. Data Retention Timing Diagram
34
Data Sheet
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
OUTLINE DIMENSIONS
48TSOP (TSOP48-P-1014)
48
24
25
1.20 MAX
0.995 ± 0.1
0.435
12.4 ±0.2
0.125
0.125 ±0.05
14.0 ±0.3
0.115 ± 0.1
0.4 TYP.
0.1
10.0 ±0.2
0.15 ±0.08
1
13.0 ±0.3
NOTE: Dimensions are in mm.
Data Sheet
48TSOP2
35
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where
component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
LIMITED WARRANTY
SHARP warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a
period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or
replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to
SHARP in writing) or, (ii) if SHARP is unable to repair or replace, refund the purchase price of the Product upon its return to SHARP. This
warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or
modified in design or construction, or which has been serviced or repaired by anyone other than Sharp. The warranties set forth herein are in
lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY
EXCLUDED. In no event will Sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage.
The above warranty is also extended to Customers of Sharp authorized distributors with the following exception: reports of failures of Products
during the warranty period and return of Products that were purchased from an authorized distributor must be made through the distributor.
In case Sharp is unable to repair or replace such Products, refunds will be issued to the distributor in the amount of distributor cost.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics
of the Americas
5700 NW Pacific Rim Blvd., M/S 20
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Telex: 49608472 (SHARPCAM)
Facsimile: (360) 834-8903
http://www.sharpsma.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Facsimile: (49) 40 2376-2232
http://www.sharpmed.com
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: (07436) 5-1321
Telex: LABOMETA-B J63428
Facsimile: (07436) 5-1532
©1999 by SHARP Corporation
Reference Code SMA99088