Ordering number : EN5973 LA6543 Monolithic Linear IC LA6543 4-Channel Bridge (BTL) Driver for CD-ROM Overview Package Dimensions The LA6543 is a 4-channel bridge (BTL) driver developed for CD-ROM applications. unit: mm 3219-QFP34HC [LA6543] Features and Functions 13.2 10.0 1.6 1.6 • Integrated 4-channel power amplifier with bridge circuit (BTL) (two output stage power supply lines) • IOmax: 1A • Integrated level shift circuit • Integrated muting circuit MUTE: Output OFF at Low, output ON at High. MUTE1 is for channels 1 and 2, and MUTE2 for channels 3 and 4. • Integrated thermal shutdown circuit • Divided output stage power supply (VS1: CH1, CH2, CH3; VS2: CH4) 1.0 23 4.8 1.0 0.8 0.2 18 24 11.6 0.35 8.4 13.2 10.0 0.8 17 7 34 6 0.8 1 2.45max 2.2 0.1 4.0 SANYO : QFP34HC Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage 1 VCCmax 14 V Maximum supply voltage 2 VSmax VS1, 2 14 V Maximum input voltage VINmax Input pins V IN1 to 4 13 V Mute pin voltage Allowable power dissipation VMUTEmax Pd max IC only 13 V 0.77 W Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Recommended operation voltage 1 VCC 4 to 13 V Recommended operation voltage 2-1 VS1 VS1: CH1 to CH3 4 to 13 V Recommended operation voltage 2-2 VS 2 VS2: CH4 output reference power supply 4 to 13 V * V CC ≥ VS1, 2 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N1798RM(KI) No. 5973-1/7 LA6543 Electrical Characteristics at VCC = 12V, VS1 = 5V, VS2 = 12V, Ta = 25˚C Parameter Symbol Ratings Conditions min VCC no-load current drain ICC1 All outputs ON (MUTE1, MUTE2: High) ICC2 IS1-1 All outputs OFF (MUTE1, MUTE2: Low) VS1 no-load current drain IS1-2 CH1 OFF (MUTE1, MUTE2: Low) VS2 no-load current drain IS2-1 CH2 to CH4 ON (MUTE1, MUTE2: High) IS2-2 CH2 to CH4 OFF (MUTE1, MUTE2: Low) 5 CH1 ON (MUTE1, MUTE2: High) V OFF1 to4 Potential difference between plus and minus outputs for CH1 to CH4 Output offset voltage VIN Input voltage range Input voltage range forV IN1 to VIN4 10 20 mA 5 10 mA 20 40 mA 4 mA 5 10 mA 4 mA 50 mV –50 4.4 Unit max 0.5 VO source Plus and minus outputs at high level Output voltage (source) typ 5 4.7 V V IO = 700 mA VO sink (sink) Plus and minus outputs at low level 0.3 0.6 V IO = 700 mA Closed circuit voltage gain1 VG1 Voltage gain between CH1 to CH3 BTL amplifiers Closed circuit voltage gain2 VG2 Voltage gain between CH4 BTL amplifiers Slew rate SR 7 dB 14 dB (Note 1) 0.5 Mute ON voltage V MUTE MUTE1, MUTE2 voltage when output is ON (Note 2) 1.5 2 V/µs Mute ON current IMUTE MUTE1, MUTE2 voltage when output is ON (Note 2) 6 10 V µA Allowable power dissipation, Pd max – W Note 1: Guaranteed design value Note 2: MUTE turns amplifier output ON at High and OFF at Low. (At Low, output impedance becomes high.) MUTE1 and MUTE2 operate independently on the respective channels. Pd max – Ta 1.0 0.8 IC Only 0.77 0.6 0.46 0.4 0.2 0 –20 0 20 40 60 80 100 Ambient temperature, Ta – ˚C No. 5973-2/7 LA6543 MUTE2 VCC RF RF VREF-IN VREF-OUT Pin Assignment 23 22 21 20 19 18 17 VO8 VIN4 25 16 VO7 VG3 26 15 VS2 VIN3 27 14 NC VG2 28 Heat sink VIN2 29 NC 30 LA6543 VG4 24 13 VO6 12 VO5 11 VO4 NC 34 7 VO1 1 2 3 4 5 6 VSS1-OUT 8 VO2 VSS1 MUTE1 33 RF 9 VS1 RF VIN1 32 VSS2 10 VO3 VSS2-OUT VG1 31 Top view A11146 No. 5973-3/7 LA6543 Pin Function Pin number Pin name 1 V SS2-OUT Equivalent circuit Pin function Output stage reference voltage (V SS2-V BE)/2: typ) 2 3,4 20,21 Connect to V S 2 V SS2 Substrate (minimum potential) VS RF 9 15 7 V O1 8 VO2 10 V O3 11 VO 11 12 7 V O4 13 16 12 V O5 17 13 V O6 4 16 V O7 17 VO8 3 20 RF 21 9 VS 1 15 VS 2 (CH4) 5 V SS1 Connect to V S 1 6 V SS1-OUT 34 18 8 10 CH1 inverted output (CH1-) Drive circuit 14,30 CH1 non-inverted output (CH1+) CH2 non-inverted output (CH2+) CH2 inverted output (CH2-) CH3 non-inverted output (CH3+) CH3 inverted output (CH3-) CH4 non-inverted output (CH4+) CH4 inverted output (CH4-) A11144 Output reference voltage (V SS1/2: typ) May not be used. NC Output reference voltage V REF-OUT (V REF buffer amplifier output) 22 VCC 24 VG4 26 VG3 28 VG2 31 VG1 25 V IN4 32 27 V IN3 26 29 V IN2 32 V IN1 Input pin for CH4 (gain adjustment) Input pin for CH3 (gain adjustment) VIN 29 25 11kΩ Drive circuit 27 Input pin for CH2 (gain adjustment) Input pin for CH1 (gain adjustment) Input pin for CH4 (fixed gain) Input pin for CH3 (fixed gain) VG 28 24 4 31 3 20 RF 21 18 VREF OUT 19 Power supply for output stage (CH1 to CH3) Input pin for CH2 (fixed gain) Input pin for CH1 (fixed gain) A11143 Reference voltage input V REF-IN (V REF buffer amplifier input) 22 V CC 23 MUTE2 33 MUTE1 Power supply CH2-CH4 amplifier output ON/OFF 22 VCC CH1 amplifier output ON/OFF 33 23 MUTE To bias circuit 4 3 20 RF 21 A11145 No. 5973-4/7 LA6543 Block Diagram VREF OUT MUTE1 MUTE2 VS1 V82 Thermal shutdown – VREF IN + MUTE1 CH1 (VO1–VO2) Level shift VIN1 11 kΩ MUTE2 CH2 (VO3–VO4) CH3 (VO5–VO6) CH4 (VO7–VO8) – VO1 + – VG1 VO2 + – Level shift VIN2 11 kΩ VO3 + – VG2 VO4 + Level shift VIN3 11 kΩ – VO5 + – VG3 VO6 + Level shift VIN4 11 kΩ – VO7 + – VG4 VO8 + VSS2 VCC VSS1 VCC – – + RF + VSS1-OUT VSS2-OUT A11149 System Diagram (relationship between power supply and MUTE) (VS1/VS2) (MUTE1/MUTE2) MUTE1 CH1(VO1–VO2) CH2(VO3–VO4) MUTE2 VS 1 CH3(VO5–VO6) CH4(VO7–VO8) VS 2 A11147 No. 5973-5/7 LA6543 Sample Application Circuit Reference voltage Tracking input 21 20 19 18 RF RF VREF IN VREF OUT M VO7 16 26 VG3 VS2 15 27 VIN3 NC 14 28 VG2 Focus input VO8 17 25 VIN4 Heat sink 29 VIN2 30 NC LA6543 Sled input 22 VCC 24 VG4 23 MUTE2 Microprocessor Sled 12V power supply VO6 13 Tracking VO5 12 VO4 11 Focus 33 MUTE1 VO2 8 34 NC VSS1 OUT Microprocessor VSS1 VS1 9 RF 32 VIN1 RF Loading input VSS2 VO3 10 VSS2 OUT 31 VG1 1 2 3 4 5 6 5V power supply M Loading VO1 7 A11148 No. 5973-6/7 LA6543 Gain Setting (input pins and adjustment pins) A simplified diagram of VIN and VG is shown below. 1) Consider an 11 kΩ (typ.) resistor inserted between VIN and VG. 2) When not the pin VG but the pin VIN is used alone, the BTL gain (between VO+ and V O–) is set to 7 dB for CH1 to CH3 (1 dB for AMP only). For CH4, it is 14 dB (8 dB for AMP only). This also applies for the case when VIN is not used and an 11 kΩ external resistor is connected to VG for input. 3) Gain is set by the input impedance as seen from point A. When VG only is used and the external resistor is R, the BTL gain (between VO+ and VO– ) is 20 log (11 kΩ /R) + 14 dB. When an 11 kΩ resistor is inserted between VIN and VG, and input is via VIN , the combined resistance Rz as seen from point A is Rz = 5.5 kΩ. Gain is CH1 to CH3 : 20 log (11 kΩ/5.5 kΩ) + 7 dB = 13 dB CH4 : 20 log (11 kΩ/5.5 kΩ) + 14 dB = 20 dB. VG 11 kΩ VIN Level shift – VREF1 + VREF VSS CH4 only 11 kΩ – AMP1 + VO+ – AMP2 + VO– A – VREF2 + 11 kΩ A11150 GND Offset Voltage This IC incorporates a level shifter circuit. The input references the voltage VREF to be applied and references the voltage (VSS1)/2V for channels 1 to 3 or the voltage (VSS2–V BE (0.7))/2V for channel 4 to be output. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 5973-7/7