Ordering number : EN7739A Monolithic Linear IC LA6571 5CH Driver for Mini Disk and Compact Disk Overview The LA6571 is 5-channel driver for mini disk and compact disk applications (BTL-AMP: 5CH). Features • Power amplifier 5-channel built-in. • IO max 1A • Level shift circuit built-in. • Mute circuit (output ON/OFF) with three built-in channels (2-2-1). (Operates independently for each of MUTE1: CH1 and 2, MUTE2: CH3 and 4, and MUTE3: CH5. Not operating for the regulator (REG)) • Regulator (REG) built-in (external PNP transistor). Voltage setting (typ: 1.5V or more) with an external resistor • Overheat protection circuit (thermal shutdown) built-in. Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings VCC max Supply voltage Unit 14 V Maximum output current IO max 1 A Maximum input voltage VINB 13 V MUTE pin voltage VMUTE 13 V Allowable loss Pd max Each output for channel 1 to 5. Independent IC Mounted on a specified board* 0.8 W 2 W Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C * Mounted on a specified board: 76.1mm×114.3mm×1.6mm glass epoxy Recommended Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage 1 VCC1 4.5 to VCC2 V Supply voltage 2 VCC2 6 to 13 V Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 92706 / 40506 MS IM B8-8101, 5525 No.7739-1/7 LA6571 Electrical Characteristics at Ta = 25°C, VCC1 = 5V, VCC2 = 12V, VREF-IN = 1.65V, unless especially specified Parameter Symbol Ratings Conditions min typ Unit max [ALL Blocks] No-load current drain ON ICC ON All outputs ON *1 30 50 mA No-load current drain OFF ICC OFF All outputs OFF *1 10 20 mA VREF input voltage range VREF-IN Thermal shutdown temperature TSD 1 *7 VCC2-1 V 200 °C -50 50 mV -80 80 mV 150 175 [BTL AMP Block] (CH1 to CH5) Output offset voltage VOFF Voltage difference in output between BTL AMP and each channel. Output offset voltage VOFF1 Voltage difference in output between BTL AMP and each channel. Output voltage VO CH1,CH2 *3 3.2 4.0 V Output voltage VO1 CH3,CH4,CH5 *4 9.7 10.5 V Closed-circuit voltage gain V G1 Gain between input and output for CH1, CH2, 4.2 5.0 6.0 times 8.2 9.0 11.0 times and CH5 *2 Closed-circuit voltage gain V G3 Gain between input and output for CH3 and CH4 *2 Slew rate SR AMP Independent. 0.5 Multiply 2 between outputs. *7 MUTE ON voltage VMUTE ON Each MUTE *6 MUTE OFF voltage VMUTE OFF Each MUTE *6 V/µs 2 V 0.5 V [Input AMP Block] Input voltage range VIN op Output offset voltage VOFF op Output current (SINK) SINK op Output current (SOURCE) SOURCE op 0 VCC2-1.5 -10 10 2 V mV mA *5 300 500 For error Amp, RL = 10kΩ at buffer 1.2 1.3 5 10 µA [Power Supply Block] (PNP transistor: 2SB632K) Regulator output REG-IN SINK current VOUT 1.4 V REG-IN-SINK Base current to external PNP Line regulation ∆VOLN 6V ≤ VCC ≤ 12V, IO = 200mA 20 150 mV Load regulation ∆VOLD 5mA ≤ IO ≤ 200mA 50 200 mV mA *1. Current dissipation that is a sum of VCC1 and VCC2 at no load. *2. Input AMP is a BUFFER AMP. *3. Voltage difference between both ends of load (8Ω). Output saturated. *4. Voltage difference between both ends of load (12Ω). Output saturated. *5. The source of input OP-AMP is a constant current. (See the specified block diagram.) As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input OP-AMP gain. *6. Output ON with MUTE: [H] and OFF with MUTE: [L] (HI impedance). *7. Design guarantee value No.7739-2/7 LA6571 Package Dimensions unit : mm 3251 Pd max - Ta 17.8 (6.2) 19 0.65 (4.9) 7.9 10.5 36 2.0 0.3 18 0.25 0.1 2.7 2.45max 0.8 (2.25) (0.5) 1 Allowable Power Dissipation, Pd max - W 3.0 Mounted on a specified board: 76.1mm×114.3mm×1.6mm glass epoxy 2.5 Mounted on a specified board 2.0 1.5 1.04 1.0 Independent IC 0.8 0.5 0.42 0 -40 -30 -20 0 20 40 60 80 85 Ambient Temperature, Ta -°C 100 ILA00922 SANYO : HSOP36R(375mil) Pin Description Pin Pin Name Name VIN1+ VIN1− VIN1 VIN2+ VIN2− VIN2 VIN3+ VIN3− Output MUTE Description Each input pin 17 16 VIN- 15 20 VIN VCC 19 18 23 22 VIN3 VIN4− VIN4+ 21 VIN4 VIN5+ VIN5− VIN5 31 VO1+ VO1− VO2+ VO2− VO3+ VO3− VO4+ VO4− VO5+ VO5− Equivalent Circuit Diagram VIN+ 30 29 32 33 S-GND 34 Each output 12 VCC 13 10 11 8 VO 9 6 7 RF 5 4 MUTE1 1 MUTE2 2 MUTE1: CH1, 2 MUTE3 36 MUTE2: CH3, 4, and Turns ON/OFF the output for VCC MUTE3: CH5. Each MUTE operates MUTE S-GND 100kΩ 100kΩ Input Pin No. independently. MUTE: H output ON MUTE: L output OFF With the output OFF, the output has a high impedance. No.7739-3/7 LA6571 Relationship between MUTE and Power (VCC) CH1 (4-fold) MUTE1 VCC1 (5V) CH2 (4-fold) CH3 (10.5-fold) MUTE2 VCC2 (12V) CH4 (10.5-fold) MUTE3 CH5 (10.5-fold) * MUTE operates independently for each corresponding channel. Schematic Diagram of I/O Related Components VINVIN+ Level Shift 11kΩ VIN 11kΩ - - + + - VREF-IN + + + VO+ VO- + No.7739-4/7 LA6571 Block Diagram MUTE1 1 MUTE1 CH1,2 MUTE2 2 MUTE2 CH3,4 VCC2 3 VO5− 4 Thermal Shutdown Level Shift CH3,4,5 Power Supply VO4+ 6 Level Shift 5 CH4 VO4− MUTE3 Each MUTE operates independently for each corresponding current. “H”: Output ON “L”: Output OFF CH5 VO5+ CH5 7 27.5kΩ 11kΩ - 50kΩ VO3− 9 S-GND 34 VIN5 33 VIN5− 32 VIN5+ 31 VIN4 30 VIN4− 29 VIN4+ 28 VREF-IN FR FR 27 VREF-IN(CH5) 26 REG-IN(B) 25 (NC) 24 REG-VREF 23 VIN3+ 22 VIN3− 21 VIN3 20 VIN2+ 19 VIN2− + + Level Shift CH3 35 + + 11kΩ 8 MUTE3 - VO3+ 36 + FR VO2+ 10 + Level Shift FR CH2 11 VO1+ 12 + CH1 VO1− 13 VCC1 14 VREG - Level Shift VO2− CH1,2 5V Power Supply 50kΩ 11kΩ - VIN1 - + - 15 + + VIN1− 16 27.5kΩ - VIN1+ 17 + 11kΩ + 27.5kΩ 11kΩ - VIN2 18 + + - No.7739-5/7 LA6571 Sample Application Circuit No.7739-6/7 LA6571 Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 2006. Specifications and information herein are subject to change without notice. PS No.7739-7/7