19-2748; Rev 5; 1/11 KIT ATION EVALU E L B A AVAIL 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range The MAX1473 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz frequency range. Its signal range is from -114dBm to 0dBm. With few external components and a low-current power-down mode, it is ideal for cost- and power-sensitive applications typical in the automotive and consumer markets. The chip consists of a low-noise amplifier (LNA), a fully differential image-rejection mixer, an onchip phase-locked-loop (PLL) with integrated voltagecontrolled oscillator (VCO), a 10.7MHz IF limiting amplifier stage with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. The MAX1473 also has a discrete one-step automatic gain control (AGC) that drops the LNA gain by 35dB when the RF input signal is greater than -57dBm. The MAX1473 is available in 28-pin TSSOP and 32-pin thin QFN packages. Both versions are specified for the extended (-40°C to +85°C) temperature range. Features o Optimized for 315MHz or 433MHz ISM Band o Operates from Single 3.3V or 5.0V Supplies o High Dynamic Range with On-Chip AGC o Selectable Image-Rejection Center Frequency o Selectable x64 or x32 fLO/fXTAL Ratio o Low 5.2mA Operating Supply Current o < 2.5µA Low-Current Power-Down Mode for Efficient Power Cycling o 250µs Startup Time o Built-In 50dB RF Image Rejection o Receive Sensitivity of -114dBm Ordering Information PART Applications Automotive Remote Keyless Entry Garage Door Openers Security Systems Home Automation Remote Controls Wireless Sensors Local Telemetry Systems TEMP RANGE PIN-PACKAGE MAX1473EUI+ -40°C to +85°C 28 TSSOP MAX1473ETJ+ -40°C to +85°C 32 Thin QFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Functional Diagram and Typical Application Circuit appear at end of data sheet. LNASRC 4 25 DATAOUT AGND 5 LNAOUT 6 MAX1473 XTAL1 XTAL2 PWRDN PDOUT N.C. 28 27 26 25 + AVDD 26 PDOUT 29 LNAIN 3 30 27 PWRDN LNAIN 28 XTAL2 AVDD 2 LNASRC + XTAL1 1 31 TOP VIEW 32 Pin Configurations N.C. 1 24 DATAOUT 24 VDD5 AGND 2 23 VDD5 23 DSP LNAOUT 3 22 DSP 21 N.C. 20 DFFB AVDD 7 22 DFFB AVDD 4 MIXIN1 8 21 OPP MIXIN1 5 MIXIN2 9 20 DSN MIXIN2 6 19 OPP AGND 10 19 DFO AGND 7 18 DSN IRSEL 11 18 IFIN2 IRSEL 8 17 DFO MIXOUT 12 17 IFIN1 13 14 15 16 N.C. IFIN1 IFIN2 12 XTALSEL 11 DVDD AGCDIS TSSOP 9 15 AGCDIS 10 DVDD 14 DGND 16 XTALSEL MIXOUT DGND 13 MAX1473 THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1473 General Description MAX1473 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range ABSOLUTE MAXIMUM RATINGS VDD5 to AGND.......................................................-0.3V to +6.0V AVDD to AGND .....................................................-0.3V to +4.0V DVDD to DGND .....................................................-0.3V to +4.0V AGND to DGND.....................................................-0.1V to +0.1V IRSEL, DATAOUT, XTALSEL, AGCDIS, PWRDN to AGND .....................................-0.3V to (VDD5 + 0.3V) All Other Pins to AGND ..............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin TSSOP (derate 12.8mW/°C above +70°C) .1025.6mW 32-Pin Thin QFN (derate 21.3mW/°C above +70°C).........................................................1702.1mW Operating Temperature Ranges MAX1473E__ ..................................................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (3.3V OPERATION) (Typical Application Circuit, VDD = 3.0V to 3.6V, no RF signal applied, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1) PARAMETER Supply Voltage Supply Current Shutdown Supply Current SYMBOL VDD CONDITIONS 3.3V nominal supply IDD V P WRDN = VDD IPWRDN V P WRDN = 0V, VXTALSEL = 0V Input Voltage Low VIL Input Voltage High VIH Input Logic Current High IIH MIN 3.0 TYP DATAOUT Voltage Output Low VOL DATAOUT Voltage Output High VOH 2 UNITS V 3.3 3.6 fRF = 315MHz 5.2 6.23 fRF = 433MHz 5.8 6.88 fRF = 315MHz 1.6 fRF = 433MHz 2.5 5.3 0.4 VDD - 0.4 µA V µA VDD - 0.4 fRF = 375MHz, VIRSEL = VDD/2 1.1 fRF = 315MHz, VIRSEL = 0V 0.4 RL = 5kΩ mA V 10 fRF = 433MHz, VIRSEL = VDD Image Reject Select (Note 2) MAX VDD - 0.4 _______________________________________________________________________________________ VDD - 1.5 V 0.4 V V 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range (Typical Application Circuit, VDD = 4.5V to 5.5V, no RF signal applied, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 5.0V and TA = +25°C.) (Note 1) PARAMETER Supply Voltage SYMBOL VDD Supply Current Shutdown Supply Current CONDITIONS IDD V P WRDN = VDD IPWRDN V P WRDN = 0V, VXTALSEL = 0V Input Voltage Low VIL Input Voltage High VIH Input Logic Current High IIH MIN TYP MAX UNITS 4.5 5.0 5.5 V fRF = 315MHz 5.2 6.04 fRF = 433MHz 5.7 6.76 fRF = 315MHz 2.3 fRF = 433MHz 2.8 5.0V nominal supply 0.4 VDD - 0.4 DATAOUT Voltage Output Low VOL DATAOUT Voltage Output High VOH 10 V µA VDD - 0.4 fRF = 375MHz, VIRSEL = VDD/2 1.1 fRF = 315MHz, VIRSEL = 0V 0.4 VDD - 1.5 0.4 RL = 5kΩ µA V fRF = 433MHz, VIRSEL = VDD Image Reject Select (Note 2) 6.2 mA VDD - 0.4 V V V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, VDD = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS Startup Time tON Receiver Input Frequency Time for valid signal detection after V P WRDN = VOH fRF 300 Maximum Receiver Input Level PRFIN_MAX Modulation depth > 18dB Sensitivity (Note 3) PRFIN_MIN AGC Hysteresis 250 450 0 Average carrier power level -120 Peak power level -114 LNA gain from low to high µs MHz dBm dBm 8 dB 150 ms 16 dB LNA IN HIGH-GAIN MODE Power Gain Input Impedance ZIN_LNA 1dB Compression Point Input-Referred 3rd-Order Intercept Normalized to 50Ω (Note 4) fRF = 433MHz 1 - j3.4 fRF = 375MHz 1 - j3.9 fRF = 315MHz 1 - j4.7 P1dBLNA -22 dBm IIP3LNA -12 dBm _______________________________________________________________________________________ 3 MAX1473 DC ELECTRICAL CHARACTERISTICS (5.0V OPERATION) MAX1473 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, VDD = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS LO Signal Feedthrough to Antenna Noise Figure NFLNA MIN TYP MAX UNITS -80 dBm 2 dB LNA IN LOW-GAIN MODE Input Impedance (Note 4) 1dB Compression Point Input-Referred 3rd-Order Intercept ZIN_LNA Normalized to 50Ω fRF = 433MHz 1 - j3.4 fRF = 375MHz 1 - j3.9 fRF = 315MHz 1 - j4.7 P1dBLNA -10 dBm IIP3LNA -7 dBm -80 dBm LO Signal Feedthrough to Antenna Noise Figure NFLNA 2 dB 0 dB 35 dB IIP3MIX -18 dBm ZOUT_MIX 330 Ω NFMIX 16 dB Power Gain Voltage Gain Reduction AGC enabled (depends on tank Q) MIXER Input-Referred 3rd-Order Intercept Output Impedance Noise Figure fRF = 433MHz, VIRSEL = VDD Image Rejection (not Including LNA Tank) Conversion Gain 42 fRF = 375MHz, VIRSEL = VDD/2 44 fRF = 315MHz, VIRSEL = 0V 44 330Ω IF filter load 13 dB dB INTERMEDIATE FREQUENCY (IF) Input Impedance Operating Frequency ZIN_IF fIF Bandpass response 3dB Bandwidth RSSI Linearity RSSI Dynamic Range RSSI Level 4 Ω MHz 20 MHz ±0.5 dB 80 dB PRFIN < -120dBm 1.15 PRFIN > 0dBm, AGC enabled 2.35 LNA gain from low to high 1.45 LNA gain from high to low 2.05 RSSI Gain AGC Threshold 330 10.7 14.2 _______________________________________________________________________________________ V mV/dB V 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range (Typical Application Circuit, VDD = 3.0V to 3.6V, all RF inputs are referenced to 50Ω, fRF = 315MHz, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DATA FILTER Maximum Bandwidth BWDF 100 kHz Comparator Bandwidth BWCMP 100 kHz Maximum Load Capacitance CLOAD 10 pF Output High Voltage VDD5 V Output Low Voltage 0 V DATA SLICER CRYSTAL OSCILLATOR fRF = 433MHz Crystal Frequency (Note 5) fXTAL fRF = 315MHz VXTALSEL = 0V 6.6128 VXTALSEL = VDD 13.2256 VXTALSEL = 0V 4.7547 VXTALSEL = VDD 9.5094 Crystal Tolerance Input Impedance From each pin to ground MHz MHz 50 ppm 6.2 pF Note 1: 100% tested at TA = +25°C. Guaranteed by design and characterization over temperature. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image rejection setting is desired. A 1nF capacitor is recommended in noisy environments. Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = VDD. _______________________________________________________________________________________ 5 MAX1473 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. RF FREQUENCY +85°C 5.3 +25°C 5.2 5.1 MAX1473 toc02 100 fRF = 433MHz 10 +105°C BIT-ERROR RATE (%) SUPPLY CURRENT (mA) 5.4 6.5 SUPPLY CURRENT (mA) +105°C 5.5 7.0 MAX1473 toc01 5.6 BIT-ERROR RATE vs. AVERAGE RF INPUT POWER MAX1473 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE 6.0 5.5 +85°C 1 fRF = 315MHz 0.1 +25°C 5.0 -40°C -40°C 3.2 3.3 3.4 3.6 3.5 400 450 SENSITIVITY vs. TEMPERATURE RSSI vs. RF INPUT POWER MAX1473 toc04 -121 -120 500 IF BANDWIDTH = 280kHz 2.2 VAGCDIS = VDD RSSI (V) -110 -111 1.8 VAGCDIS = 0V 1.6 1.4 fRF = 315MHz -114 10 35 60 85 TEMPERATURE (°C) SYSTEM GAIN vs. FREQUENCY 10 50dB IMAGE REJECTION 0 LOWER SIDEBAND -10 FROM RFIN TO MIXOUT fRF = 315MHz -20 -60 -40 -20 5 10 15 20 IF FREQUENCY (MHz) 25 0.5 1.6 -0.5 DELTA -1.5 RSSI -2.5 -3.5 -90 -70 -50 -30 IMAGE REJECTION vs. RF FREQUENCY IMAGE REJECTION vs. TEMPERATURE 50 45 40 fRF = 375MHz -10 10 60 85 45 fRF = 315MHz 45 44 44 43 fRF = 375MHz 43 42 fRF = 433MHz 42 fRF = 315MHz fRF = 433MHz 30 1.8 IF INPUT POWER (dBm) 41 30 0 1.5 RF INPUT POWER (dBm) 35 -30 2.0 0 MAX1473 toc08 20 -80 55 IMAGE REJECTION (dB) UPPER SIDEBAND MAX1473 toc07 30 2.5 1.0 -140 -120 -100 110 IMAGE REJECTION (dB) -15 2.2 1.2 1.0 -40 3.5 1.4 1.2 -113 MAX1473 toc06 2.4 2.0 -109 -119 -118 -117 -116 -115 -114 AVERAGE INPUT POWER (dBm) RSSI AND DELTA vs. IF INPUT POWER 2.4 fRF = 433MHz -108 -112 6 350 RF FREQUENCY (MHz) PEAK RF INPUT POWER 1% BER IF BANDWIDTH = 280MHz -107 300 SUPPLY VOLTAGE (V) -105 -106 250 RSSI (V) 3.1 MAX1473 toc05 3.0 SENSITIVITY (dBm) 0.01 4.5 41 280 330 380 430 RF FREQUENCY (MHz) 480 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ DELTA (dB) 4.9 MAX1473 toc09 5.0 SYSTEM GAIN (dB) MAX1473 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range NORMALIZED IF GAIN vs. IF FREQUENCY -5 -10 MAX1473 toc12 MAX1473 toc11 MAX1473 toc10 0 S11 SMITH PLOT OF RFIN S11 MAGNITUDE-LOG PLOT OF RFIN 30 20 10 MAGNITUDE (dB) NORMALIZED IF GAIN (dB) 5 600MHz 0 -10 -20 100MHz -30 -40 315MHz -34dB -50 -15 -60 -70 -20 IF FREQUENCY (MHz) RF FREQUENCY (MHz) REGULATOR VOLTAGE vs. REGULATOR CURRENT PHASE NOISE vs. OFFSET FREQUENCY 0 MAX1473 toc13 -40°C 2.9 +25°C +85°C +105°C 2.8 2.7 2.6 VDD = 5.0V 2.5 5 15 25 35 REGULATOR CURRENT (mA) -20 PHASE NOISE (dBc/Hz) 3.0 45 fRF = 315MHz PHASE NOISE vs. OFFSET FREQUENCY 0 -40 -60 -80 -100 fRF = 433MHz -20 PHASE NOISE (dBc/Hz) 3.1 REGULATOR VOLTAGE (V) 10 109 208 307 406 505 604 703 802 901 1000 100 MAX1473 toc15 10 MAX1473 toc14 1 -40 -60 -80 -100 -120 -120 -140 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 -140 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 OFFSET FREQUENCY (MHz) OFFSET FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX1473 Typical Operating Characteristics (continued) (Typical Application Circuit, VDD = 3.3V, fRF = 315MHz, TA = +25°C, unless otherwise noted.) MAX1473 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Pin Description PIN TSSOP TQFN 1 29 FUNCTION XTAL1 1st Crystal Input. (See the Phase-Locked Loop section.) Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close as possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section and the Typical Application Circuit). Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.) 2, 7 4, 30 AVDD 3 31 LNAIN 4 32 LNASRC 5 2 AGND 6 3 LNAOUT 8 5 MIXIN1 Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set LNA input impedance. (See the Low-Noise Amplifier section.) Analog Ground Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise Amplifier section.) 1st Differential Mixer Input. Connect through a 100pF capacitor to VDD3 side of the LC tank. 9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT. 10 7 AGND Analog Ground 8 IRSEL Image Rejection Select Pin. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = VDD to center image rejection at 433MHz. 12 9 MIXOUT 13 10 DGND Digital Ground 14 11 DVDD Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF capacitor as close as possible to the pin (see the Typical Application Circuit). 15 12 AGCDIS 16 14 XTALSEL 17 15 IFIN1 18 16 IFIN2 19 17 DFO Data Filter Output 20 18 DSN Negative Data Slicer Input 21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter 22 20 DFFB Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. 23 22 DSP Positive Data Slicer Input 24 23 VDD5 +5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For +5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.2V output appears at the pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.) 25 24 26 26 PDOUT Peak Detector Output 27 27 PWRDN Power-Down Select Input. Drive this pin with a logic high to power on the IC. 28 28 XTAL2 — 1, 13, 21, 25 N.C. — — EP 11 8 NAME 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter. AGC Control Pin. Pull high to disable AGC. Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL high to select divider ratio of 32. 1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF capacitor. 2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz bandpass filter. DATAOUT Digital Baseband Data Output 2nd Crystal Input No Connection Exposed Pad (TQFN Only). Connect EP to GND. _______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range The MAX1473 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 100kbps can be achieved. The MAX1473 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. Voltage Regulator For operation with a single +3.0V to +3.6V supply voltage, connect AVDD, DVDD, and VDD5 to the supply voltage. For operation with a single +4.5V to +5.5V supply voltage, connect VDD5 to the supply voltage. An on-chip voltage regulator drives one of the AVDD pins to approximately +3.2V. For proper operation, DVDD and both the AVDD pins must be connected together. Bypass VDD5, DVDD, and the pin 7 AVDD pin to AGND with 0.01µF capacitors, and the pin 2 AVDD pin to AGND with a 0.1µF capacitor, all placed as close as possible to the pins. Low-Noise Amplifier The LNA is an NMOS cascode amplifier with off-chip inductive degeneration that achieves approximately 16dB of power gain with a 2.0dB noise figure and an IIP3 of -12dBm. The gain and noise figure are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a typical PCB trace antenna. A nominal value for this inductor with a 50Ω input impedance is 15nH, but is affected by PCB trace. See the Typical Operating Characteristics for the relationship between the inductance and the LNA input impedance. The AGC circuit monitors the RSSI output. When the RSSI output reaches 2.05V, which corresponds to an RF input level of approximately -57dBm, the AGC switches on the LNA gain reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.45V (approximately -65dBm at RF input) for 150ms. The AGC has a hysteresis of ~8dB. With the AGC func- tion, the MAX1473 can reliably produce an ASK output for RF input levels up to 0dBm with a modulation depth of 18dB. The LC tank filter connected to LNAOUT comprises L3 and C2 (see the Typical Application Circuit). Select L3 and C2 to resonate at the desired RF input frequency. The resonant frequency is given by: f = 1 2π L TOTAL × C TOTAL where: LTOTAL = L3 + LPARASITICS CTOTAL = C2 + CPARASITICS LPARASITICS and CPARASITICS include inductance and capacitance of the PCB traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. Mixer A unique feature of the MAX1473 is the integrated image rejection of the mixer. This device eliminates the need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF fIF). The image-rejection circuit then combines these signals to achieve a minimum 45dB of image rejection over the full temperature range. Low-side injection is required due to the on-chip image rejection architecture. The IF output is driven by a source-follower biased to create a driving impedance of 330Ω; this provides a good match to the off-chip 330Ω ceramic IF filter. The voltage conversion gain is approximately 13dB when the mixer is driving a 330Ω load. The IRSEL pin is a logic input that selects one of the three possible image-rejection frequencies. When VIRSEL = 0V, the image rejection is tuned to 315MHz. VIRSEL = VDD/2 tunes the image rejection to 375MHz, and when VIRSEL = VDD, the image rejection is tuned to 433MHz. The IRSEL pin is internally set to VDD/2 (image rejection at 375MHz) when it is left unconnected, thereby eliminating the need for an external VDD/2 voltage. _______________________________________________________________________________________ 9 MAX1473 Detailed Description MAX1473 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range Phase-Locked Loop The PLL block contains a phase detector, charge pump/integrated loop filter, VCO, asynchronous 64x clock divider, and crystal oscillator driver. Besides the crystal, this PLL does not require any external components. The VCO generates a low-side local oscillator (LO). The relationship between the RF, IF, and reference frequencies is given by: fREF = (fRF - fIF)/(32 M) where: M = 1 (VXTALSEL = VDD) or 2 (VXTALSEL = 0V) The AGC circuit monitors the RSSI output. When the RSSI output reaches 2.05V, which corresponds to an RF input level of approximately -57dBm, the AGC switches on the LNA gain reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.45V (approximately -65dBm at RF input) for 150ms. The AGC has a hysteresis of ~8dB. With the AGC function, the MAX1473 can reliably produce an ASK output for RF input levels up to 0dBm with modulation depth of 18dB. Applications Information To allow the smallest possible IF bandwidth (for best sensitivity), the tolerance of the reference must be minimized. Intermediate Frequency/RSSI The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The six internal AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 11.5MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.2mV/dB (see the Typical Operating Characteristics). Crystal Oscillator The XTAL oscillator in the MAX1473 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. For example, a 4.7547MHz crystal designed to operate with a 10pF load capacitance oscillates at 4.7563MHz with the MAX1473, causing the receiver to be tuned to 315.1MHz rather than 315.0MHz, an error of about 100kHz, or 320ppm. Table 1. Component Values for Typical Application Circuit COMPONENT VALUE FOR 433MHz RF VALUE FOR 315MHz RF DESCRIPTION C1 C2 100pF 2.7pF 100pF 4.7pF 5% ± 0.1pF C3 100pF 100pF 5% 10 C4 100pF 100pF 5% C5 C6 1500pF 220pF 1500pF 220pF 10% 5% C7 470pF 470pF 5% C8 0.47µF 0.47µF 20% C9 C10 220pF 0.01µF 220pF 0.01µF 10% 20% C11 0.01µF 0.01µF 20% C12 15pF 15pF Depends on XTAL C13 L1 15pF 56nH 15pF 110nH Depends on XTAL TOKO LL1608-FH L2 15nH 15nH Murata LQP11A L3 15nH 27nH Murata LQP11A R1 X1 5kΩ 6.6128MHz or 13.2256MHz 5kΩ 4.7547MHz or 9.5094MHz 5% — X2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range where: fp is the amount the crystal frequency pulled in ppm. Cm is the motional capacitance of the crystal. Ccase is the case capacitance. Cspec is the specified load capacitance. Cload is the actual load capacitance. When the crystal is loaded as specified, i.e., Cload = Cspec, the frequency pulling equals zero. Data Filter The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 1 can create a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of C5 and C6, use the following equations along with the coefficients in Table 2: b C5 = a 100k π fc ( )( )( ) C6 = a ( )( )( ) 4 100k π fc where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a corner frequency of 5kHz: C5 = ( )( 1.000 )( )( ) 1.414 100kΩ 3.14 5kHz ≈ 450pF Choosing standard capacitor values changes C5 to 470pF and C6 to 220pF, as shown in the Typical Application Circuit. Data Slicer The purpose of the data slicer is to take the analog output of the data filter and convert it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. One input is supplied by the data filter output. Both comparator inputs are accessible off chip to allow for different methods of generating the slicing threshold, which is applied to the second comparator input. The suggested data slicer configuration uses a resistor (R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 2). This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The sizes of R1 and C4 affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. MAX1473 RSSI RDF1 100kΩ RDF2 100kΩ 22 DFFB 21 OPP 19 DFO C6 C5 Figure 1. Sallen-Key Lowpass Data Filter Table 2. Coefficents to Calculate C5 and C6 FILTER TYPE a b Butterworth (Q = 0.707) 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 ______________________________________________________________________________________ 11 MAX1473 In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: ⎞ C ⎛ 1 1 ⎟ × 106 fp = m ⎜ ⎜ 2 ⎝ Ccase + Cload Ccase + Cspec ⎟⎠ MAX1473 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 MAX1473 DATA SLICER DATA SLICER 20 DSN 25 DATAOUT 19 DFO 23 DSP 25 DATAOUT 20 DSN 23 DSP R4 19 DFO R1 C4 R3 R1 R2 C4 *OPTIONAL Figure 2. Generating Data Slicer Threshold Note that a long string of zeros or 1’s can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and 1’s, is used. Figure 3. Generating Data Slicer Hysteresis To prevent continuous toggling of DATAOUT in the absence of an RF signal due to noise, hysteresis can be added to the data slicer as shown in Figure 3. MAX1473 Peak Detector The peak detector output (PDOUT), in conjunction with an external RC filter, creates a DC output voltage equal to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data filter output voltage. For faster receiver startup, the circuit shown in Figure 4 can be used. DATA SLICER 25 DATAOUT 20 DSN 12 19 DFO 26 PDOUT 25kΩ Layout Considerations A properly designed PCB is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of λ/10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PCB trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all power-supply pins. 23 DSP 47nF Figure 4. Using PDOUT for Faster Startup Chip Information PROCESS: CMOS ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range VDD VDD3 THEN VDD3 IS IF VDD IS (SEE TABLE) 3.0V TO 3.6V CONNECTED TO VDD 4.5V TO 5.5V X1 CREATED BY LDO, AVAILABLE AT AVDD (PIN 2) C11 C12 C13 1 RF INPUT 2 C1 L1 3 4 L2 5 6 C14 VDD3 7 L3 C3 8 C2 9 C4 10 C9 11 12 13 14 XTAL1 XTAL2 AVDD PWRDN LNAIN PDOUT MAX1473 LNASRC DATAOUT AGND VDD5 LNAOUT DSP AVDD DFFB MIXIN1 OPP MIXIN2 DSN AGND DFO IRSEL IFIN2 MIXOUT IFIN1 DGND XTALSEL DVDD AGCDIS 28 TO/FROM μP POWER DOWN DATA OUT 27 26 R2 25 C15 24 R3 23 22 21 C7 20 19 18 17 R1 16 15 C5 X2 C6 C8 IF FILTER C10 IN OUT GND COMPONENT VALUES IN TABLE 1 ______________________________________________________________________________________ 13 MAX1473 Typical Application Circuit 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range MAX1473 Functional Diagram LNASRC 4 LNAIN AVDD VDD5 AVDD DVDD DGND AGND 3 AGCDIS LNAOUT 15 6 MIXIN1 MIXIN2 8 9 Q IMAGE REJECTION 2 24 IFIN1 17 IFIN2 18 0˚ AUTOMATIC GAIN CONTROL LNA MIXOUT 12 IRSEL 11 IF LIMITING AMPS ∑ 90˚ 3.2V REG I MAX1473 RSSI 7 14 13 5,10 DIVIDE BY 64 VCO PHASE DETECTOR LOOP FILTER ÷1 DATA FILTER RDF1 100kΩ RDF2 100kΩ ÷2 CRYSTAL DRIVER 16 1 XTALSEL XTAL1 XTAL2 28 DATA SLICER POWER DOWN 27 25 PWRDN DATAOUT 20 23 19 DSN DSP DFO 26 21 22 PDOUT OPP DFFB Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 14 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 TSSOP U28+1 21-0066 90-0171 32 Thin QFN-EP T3255+3 21-0140 90-0001 ______________________________________________________________________________________ 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range REVISION NUMBER REVISION DATE 4 5/10 Added lead-free parts and exposed pad in Ordering Information and Pin Description tables 1/11 Updated Absolute Maximum Ratings, AC Electrical Characteristics, Pin Description, Layout Considerations, Typical Application Circuit, Functional Diagram, and Package Information; added Voltage Regulator section to the Detailed Description section 5 DESCRIPTION PAGES CHANGED 1, 8 2, 3, 4, 8, 9, 12, 13, 14 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX1473 Revision History