AD AD8422ARMZ-RL

FEATURES
CONNECTION DIAGRAM
APPLICATIONS
AD8422
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
Figure 1. 8-Lead MSOP (RM), 8-Lead SOIC (R)
–20
RL = 2kΩ
VOUT = ±10V
–30
–40
–50
AMPLITUDE (dBc)
Low power: 330 µA maximum quiescent current
Rail-to-rail output
Low noise and distortion
8 nV/√Hz maximum input voltage noise at 1 kHz
0.15 µV p-p RTI noise (G = 100)
0.5 ppm nonlinearity with 2 kΩ load (G = 1)
Excellent ac specifications
80 dB minimum CMRR at 7 kHz (G = 1)
2.2 MHz bandwidth (G = 1)
High precision dc performance (AD8422BRZ)
150 dB minimum CMRR (G = 1000)
0.04% maximum gain error (G = 1000)
0.3 µV/°C maximum input offset drift
0.5 nA maximum input bias current
Wide supply range
3.6 V to 36 V single supply
±1.8 V to ±18 V dual supply
Input overvoltage protection: 40 V from opposite supply
Gain range: 1 to 1000
11197-001
–60
–70
–80
G = 1000
–90
–100
G = 100
–110
G = 10
G=1
–120
–130
Medical instrumentation
Industrial process controls
Strain gages
Transducer interfaces
Precision data acquisition systems
Channel-isolated systems
Portable instrumentation
–140
10
100
FREQUENCY (Hz)
1k
5k
11197-102
Data Sheet
High Performance, Low Power, Rail-to-Rail
Precision Instrumentation Amplifier
AD8422
Figure 2. Total Harmonic Distortion vs. Frequency
GENERAL DESCRIPTION
The AD8422 is a high precision, low power, low noise, rail-to-rail
instrumentation amplifier that delivers the best performance
per unit microampere in the industry. The AD8422 processes
signals with ultralow distortion performance that is load
independent over its full output range.
The AD8422 is the third generation development of the industrystandard AD620. The AD8422 employs new process technologies
and design techniques to achieve higher dynamic range and
lower errors than its predecessors, while consuming less than
one-third of the power. The AD8422 uses the high performance
pinout introduced by the AD8221.
Very low bias current makes the AD8422 error-free with high
source impedance, allowing multiple sensors to be multiplexed
to the inputs. Low voltage noise and low current noise make the
AD8422 an ideal choice for measuring a Wheatstone bridge.
Rev. 0
The wide input range and rail-to-rail output of the AD8422
bring all of the benefits of a high performance in-amp to singlesupply applications. Whether using high or low supply voltages,
the power savings make the AD8422 an excellent choice for
high channel count or power sensitive applications on a very
tight error budget.
The AD8422 uses robust input protection that ensures reliability
without sacrificing noise performance. The AD8422 has high
ESD immunity, and the inputs are protected from continuous
voltages up to 40 V from the opposite supply rail.
A single resistor sets the gain from 1 to 1000. The reference pin
can be used to apply a precise offset to the output voltage.
The AD8422 is specified from −40°C to +85°C and has typical
performance curves to 125°C. It is available in 8-lead MSOP
and 8-lead SOIC packages.
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Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8422
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Architecture ................................................................................ 19 Applications ....................................................................................... 1 Gain Selection ............................................................................. 19 Connection Diagram ....................................................................... 1 Reference Terminal .................................................................... 20 General Description ......................................................................... 1 Input Voltage Range ................................................................... 20 Revision History ............................................................................... 2 Layout .......................................................................................... 20 Specifications..................................................................................... 3 Input Bias Current Return Path ............................................... 21 SOIC Package ................................................................................ 3 Input Voltages Beyond the Supply Rails.................................. 21 MSOP Package .............................................................................. 5 Radio Frequency Interference (RFI) ........................................ 22 Absolute Maximum Ratings............................................................ 8 Applications Information .............................................................. 23 Thermal Resistance ...................................................................... 8 Precision Bridge Conditioning ................................................. 23 ESD Caution .................................................................................. 8 Process Control Analog Input .................................................. 23 Pin Configuration and Function Descriptions ............................. 9 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 24 Theory of Operation ...................................................................... 19 REVISION HISTORY
5/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
AD8422
SPECIFICATIONS
SOIC PACKAGE
VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 1.
Parameter
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
G=1
G = 10
G = 100
G = 1000
Over Temperature, G=1
CMRR at 7 kHz
G=1
G = 10
G = 100
G = 1000
NOISE 1
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
Peak to Peak, RTI
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET 2
Input Offset, VOSI
Over Temperature
Average Temperature
Coefficient
Output Offset, VOSO
Over Temperature
Average Temperature
Coefficient
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average Temperature
Coefficient
Input Offset Current
Over Temperature
Average Temperature
Coefficient
Test Conditions/
Comments
Min
AD8422ARZ
Typ
Max
Min
AD8422BRZ
Typ
Max
Unit
VCM = −10 V to +10 V
T = −40°C to +85°C
VCM = −10 V to +10 V
86
106
126
146
83
94
114
134
150
89
dB
dB
dB
dB
dB
80
90
100
100
80
95
100
100
dB
dB
dB
dB
VIN+, VIN−, VREF = 0 V
8
80
8
80
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
2
0.5
0.15
90
8
f = 1 kHz
f = 0.1 Hz to 10 Hz
2
0.5
0.15
90
8
110
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
60
70
0.4
25
40
0.3
µV
µV
µV/°C
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
300
500
5
150
300
2
µV
µV
µV/°C
VS = ±1.8 V to ±18 V
90
110
124
130
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
110
130
150
150
0.5
100
120
140
140
1
2
4
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
0.2
1
Rev. 0 | Page 3 of 24
120
140
160
160
0.2
dB
dB
dB
dB
0.5
1
nA
nA
pA/°C
0.15
0.3
nA
nA
pA/°C
4
0.3
0.8
0.1
1
AD8422
Parameter
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=1
G = 10
G = 100
G = 1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Settling Time 0.001%
G=1
G = 10
G = 100
G = 1000
Slew Rate
GAIN 3
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Gain Nonlinearity
G=1
G = 10
G = 100
G = 1000
Gain vs. Temperature
G=1
G>1
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range 4
Over Temperature
OUTPUT
Output Swing, RL = 10 kΩ
Over Temperature
Output Swing, RL = 10 kΩ
Over Temperature
Output Swing, RL = 2 kΩ
Over Temperature 5
Output Swing, RL = 2 kΩ
Over Temperature
Short-Circuit Current
Data Sheet
Test Conditions/
Comments
Min
AD8422ARZ
Typ
Max
20
35
VIN+, VIN−, VREF = 0 V
Min
AD8422BRZ
Typ
Max
1
1
kΩ
µA
V
V/V
2200
850
120
12
2200
850
120
12
kHz
kHz
kHz
kHz
13
13
12
80
13
13
12
80
µs
µs
µs
µs
15
15
15
160
15
15
15
160
µs
µs
µs
µs
V/µs
–VS
50
+VS
20
35
Unit
–VS
50
+VS
10 V step
10 V step
G = 1 to 100
G = 1 + (19.8 kΩ/RG)
0.8
0.8
1
1000
1
1000
V/V
0.01
0.04
0.04
0.04
%
%
%
%
5
5
10
20
ppm
ppm
ppm
ppm
1
–80
ppm/°C
ppm/°C
GΩ||pF
GΩ||pF
V
V
VOUT ± 10 V
0.03
0.2
0.2
0.2
VOUT = −10 V to +10 V
RL = 2 kΩ
0.5
2
4
10
5
5
10
20
0.5
2
4
10
5
−80
200||2
200||2
200||2
200||2
VS = ±1.8 V to ±18 V
T = −40°C to +85°C
−VS + 1.2
−VS + 1.2
+VS − 1.1
+VS − 1.2
–VS + 1.2
–VS + 1.2
+VS − 1.1
+VS − 1.2
VS = ±15 V
T = −40°C to +85°C
VS = ±1.8 V
T = −40°C to +85°C
VS = ±15 V
T = −40°C to +85°C
VS = ±1.8 V
T = −40°C to +85°C
−VS + 0.2
−VS + 0.25
−VS + 0.12
−VS + 0.13
−VS + 0.25
−VS + 0.3
−VS + 0.15
−VS + 0.2
+VS − 0.2
+VS − 0.25
+VS − 0.12
+VS − 0.13
+VS − 0.25
+VS – 1.4
+VS − 0.15
+VS − 0.2
−VS + 0.2
−VS + 0.25
−VS + 0.12
−VS + 0.13
−VS + 0.25
−VS + 0.3
−VS + 0.15
−VS + 0.2
+VS − 0.2
+VS − 0.25
+VS − 0.12
+VS − 0.13
+VS − 0.25
+VS – 1.4
+VS − 0.15
+VS − 0.2
20
Rev. 0 | Page 4 of 24
20
V
V
V
V
V
V
V
V
mA
Data Sheet
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance
Operating Range 6
AD8422
Test Conditions/
Comments
Dual-supply operation
Single-supply
operation
Min
AD8422ARZ
Typ
Max
Min
AD8422BRZ
Typ
Max
±1.8
3.6
±18
36
±1.8
3.6
±18
36
V
V
330
400
µA
µA
+85
+125
°C
°C
300
T = −40°C to +85°C
–40
–40
330
400
+85
+125
300
–40
–40
Unit
Total RTI noise = √eNI2 + (eNO/G)2
Total RTI VOS = (VOSI) + (VOSO/G).
3
Gain does not include the effects of the external resistor, RG.
4
One input grounded. G = 1.
5
Output current limited at cold temperatures. See Figure 35.
6
See Typical Performance Characteristics for expected operation between 85°C and 125°C.
1
2
MSOP PACKAGE
VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2.
Parameter
COMMON-MODE REJECTION RATIO
CMRR DC to 60 Hz with 1 kΩ
Source Imbalance
G=1
G = 10
G = 100
G = 1000
Over Temperature, G = 1
CMRR at 7 kHz
G=1
G = 10
G = 100
G = 1000
NOISE 1
Voltage Noise, 1 kHz
Input Voltage Noise, eNI
Output Voltage Noise, eNO
Peak to Peak, RTI
G=1
G = 10
G = 100 to 1000
Current Noise
VOLTAGE OFFSET 2
Input Offset, VOSI
Over Temperature
Average Temperature
Coefficient
Output Offset, VOSO
Over Temperature
Average Temperature
Coefficient
Test Conditions/
Comments
Min
AD8422ARMZ
Typ
Max
Min
AD8422BRMZ
Typ
Max
Unit
VCM = −10 V to +10 V
T = −40°C to +85°C
VCM = −10 V to +10 V
86
106
126
146
83
90
110
130
150
86
dB
dB
dB
dB
80
90
100
100
80
95
100
100
dB
dB
dB
dB
VIN+, VIN−, VREF = 0 V
8
80
8
80
nV/√Hz
nV/√Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
2
0.5
0.15
90
8
2
0.5
0.15
90
8
110
µV p-p
µV p-p
µV p-p
fA/√Hz
pA p-p
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
70
110
0.6
50
75
0.4
µV
µV
µV/°C
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
300
500
5
150
300
2
µV
µV
µV/°C
Rev. 0 | Page 5 of 24
AD8422
Parameter
Offset RTI vs. Supply (PSR)
G=1
G = 10
G = 100
G = 1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average Temperature
Coefficient
Input Offset Current
Over Temperature
Average Temperature
Coefficient
REFERENCE INPUT
RIN
IIN
Voltage Range
Gain to Output
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G=1
G = 10
G = 100
G = 1000
Settling Time 0.01%
G=1
G = 10
G = 100
G = 1000
Settling Time 0.001%
G=1
G = 10
G = 100
G = 1000
Slew Rate
GAIN 3
Gain Range
Gain Error
G=1
G = 10
G = 100
G = 1000
Gain Nonlinearity
G=1
G = 10
G = 100
G = 1000
Gain vs. Temperature
G=1
G>1
Data Sheet
Test Conditions/
Comments
VS = ±1.8 V to ±18 V
Min
90
110
124
130
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
AD8422ARMZ
Typ
Max
110
130
150
150
0.5
Min
100
120
140
140
1
2
0.2
0.3
0.8
0.1
20
35
0.5
1
nA
nA
pA/°C
0.15
0.3
nA
nA
pA/°C
1
1
1
kΩ
µA
V
V/V
2200
850
120
12
2200
850
120
12
kHz
kHz
kHz
kHz
13
13
12
80
13
13
12
80
µs
µs
µs
µs
15
15
15
160
15
15
15
160
µs
µs
µs
µs
V/µs
−VS
50
+VS
20
35
Unit
dB
dB
dB
dB
4
1
VIN+, VIN−, VREF = 0 V
120
140
160
160
0.2
4
VS = ±1.8 V to ±15 V
T = −40°C to +85°C
AD8422BRMZ
Typ
Max
−VS
50
+VS
10 V step
10 V step
G = 1 to 100
G = 1 + (19.8 kΩ/RG)
0.8
0.8
1
1000
1
1000
V/V
0.01
0.04
0.04
0.04
%
%
%
%
5
5
10
20
ppm
ppm
ppm
ppm
1
−80
ppm/°C
ppm/°C
VOUT ± 10 V
0.03
0.2
0.2
0.2
VOUT = −10 V to +10 V
RL = 2 kΩ
0.5
2
4
10
5
5
10
20
5
−80
Rev. 0 | Page 6 of 24
0.5
2
4
10
Data Sheet
Parameter
INPUT
Input Impedance
Differential
Common Mode
Input Operating Voltage Range 4
Over Temperature
OUTPUT
Output Swing, RL = 10 kΩ
Over Temperature
Output Swing, RL = 10 kΩ
Over Temperature
Output Swing, RL = 2 kΩ
Over Temperature 5
Output Swing, RL = 2 kΩ
Over Temperature
Short-Circuit Current
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
Specified Performance
Operating Range 6
AD8422
Test Conditions/
Comments
Min
AD8422ARMZ
Typ
Max
Min
200||2
200||2
AD8422BRMZ
Typ
Max
200||2
200||2
Unit
GΩ||pF
GΩ||pF
VS = ±1.8 V to ±18 V
T = −40°C to +85°C
−VS + 1.2
−VS + 1.2
+VS − 1.1
+VS − 1.2
−VS + 1.2
−VS + 1.2
+VS − 1.1
+VS − 1.2
V
V
VS = ±15 V
T = −40°C to +85°C
VS = ±1.8 V
T = −40°C to +85°C
VS = ±15 V
T = −40°C to +85°C
VS = ±1.8 V
T = −40°C to +85°C
−VS + 0.2
−VS + 0.25
−VS + 0.12
−VS + 0.13
−VS + 0.25
−VS + 0.3
−VS + 0.15
−VS + 0.2
+VS − 0.2
+VS − 0.25
+VS − 0.12
+VS − 0.13
+VS − 0.25
+VS – 1.4
+VS − 0.15
+VS − 0.2
−VS + 0.2
−VS + 0.25
−VS + 0.12
−VS + 0.13
−VS + 0.25
−VS + 0.3
−VS + 0.15
−VS + 0.2
+VS − 0.2
+VS − 0.25
+VS − 0.12
+VS − 0.13
+VS − 0.25
+VS – 1.4
+VS − 0.15
+VS − 0.2
V
V
V
V
V
V
V
V
mA
±18
36
330
400
V
V
µA
µA
+85
+125
°C
°C
20
Dual-supply operation
Single-supply operation
±1.8
3.6
300
T = −40°C to +85°C
–40
–40
Total RTI Noise = √eNI2 + (eNO/G)2
Total RTI VOS = (VOSI) + (VOSO/G).
3
Gain does not include the effects of the external resistor, RG.
4
One input grounded. G = 1.
5
Output current limited at cold temperatures. See Figure 35.
6
See Typical Performance Characteristics for expected operation between 85°C and 125°C.
1
2
Rev. 0 | Page 7 of 24
20
±18
36
330
400
±1.8
3.6
+85
+125
–40
–40
300
AD8422
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Output Short-Circuit Current Duration
Maximum Voltage at −IN or +IN1
Minimum Voltage at −IN or +IN
Maximum Voltage at REF
Storage Temperature Range
Operating Temperature Range
Maximum Junction Temperature
ESD
Human Body Model
Charge Device Model
Machine Model
1
θJA is specified for a device in free air using a 4-layer JEDEC
printed circuit board (PCB).
Rating
±1.8 V to ±18 V
Indefinite
−VS + 40 V
+VS − 40 V
±VS ± 0.3 V
−65°C to +150°C
−40°C to +125°C
150°C
Table 4.
Package
8-Lead SOIC
8-Lead MSOP
ESD CAUTION
3 kV
1.25 kV
100 V
For voltages beyond these limits, use input protection resistors. See the
Theory of Operation section for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 8 of 24
θJA
100
162
Unit
°C/W
°C/W
Data Sheet
AD8422
AD8422
–IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
TOP VIEW
(Not to Scale)
11197-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2, 3
4
5
6
7
8
Mnemonic
−IN
RG
+IN
−VS
REF
VOUT
+VS
Description
Negative Input Terminal.
Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (19.8 kΩ/RG).
Positive Input Terminal.
Negative Power Supply Terminal.
Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output.
Output Terminal.
Positive Power Supply Terminal.
Rev. 0 | Page 9 of 24
AD8422
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15, VREF = 0 V, RL = 10 kΩ, unless otherwise noted.
400
400
350
350
300
300
200
150
150
100
100
50
50
0
–90
–60
0
30
–30
INPUT OFFSET VOLTAGE (µV)
60
90
0
–300
–200
–100
0
200
100
300
OUTPUT OFFSET VOLTAGE (µV)
Figure 4. Typical Distribution of Input Offset Voltage
11197-006
HITS
200
11197-003
Figure 7. Typical Distribution of Output Offset Voltage
800
400
600
HITS
HITS
300
400
200
200
100
0
300
600
–600
–300
POSITIVE INPUT BIAS CURRENT (pA)
900
0
–300
11197-004
0
–900
–200
–100
0
100
200
300
INPUT OFFSET CURRENT (pA)
Figure 5. Typical Distribution of Input Bias Current
11197-007
HITS
250
250
Figure 8. Typical Distribution of Input Offset Current
500
500
400
HITS
300
200
100
100
–6
–3
3
0
PSRR G = 1 (µV/V)
6
9
0
–40
–20
0
CMRR G = 1 (µV/V)
20
Figure 9. Typical Distribution of CMRR (G = 1)
Figure 6. Typical Distribution of PSRR (G = 1)
Rev. 0 | Page 10 of 24
40
11197-008
0
–9
300
200
11197-005
HITS
400
Data Sheet
AD8422
20
20
VS = ±15V
10
5
VS = ±12V
0
–5
VS = ±5V
–10
–15
–20
–20
–15
–10
–5
0
5
10
15
20
OUTPUT VOLTAGE (V)
Figure 10. Input Common-Mode Voltage vs. Output Voltage (G = 1),
VS = ±15 V, VS = ±12 V, VS = ±5 V
10
VS = ±12V
5
0
–5
VS = ±5V
–10
–15
–20
–20
–10
–5
0
5
10
15
20
Figure 13. Input Common-Mode Voltage vs. Output Voltage (G = 100),
VS = ±15 V, VS = ±12 V, VS = ±5 V
5.0
G=1
G = 100
4.5
VREF = 2.5V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
OUTPUT VOLTAGE (V)
0
–0.5
11197-010
0
–0.5
Figure 11. Input Common-Mode Voltage vs. Output Voltage (G = 1),
Single-Supply, VS = 5 V
VREF = 2.5V
VREF = 0V
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
OUTPUT VOLTAGE (V)
11197-013
VREF = 0V
INPUT COMMON-MODE VOLTAGE (V)
4.5
0.5
Figure 14. Input Common-Mode Voltage vs. Output Voltage (G = 100),
Single-Supply, VS = 5 V
3.0
3.0
G=1
G = 100
VREF = 0V
2.5
2.0
1.5
1.0
0.5
0
–0.5
0
0.5
1.0
1.5
2.0
2.5
OUTPUT VOLTAGE (V)
3.0
3.5
4.0
Figure 12. Input Common-Mode Voltage vs. Output Voltage (G = 1),
Single-Supply, VS = 3.6 V
2.5
2.0
1.5
1.0
VREF = 0V
VREF = 1.8V
0.5
0
–0.5
0
0.5
1.0
1.5
2.0
2.5
OUTPUT VOLTAGE (V)
3.0
3.5
4.0
11197-014
INPUT COMMON-MODE VOLTAGE (V)
VREF = 1.8V
11197-011
INPUT COMMON-MODE VOLTAGE (V)
–15
OUTPUT VOLTAGE (V)
5.0
INPUT COMMON-MODE VOLTAGE (V)
VS = ±15V
15
11197-012
INPUT COMMON-MODE VOLTAGE (V)
G = 100
15
11197-009
INPUT COMMON-MODE VOLTAGE (V)
G=1
Figure 15. Input Common-Mode Voltage vs. Output Voltage (G = 100),
Single-Supply, VS = 3.6 V
Rev. 0 | Page 11 of 24
AD8422
Data Sheet
16
12
IIN
3.0
4
2.5
0
2.0
–4
1.5
–8
1.0
–12
0.5
0
5
OUTPUT VOLTAGE (V)
8
0
–35 –30 –25 –20 –15 –10 –5
IIN
5
5
0
0
–5
–5
–10
–10
–16
–15
–15
–20
–20
–25
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
20
10
VOUT
Figure 16. Input Overvoltage Performance; G = 1, VS = 5 V
–20
–20
–15
–10
0
5
10
–5
INPUT VOLTAGE (V)
15
20
25
Figure 19. Input Overvoltage Performance; G = 100, VS = ±15 V
0.25
20
VS = ±15V
VS = ±15V
G=1
VREF = 0V
VIN– = 0V
0.20
15
INPUT BIAS CURRENT (nA)
0.15
10
10
VOUT
5
5
0
0
IIN
INPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
15
10
3.5
15
20
VS = ±15V
G = 100
VREF = 0V
VIN– = 0V
15
VOUT
INPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
4.0
11197-015
4.5
20
INPUT CURRENT (mA)
VS = 5V
G=1
VREF = 2.5V
VIN– = 2.5V
11197-018
20
5.0
0.10
0.05
0
–0.05
–5
–5
–10
–10
–15
–15
–0.20
–20
–0.25
–15
–0.10
–15
–10
0
5
10
–5
INPUT VOLTAGE (V)
15
20
25
0.20
16
0.15
VOUT
INPUT BIAS CURRENT (nA)
12
IIN
3.5
8
3.0
4
2.5
0
2.0
–4
1.5
–8
1.0
–12
0.5
–16
0
–35 –30 –25 –20 –15 –10 –5
–20
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
0
5
10
15
VS = 5V
INPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
4.0
20
0.10
0.05
0
–0.05
–0.10
–0.15
11197-017
4.5
VS = 5V
G = 100
VREF = 2.5V
VIN– = 2.5V
–5
COMMON-MODE VOLTAGE (V)
Figure 20. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V
Figure 17. Input Overvoltage Performance; G = 1, VS = ±15 V
5.0
–10
11197-019
–20
Figure 18. Input Overvoltage Performance; G = 100, VS = 5 V
–0.20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
COMMON-MODE VOLTAGE (V)
Figure 21. Input Bias Current vs. Common-Mode Voltage, VS = 5 V
Rev. 0 | Page 12 of 24
11197-020
–20
–25
11197-016
–0.15
Data Sheet
AD8422
180
180
GAIN = 1000
160
GAIN = 10
GAIN = 100
140
120
GAIN = 1
CMRR (dB)
POSITIVE PSRR (dB)
140
GAIN = 1000
160
GAIN = 100
100
80
GAIN = 10
120
GAIN = 1
100
60
80
40
1
10
100
1k
FREQUENCY (Hz)
10k
100k
40
0.1
11197-021
0
0.1
1
Figure 22. Positive PSRR vs. Frequency
10k
100k
10k
100k
180
GAIN = 1000
GAIN = 1000
160
GAIN = 100
GAIN = 100
140
GAIN = 10
140
120
GAIN = 1
CMRR (dB)
NEGATIVE PSRR (dB)
100
1k
FREQUENCY (Hz)
Figure 25. CMRR vs. Frequency
180
160
10
11197-024
60
20
100
80
120
GAIN = 10
100
GAIN = 1
60
80
40
1
10
100
1k
FREQUENCY (Hz)
10k
100k
40
0.1
11197-022
0
0.1
Figure 23. Negative PSRR vs. Frequency
10
0
GAIN = 1
–10
–20
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 24. Gain vs. Frequency
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
10
20
30
40
50
60
70
80
90
100
TIME (s)
Figure 27. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time
Rev. 0 | Page 13 of 24
11197-026
CHANGE IN INPUT OFFSET VOLTAGE (µV)
GAIN = 10
11197-023
GAIN (dB)
GAIN = 100
30
20
100
1k
FREQUENCY (Hz)
0.5
GAIN = 1000
50
40
10
Figure 26. CMRR vs. Frequency, 1 kΩ Source Imbalance
70
60
1
11197-025
60
20
AD8422
Data Sheet
0.4
VS = ±15V
NORMALIZED AT 25°C
0.5
0.1
0
0
–0.5
–0.1
–1.0
–0.2
–1.5
–0.3
–25
–10
5
20
35
50
65
80
95
110
0.40
SUPPLY CURRENT (mA)
0.2
INPUT OFFSET CURRENT (nA)
1.0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
–0.4
125
TEMPERATURE (°C)
0
–40
50
65
80
95
110
125
0
–20
–40
ISHORT +
50
40
30
20
10
0
–10
ISHORT –
–20
–80
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–30
–40
11197-028
–25
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
125
11197-031
SHORT-CIRCUIT CURRENT (mA)
GAIN ERROR (µV/V)
20
–60
Figure 32. Short-Circuit Current vs. Temperature (G = 1)
Figure 29. Gain vs. Temperature (G = 1)
+VS
50
INPUT VOLTAGE (V)
REFERRED TO SUPPLY VOLTAGES
REPRESENTATIVE SAMPLE
NORMALIZED AT 25°C
30
20
10
0
–10
–20
–30
–40
–25
–10
5
20
35
50
65
TEMPERATURE (°C)
80
95
110
125
11197-029
CMRR (µV/V)
35
60
40
–50
–40
20
70
REPRESENTATIVE SAMPLES
NORMALIZED AT 25°C
60
40
5
Figure 31. Supply Current vs. Temperature (G = 1)
100
–100
–40
–10
TEMPERATURE (°C)
Figure 28. Input Bias Current and Input Offset Current vs. Temperature
80
–25
–0.5
–1.0
–40°C
+25°C
+85°C
+105°C
+125°C
–1.5
+1.5
+1.0
+0.5
–VS
0
2
4
6
8
10
12
14
SUPPLY VOLTAGE (±VS)
Figure 33. Input Voltage Limit vs. Supply Voltage
Figure 30. CMRR vs. Temperature (G = 1), Normalized at 25°C
Rev. 0 | Page 14 of 24
16
18
11197-034
–2.0
–40
0.45
0.3
11197-027
INPUT BIAS CURRENT (nA)
1.5
0.50
11197-030
2.0
Data Sheet
AD8422
+VS
–0.2
–0.1
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–0.2
–0.3
+125°C
+85°C
+25°C
–40°C
+0.3
+0.2
+0.1
–0.6
+0.8
+0.6
+0.4
4
6
8
10
12
14
16
18
–VS
100µ
–0.2
4
–0.4
3
GAIN NONLINEARITY (ppm)
5
–0.6
+125°C
+85°C
+25°C
–40°C
+0.8
+0.6
1
0
–1
–2
–3
+0.2
–4
2
4
6
8
10
12
14
16
18
SUPPLY VOLTAGE (±VS)
VS = ±15V
G=1
2
+0.4
–5
–10
11197-036
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
+VS
0
RL = 2kΩ
RL = 10kΩ
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
Figure 38. Gain Nonlinearity (G = 1)
Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ
10
15
8
GAIN NONLINEARITY (ppm)
10
5
–40°C
+25°C
+85°C
+105°C
+125°C
0
–5
VS = ±15V
G = 10
6
4
2
0
–2
–4
–6
–10
RL = 2kΩ
RL = 10kΩ
–8
–15
100
1k
10k
LOAD RESISTANCE (Ω)
100k
11197-037
OUTPUT VOLTAGE SWING (V)
10m
Figure 37. Output Voltage Swing vs. Output Current
Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
–0.8
1m
OUTPUT CURRENT (A)
11197-038
2
11197-039
0
SUPPLY VOLTAGE (±VS)
–VS
–40°C
+25°C
+85°C
+105°C
+125°C
–0.8
+0.2
11197-035
–VS
–0.4
–10
–10
–8
–6
–4
–2
0
2
4
6
OUTPUT VOLTAGE (V)
Figure 39. Gain Nonlinearity (G = 10)
Figure 36. Output Voltage Swing vs. Load Resistance
Rev. 0 | Page 15 of 24
8
10
11197-040
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
+VS
AD8422
Data Sheet
20
G = 1000, 100nV/DIV
VS = ±15V
G = 100
16
NONLINEARITY (ppm)
12
8
4
0
G = 1, 1µV/DIV
–4
–8
RL = 2kΩ
RL = 10kΩ
–20
–10
–8
–6
–4
–2
0
2
4
6
8
1s/DIV
10
OUTPUT VOLTAGE (V)
11197-041
–16
11197-044
–12
Figure 40. Gain Nonlinearity (G = 100)
Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000)
50
10k
VS = ±15V
G = 1000
40
CURRENT NOISE (fA/√Hz)
NONLINEARITY (ppm)
30
20
10
0
–10
–20
1k
100
–30
–8
–6
–4
–2
0
2
4
6
8
10
OUTPUT VOLTAGE (V)
10
11197-042
–50
–10
1
Figure 41. Gain Nonlinearity (G = 1000)
10
100
FREQUENCY (Hz)
1k
10k
Figure 44. Current Noise Spectral Density vs. Frequency
G=1
100
5pA/DIV
G = 10
G = 100
10
1
0.1
1
10
100
1k
10k
100k
1s/DIV
FREQUENCY (Hz)
Figure 45. 0.1 Hz to 10 Hz Current Noise
Figure 42. Voltage Noise Spectral Density vs. Frequency
Rev. 0 | Page 16 of 24
11197-046
G = 1000
11197-043
VOLTAGE NOISE RTI (nV/√Hz)
1k
11197-045
RL = 2kΩ
RL = 10kΩ
–40
Data Sheet
AD8422
30
G=1
VS = ±15V
5V/DIV
20
15
12.0μs TO 0.01%
15.2µs TO 0.001%
10
0.002%/DIV
5
VS = +5V
11197-050
OUTPUT VOLTAGE (V p-p)
25
10k
FREQUENCY (Hz)
100k
1M
Figure 49. Large Signal Pulse Response and Settling Time (G = 100),
10 V Step, VS = ±15 V, RL = 2 kΩ, CL = 100 pF
Figure 46. Large Signal Frequency Response
5V/DIV
5V/DIV
80μs TO 0.01%
160µs TO 0.001%
13.6μs TO 0.01%
15.2µs TO 0.001%
0.002%/DIV
10μs/DIV
11197-048
0.002%/DIV
11197-051
1k
11197-047
10μs/DIV
0
100
100μs/DIV
Figure 47. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step,
VS = ±15 V, RL = 2 kΩ, CL = 100 pF
Figure 50. Large Signal Pulse Response and Settling Time (G = 1000),
10 V Step, VS = ±15 V, RL = 2 kΩ, CL = 100 pF
30
RL = 2kΩ
CL = 100pF
25
SETTLING TIME (µs)
5V/DIV
12.8μs TO 0.01%
15.1µs TO 0.001%
0.002%/DIV
20
SETTLED TO 0.001%
15
10
SETTLED TO 0.01%
0
2
4
6
8
10
12
14
16
STEP SIZE (V)
Figure 48. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step,
VS = ±15 V, RL = 2 kΩ, CL = 100 pF
Rev. 0 | Page 17 of 24
Figure 51. Settling Time vs. Step Size (G = 1)
18
20
11197-052
10μs/DIV
11197-049
5
AD8422
Data Sheet
50mV/DIV
11197-056
10µs/DIV
11197-053
20mV/DIV
100µs/DIV
Figure 52. Small Signal Pulse Response (G = 1), RL = 2 kΩ, CL = 100 pF
Figure 55. Small Signal Pulse Response (G = 1000), RL = 2 kΩ, CL = 100 pF
NO LOAD
20 pF
50 pF
100 pF
50mV/DIV
Figure 53. Small Signal Pulse Response (G = 10), RL = 2 kΩ, CL = 100 pF
Figure 56. Small Signal Pulse Response with Various Capacitive Loads
(G = 1), RL = No Load
11197-055
20mV/DIV
10µs/DIV
10µs/DIV
11197-057
10µs/DIV
11197-054
20mV/DIV
Figure 54. Small Signal Pulse Response (G = 100), RL = 2 kΩ, CL = 100 pF
Rev. 0 | Page 18 of 24
Data Sheet
AD8422
THEORY OF OPERATION
+VS
VB
I
IB
COMPENSATION
A1
IB
COMPENSATION
A2
C1
10kΩ
+VS
C2
10kΩ
NODE 1
–IN
ESD AND
OVERVOLTAGE
PROTECTION
R1
Q1 9.9kΩ
superβ
10kΩ
R2
9.9kΩ
+VS
+VS
RG
NODE 3
–VS
OUTPUT
A3
NODE 2
Q2
superβ
ESD AND
OVERVOLTAGE
PROTECTION
NODE 4
+VS
–VS
10kΩ
REF
+IN
–VS
–VS
11197-058
I
DIFFERENCE
AMPLIFIER STAGE
Figure 57. Simplified Schematic
ARCHITECTURE
The transfer function of the AD8422 is
The AD8422 is based on the classic 3-op-amp instrumentation
amplifier topology. This topology has two stages: a preamplifier
to provide differential amplification followed by a difference
amplifier that removes the common-mode voltage. Figure 57
shows a simplified schematic of the AD8422.
Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as
precision current feedback amplifiers that maintain a fixed
current in the emitters of Q1 and Q2. Any change in the input
signal forces the output voltages of A1 and A2 to change accordingly and maintain the Q1 and Q2 current at the correct value.
This causes a precise diode drop from –IN and +IN to Node 3
and Node 4, respectively, so that the differential signal applied
to the inputs is replicated across the RG pins. Any current
through RG must also flow through R1 and R2, creating the
gained differential voltage between Node 1 and Node 2.
The amplified differential signal and the common-mode signal
are applied to a difference amplifier that rejects the commonmode voltage but preserves the amplified differential voltage.
Laser-trimmed resistors allow for a highly accurate in-amp with a
gain error of less than 0.01% and a CMRR that exceeds 94 dB
(G = 1). The supply current is precisely trimmed to reduce
uncertainties due to part-to-part variations in power dissipation
and noise. The high performance pinout and special attention to
design and layout allow for high CMRR across a wide frequency
and temperature range. Using superbeta input transistors and
bias current compensation, the AD8422 offers extremely high
input impedance and low bias current, as well as very low voltage
noise while using only 300 µA supply current. The overvoltage
protection scheme allows the input to go 40 V from the opposite
rail at all gains without compromising the noise performance.
VOUT = G × (VIN+ − VIN−) + VREF
where:
G = 1+
19.8 kΩ
RG
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8422 that can be calculated by referring to Table 6 or by
using the following gain equation:
RG =
19.8 kΩ
G −1
The AD8422 defaults to G = 1 when no gain resistor is used. Add
the tolerance and gain drift of the RG resistor to the specifications
of the AD8422 to determine the total gain accuracy of the system.
When the gain resistor is not used, gain error and gain drift are
minimal.
Table 6. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
Calculated Gain
19.6 k
4.99 k
2.21 k
1.05 k
402
200
100
39.2
20
2.010
4.968
9.959
19.86
50.25
100.0
199.0
506.1
991.0
Rev. 0 | Page 19 of 24
AD8422
Data Sheet
RG Power Dissipation
–IN
1
RG
8
+VS
2
7
VOUT
RG
3
6
REF
+IN
4
5
–VS
REFERENCE TERMINAL
The output voltage of the AD8422 is developed with respect to the
potential on the reference terminal. This can be used to apply a
precise offset to the output signal. For example, a voltage source
can be tied to the REF pin to level shift the output, allowing the
AD8422 to drive a unipolar analog-to-digital converter (ADC).
The REF pin is protected with ESD diodes and must not exceed
either +VS or −VS by more than 0.3 V.
For best performance, maintain a source impedance to the REF
terminal that is below 1 Ω. As shown in Figure 57, the reference
terminal, REF, is at one end of a 10 kΩ resistor. Additional impedance
at the REF terminal adds to this 10 kΩ resistor and results in
amplification of the signal connected to the positive input.
The amplification from the additional RREF can be calculated as
2(10 kΩ + RREF)/(20 kΩ + RREF)
Only the positive signal path is amplified; the negative path is
unaffected. This uneven amplification degrades CMRR.
CORRECT
AD8422
REF
Common-Mode Rejection Ratio over Frequency
Poor layout can cause some of the common-mode signals to be
converted to differential signals before reaching the in-amp.
Such conversions occur when one input path has a frequency
response that is different from the other. To maintain high
CMRR over frequency, closely match the input source impedance and capacitance of each path. Place additional source
resistance in the input path (for example, for input protection)
close to the in-amp inputs, which minimizes their interaction
with parasitic capacitance from the PCB traces.
Parasitic capacitance at the gain setting pins (RG) can also affect
CMRR over frequency. If the board design has a component at
the gain setting pins (for example, a switch or jumper), choose a
component such that the parasitic capacitance is as small as
possible.
Use a stable dc voltage to power the instrumentation amplifier.
Noise on the supply pins can adversely affect performance.
REF
V
+
11197-059
OP1177
–
Figure 59. Pinout Diagram
Power Supplies and Grounding
AD8422
V
TOP VIEW
(Not to Scale)
Figure 58. Driving the Reference Pin (REF)
INPUT VOLTAGE RANGE
The 3-op-amp architecture of the AD8422 applies gain in the
first stage before removing common-mode voltage with the
difference amplifier stage. Internal nodes between the first and
second stages (Node 1 and Node 2 in Figure 57) experience a
combination of a gained signal, a common-mode signal, and a
diode drop. The voltage supplies can limit the combined signal,
even when the individual input and output signals are not limited.
Figure 10 through Figure 15 show this limitation in detail.
Place a 0.1 μF capacitor as close as possible to each supply pin.
Because the length of the bypass capacitor leads is critical at
high frequency, surface-mount capacitors are recommended. A
parasitic inductance in the bypass ground trace works against
the low impedance created by the bypass capacitor. As shown in
Figure 60, a 10 μF capacitor can be used farther away from the
device. For larger value capacitors, intended to be effective at
lower frequencies, the current return path distance is less critical.
In most cases, this capacitor can be shared by other local precision
integrated circuits.
+VS
0.1µF
10µF
+IN
RG
VOUT
AD8422
LOAD
LAYOUT
REF
–IN
To ensure optimum performance of the AD8422 at the PCB level,
take care in the design of the board layout. To aid in this task,
the pins of the AD8422 are arranged in a logical manner.
0.1µF
–VS
10µF
11197-061
INCORRECT
AD8422
11197-060
The AD8422 duplicates the differential voltage across its inputs
onto the RG resistor. Choose an RG resistor size that is sufficient
to handle the expected power dissipation at ambient temperature.
Figure 60. Supply Decoupling, REF, and Output Referred to Local Ground
Rev. 0 | Page 20 of 24
Data Sheet
AD8422
A ground plane layer is helpful to reduce parasitic inductances.
This minimizes voltage drops with changes in current. The area
of the current path is directly proportional to the magnitude of
parasitic inductances and, therefore, the impedance of the path
at high frequencies. Large changes in currents in an inductive
decoupling path or ground return create unwanted effects due
to the coupling of such changes into the amplifier inputs.
INPUT VOLTAGES BEYOND THE SUPPLY RAILS
Many instrumentation amplifiers specify excellent CMRR and
input impedance, but in a real system, the performance suffers
because of the external components required for input protection.
The AD8422 has very robust inputs. It typically does not need
additional input protection. Input voltages can be up to 40 V from
the opposite supply rail without damage to the part. For example,
with a +5 V positive supply and a 0 V negative supply, the part can
safely withstand voltages from −35 V to +40 V. Unlike some other
instrumentation amplifiers, the part can handle large differential
input voltages even when the part is in high gain.
Because load currents flow from the supplies, connect the load at
the same physical location as the bypass capacitor grounds.
Reference Pin
The output voltage of the AD8422 is developed with respect to
the potential on the reference terminal. Ensure that REF is tied
to the appropriate local ground.
+VS
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8422 must have a dc return
path to ground. When using a floating source without a current
return path, such as a thermocouple, create a current return
path, as shown in Figure 61.
INCORRECT
+
VIN+
–
For input voltages less than 40 V from the opposite rail, no input
protection is required.
Keep the rest of the AD8422 terminals within the supplies. All
terminals of the AD8422 are protected against ESD.
AD8422
REF
Input Voltages Beyond the Maximum Ratings
REF
–VS
For applications where the AD8422 encounters voltages beyond
the limits in the Absolute Maximum Ratings section, external
protection is required. This external protection depends on the
duration of the overvoltage event and the noise performance
required.
–VS
TRANSFORMER
TRANSFORMER
+VS
–VS
MOST APPLICATIONS
+VS
AD8422
AD8422
Figure 62. Input Overvoltage Protection with no External Components
CORRECT
+VS
I
11197-063
+
VIN+
–
+VS
For short-lived events, transient protectors such as metal oxide
varistors (MOVs) may be all that is required.
AD8422
For longer events, use resistors in series with the inputs combined
with diodes. To avoid worsening bias current performance, low
leakage diodes, such as the BAV199 or FJH1100s, are recommended.
The diodes prevent the voltage at the input of the amplifier from
exceeding the maximum ratings, while the resistors limit the
current into the diodes. Because most external diodes can easily
handle 100 mA or more, resistor values do not have to be large.
Therefore, the protection resistance has minimal impact on
noise performance.
AD8422
REF
REF
10MΩ
–VS
–VS
THERMOCOUPLE
THERMOCOUPLE
+VS
+VS
C
C
C
R
1
fHIGH-PASS = 2πRC
AD8422
REF
AD8422
C
REF
–VS
CAPACITIVELY COUPLED
–VS
CAPACITIVELY COUPLED
11197-062
R
Figure 61. Creating an Input Bias Current Return Path
Rev. 0 | Page 21 of 24
AD8422
Data Sheet
+
+
I
VIN+
–
RPROTECT
AD8422
+VS
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications that have strong RF signals. The disturbance can
appear as a small dc offset voltage. High frequency signals can
be filtered with a low-pass RC network placed at the input of
the instrumentation amplifier, as shown in Figure 64.
I
VIN+
–
AD8422
RPROTECT
VIN–
–
–VS
TRANSIENT PROTECTION
RPROTECT
+
VIN+
–
+VS
I
AD8422
RPROTECT
+
VIN–
–
+
–VS
VIN–
–
+VS
SIMPLE CONTINUOUS PROTECTION
+VS
RPROTECT
+
VIN+
–
0.1µF
+VS
–VS
+VS
R
AD8422
LOW NOISE CONTINUOUS
OPTION 1
+
VIN–
–
–VS
+IN
2kΩ
CD
10nF
RPROTECT
–VS
REF
–IN
2kΩ
CC
1nF
0.1µF
Figure 63. Input Protection Options for Input Voltages Beyond Absolute
Maximum Ratings
At the expense of some noise performance, another solution is
to use series resistors. In the overvoltage case, current into the
inputs of the AD8422 is internally limited to a safe value for the
amplifier. Although the AD8422 inputs must still be kept within the
Absolute Maximum Ratings, the I × R drop across the
protection resistor increases the maximum voltage that the
system can withstand to the following values:
For positive input signals,
VMAX_NEW = (40 V + Negative Supply) + IIN × RPROTECT
For negative input signals,
VMIN_NEW = (Positive Supply – 40 V) − IOUT × RPROTECT
Overvoltage performance is shown in Figure 16, Figure 17,
Figure 18, and Figure 19. With gains greater than 100 and
supply voltages less than ±2.5 V, overdrive voltages beyond
the rails may cause the output to invert as far as the REF pin
voltage.
VOUT
AD8422
RG
R
–VS
LOW NOISE CONTINUOUS
OPTION 2
10µF
CC
1nF
I
11197-064
+
10µF
–VS
11197-065
+VS
Figure 64. RFI Suppression
The filter limits the input signal bandwidth, according to the
following relationship:
FilterFrequency DIFF 
FilterFrequencyCM 
1
2πR(2C D  CC )
1
2πRCC
where CD ≥ 10 CC.
CD affects the difference signal, and CC affects the common-mode
signal. Choose values of R and CC that minimize RFI. A mismatch
between R × CC at the positive input and R × CC at the negative
input degrades the CMRR of the AD8422. By using a value of CD
that is one order of magnitude larger than CC, the effect of the
mismatch is reduced, and performance is improved.
Resistors add noise; therefore, the choice of the resistor and capacitor
values depends on the desired tradeoff between noise, input
impedance at high frequencies, and RF immunity. The resistors
used for the RFI filter can be the same as those used for input
protection.
Rev. 0 | Page 22 of 24
Data Sheet
AD8422
APPLICATIONS INFORMATION
ADA4096-2, ensure that the desired output voltage of the AD8276
is within its output range, and VL is within the input and output
range of the ADA4096-2. The transistor must have sufficient
breakdown voltage and IC. Low cost transistors, such as the BC847
or 2N5210, are recommended.
PRECISION BRIDGE CONDITIONING
With its high CMRR, low drift, and rail-to-rail output, the
AD8422 is an excellent choice for conditioning a signal from a
Wheatstone bridge. With appropriate supply voltages, the gain
and reference pin voltage can be adjusted to match the full-scale
bridge output to any desired output range, such as 0 V to 5 V.
Figure 65 shows a circuit to convert a bridge signal into a 4 mA
to 20 mA output using the AD8276 low power, precision difference
amplifier, and the ADA4096-2 low power, rail-to-rail input and
output, overvoltage protected op amp. With high precision bridge
circuits, care must be taken to compensate offsets and temperature
errors. For example, if the voltage at the REF pin is used to
compensate for the bridge offset, ensure that the AD8422 is within
its operating range for the maximum expected offset. If the zeroadjust potentiometer is excluded, connect the positive op amp
input to the center of the 24.9 kΩ, 10.7 kΩ divider, which is at
1.5 V. If lower supply voltages are used for the AD8276 and the
PROCESS CONTROL ANALOG INPUT
In process control systems such as programmable logic controllers
(PLC) and distributed control systems (DCS), analog variables
typically occur in just a few standard voltage or current ranges,
including 4 mA to 20 mA and ±10 V. Variables within these input
ranges must often be gained or attenuated and level shifted to
match a specific ADC input range such as 0 V to 5 V. The circuit in
Figure 66 shows one way this can be done with a single AD8422.
Low power, overvoltage protection, and high precision make the
AD8422 a good match for process control applications, and high
input impedance, low bias current, and low current noise allow
significant source resistance with minimum additional errors.
+5V
+5V
+IN
VOUT_FS = ±15mV
RG
+24V
AD8422
+5V
REF
–IN
AD8276
24.9kΩ
+24V
RG = 301Ω
G = 66.8V/V
SENSE
+IN
V = 0.5V TO 2.5V
+24V
VOUT
REF
–IN
+24V
1
124Ω
IOUT = 4mA TO 20mA
VL
10.7kΩ
ADA4096-2
RL
11197-066
ADA4096-2
1OPTIONAL
ZERO
ADJUST
Figure 65. Bridge Circuit with 4 mA to 20 mA Output
TERMINAL
BLOCK
0V TO 10V, ±10V
42.2kΩ
0V TO 5V, ±5V
34kΩ
8.45kΩ
49.9kΩ
+IN
RG
VOUT = 2.5V ±2.5V
AD8422
1kΩ
–IN
REF
2.5V
–15V
RG = 13.2kΩ
G = 2.5V/V
Figure 66. Process Control Analog Input
Rev. 0 | Page 23 of 24
11197-067
4mA TO 20mA,
0mA TO 20mA
±20mA
+15V
1kΩ
0V TO 1V, ±1V
AD8422
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 67. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
Figure 68. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8422ARZ
AD8422ARZ-R7
AD8422ARZ-RL
AD8422BRZ
AD8422BRZ-R7
AD8422BRZ-RL
AD8422ARMZ
AD8422ARMZ-R7
AD8422ARMZ-RL
AD8422BRMZ
AD8422BRMZ-R7
AD8422BRMZ-RL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead SOIC_N, Standard Grade
8-Lead SOIC_N, Standard Grade, 7” Tape and Reel,
8-Lead SOIC_N, Standard Grade, 13” Tape and Reel
8-Lead SOIC_N, High Performance Grade
8-Lead SOIC_N, High Performance Grade, 7” Tape and Reel
8-Lead SOIC_N, High Performance Grade, 13” Tape and Reel
8-Lead MSOP, Standard Grade
8-Lead MSOP, Standard Grade, 7” Tape and Reel,
8-Lead MSOP, Standard Grade, 13” Tape and Reel
8-Lead MSOP, High Performance Grade
8-Lead MSOP, High Performance Grade, 7” Tape and Reel
8-Lead MSOP, High Performance Grade, 13” Tape and Reel
Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11197-0-5/13(0)
Rev. 0 | Page 24 of 24
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
Y4U
Y4U
Y4U
Y4V
Y4V
Y4V