Revised August 1999 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description Features The 74F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading. ■ Serial-to-parallel converter ■ 16-Bit serial I/O shift register ■ 16-Bit parallel out storage register ■ Recirculating parallel transfer ■ Expandable for longer words ■ Slim 24 lead package ■ 74F675A version prevents false clocking through CS or R/W inputs Ordering Code: Order Number 74F675ASC Package Number M24B Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F675APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide 74F675ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram © 1999 Fairchild Semiconductor Corporation DS009587 www.fairchildsemi.com 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register April 1988 74F675A Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL SI Serial Data Input 1.0/1.0 20 µA/−0.6 mA CS Chip Select Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA SHCP Shift Clock Pulse Input (Active Falling Edge) 1.0/1.0 20 µA/−0.6 mA STCP Store Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA R/W Read/Write Input 1.0/1.0 20 µA/−0.6 mA SO Serial Data Output 50/33.3 −1 mA/20 mA Q0–Q15 Parallel Data Outputs 50/33.3 −1 mA/20 mA Functional Description The 16-Bit shift register operates in one of four modes, as determined by the signals applied to the Chip Select (CS), Read/Write (R/W) and Store Clock Pulse (STCP) input. State changes are indicated by the falling edge of the Shift Clock Pulse (SHCP). In the Shift Right mode, data enters D0 from the Serial Input (SI) pin and exits from Q15 via the Serial Data Output (SO) pin. In the Parallel Load mode, data from the storage register outputs enter the shift register and serial shifting is inhibited. The storage register is in the Hold mode when either CS or R/W is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register on the rising edge of STCP. Shift Register Operations Table Storage Register Operations Table Control Inputs CS R/W H X L L L H L H Operating SHCP STCP X To prevent false clocking of the shift register, SHCP should be in the LOW state during a LOW-to-HIGH transition of CS. To prevent false clocking of the storage register, STCP should be LOW during a HIGH-to-LOW transition of CS if R/W is LOW, and should also be LOW during a HIGH-toLOW transition of R/W if CS is LOW. Inputs Operating CS R/W STCP Hold H X X Hold X Shift Right L H Shift Right L L H Parallel Load, Hold L X Mode H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW Transition = LOW-to-HIGH Transition No Shifting X Mode Parallel Load Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V −150 mA Max VOUT = 0V VOL Output LOW Voltage IIH 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage Voltage 2.0 Units VIH 10% VCC Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded IIL Input LOW Current IOS Output Short-Circuit Current ICCH Power Supply Current 106 160 mA Max VO = HIGH ICCL Power Supply Current 106 160 mA Max VO = LOW −60 3 www.fairchildsemi.com 74F675A Absolute Maximum Ratings(Note 1) 74F675A AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 100 130 Max Min tPLH Propagation Delay 3.0 8.0 10.5 Max tPHL STCP to Qn 3.0 10.5 13.5 2.5 15.0 tPLH Propagation Delay 4.0 7.0 9.5 3.5 10.5 tPHL SHCP to SO 4.5 8.0 10.5 4.0 12.0 85 2.5 Units MHz 12.0 ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 3.5 4.0 tS(L) CS or R/W to STCP 5.5 6.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) CS or R/W to STCP 0 0 tS(H) Setup Time, HIGH or LOW 3.0 3.5 tS(L) SI to SHCP 3.0 3.5 tH(H) Hold Time, HIGH or LOW 3.0 3.5 tH(L) SI to SHCP 3.0 3.5 tS(H) Setup Time, HIGH or LOW 6.5 7.5 tS(L) R/W to SHCP 9.0 10.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) R/W to SHCP 0 0 tS(H) Setup Time, HIGH or LOW 7.0 8.0 tS(L) STCP to SHCP 7.0 8.0 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) STCP to SHCP 0 0 tS(H) Setup Time, HIGH or LOW 3.0 3.5 tS(L) CS to SHCP 3.0 3.5 tH(H) Hold Time, HIGH or LOW 3.0 3.5 3.5 tH(L) CS to SHCP 3.0 tW(H) SHCP Pulse Width 5.0 6.0 tW(L) HIGH or LOW 5.0 6.0 Units Max ns ns ns ns ns ns tW(H) STCP Pulse Width 6.0 7.0 tW(L) HIGH or LOW 5.0 6.0 tS(L) SHCP to STCP 8.0 9.0 ns tH(H) SHCP to STCP 0.0 0.0 ns www.fairchildsemi.com 4 74F675A Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A 5 www.fairchildsemi.com 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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