FAIRCHILD 74F164A_00

Revised October 2000
74F164A
Serial-In, Parallel-Out Shift Register
General Description
Features
The 74F164A is a high-speed 8-bit serial-in/parallel-out
shift register. Serial data is entered through a 2-input AND
gate synchronous with the LOW-to-HIGH transition of the
clock. The device features an asynchronous Master Reset
which clears the register, setting all outputs LOW independent of the clock. The 74F164A is a faster version of the
74F164.
■ Typical shift frequency of 90 MHz
■ Asynchronous Master Reset
■ Gated serial data input
■ Fully synchronous data transfers
■ 74F164A is a faster version of the 74F164
Ordering Code:
Order Number
Package Number
Package Description
74F164ASC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F164ASJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F164APC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS010613
www.fairchildsemi.com
74F164A Serial-In, Parallel-Out Shift Register
October 1989
74F164A
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
A, B
Data Inputs
1.0/1.0
20 µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
MR
Master Reset Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
Q0–Q7
Outputs
50/33.3
−1 mA/20 mA
Functional Description
Mode Select Table
The 74F164A is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
HIGH Enable for data entry through the other input. An
unused input must be tied HIGH.
Operating
Mode
Reset (Clear)
Shift
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Inputs
Outputs
MR
A
B
Q0
L
X
X
L
L-L
H
l
l
L
q0–q6
Q1–Q7
H
l
h
L
q0–q6
H
h
l
L
q0–q6
H
h
h
H
q0–q6
H(h) = HIGH Voltage Levels
L(l) = LOW Voltage Levels
X = Immaterial
qn = Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 1)
−0.5V to +7.0V
Input Current (Note 1)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
VCC
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
V
Min
0.5
V
Min
IOL = 20 mA
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
−0.6
mA
Max
−150
mA
Max
VOUT = 0V
55
mA
Max
CP = HIGH
Output HIGH
Voltage
VOL
Output LOW Voltage
IIH
Input HIGH
10% VCC
2.5
5% VCC
2.7
V
Conditions
Input HIGH Voltage
VOH
2.0
Units
VIH
10% VCC
Current
IBVI
Input HIGH Current
Breakdown Test
ICEX
Output HIGH
Leakage Current
VID
Input Leakage
Test
IOD
4.75
Output Leakage
Circuit Current
IIL
Input LOW Current
IOS
Output Short-Circuit Current
ICC
Power Supply Current
−60
35
Recognized as a HIGH Signal
Recognized as a LOW Signal
IIN = −18 mA
IOH = −1 mA
IOH = −1 mA
IID = 1.9 µA
All other pins grounded
VIOD = 150 mV
All other pins grounded
VIN = 0.5V
MR = GND, A, B = GND
3
www.fairchildsemi.com
74F164A
Absolute Maximum Ratings(Note 1)
74F164A
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = 5.0V
VCC = 5.0V
CL = 50 pF
CL = 50 pF
CL = 50 pF
Min
Typ
fMAX
Maximum Clock Frequency
80
120
tPLH
Propagation Delay
3.0
4.8
7.5
2.5
9.0
3.0
7.5
tPHL
CP to Qn
3.5
5.0
8.0
3.0
8.5
3.5
8.0
tPHL
Propagation Delay
5.0
7.0
10.0
4.0
12.5
5.0
10.5
MR to Qn
Max
Min
Max
60
Min
Units
Max
80
MHz
ns
ns
AC Operating Requirements
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
VCC = +5.0V
VCC = 5.0V
Min
Max
Min
Max
TA = 0°C to +70°C
VCC = 5.0V
Min
Units
Max
tS(H)
Setup Time, HIGH or LOW
4.5
5.5
4.5
tS(L)
A or B to CP
4.0
4.0
4.0
tH(H)
Hold Time, HIGH or LOW
1.0
1.0
1.0
tH(L)
A or B to CP
1.0
1.0
1.0
tW(H)
CP Pulse Width
4.0
4.0
4.0
tW(L)
HIGH or LOW
7.0
7.0
7.0
tW(L)
MR Pulse Width, LOW
4.0
5.0
4.0
ns
tREC
Recovery Time
5.0
6.5
5.0
ns
MR to CP
www.fairchildsemi.com
4
ns
ns
74F164A
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
5
www.fairchildsemi.com
74F164A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
6
74F164A Serial-In, Parallel-Out Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
7
www.fairchildsemi.com