MICROCHIP TC1307

M
TC1307
Four-Channel CMOS LDO with Select Mode, Shutdown and
Independent Reset
Features
•
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•
•
•
•
•
•
•
•
•
•
Four Independent 150 mA LDOs
Low Supply Current (220 µA typical)
High Output Voltage Accuracy (0.5% typical)
Low Dropout Voltage (100 mV typical with
150 mA load)
Four Independent Shutdown Inputs
Select Mode™: Selectable Output Voltages for
High Design Flexibility
Integrated Independent Microprocessor Reset
Low Noise Outputs
Fast Response from Shutdown (10 µs typical)
RESET Output for Low Battery Detection or Reset
Generator
Over Current and Over-Temperature Protection
Small 16-Pin QSOP Package
Specified Junction Temperature Range:
- -40°C to +125°C
Applications
•
•
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Battery Operated Systems
Potable Computers
Set Top Boxes
Load Partitioning
Medical Instruments
Cellular / GSM / PHS Phones
Instrumentation
Linear Post Regulator for SMPS
Pagers
All four LDOs have independent shutdown inputs and
can be programmed using two select inputs making the
TC1307 adaptable for a wide range of multiple output
applications. The tri-state SELECT12 input pin allows
the designer to select the output voltages on VOUT1,
and VOUT2 from three different values (2.5V, 2.8V or
3.0V). The tri-state SELECT34 input pin allows the
designer to select the output voltages on VOUT3, and
VOUT4 from three different values (1.8V, 2.5V or 2.8V).
All four LDO’s require only a 1 µF output capacitor for
stability that can be ceramic, tantalum or aluminum
over the entire input voltage operating range and 0 mA
to 150 mA rated load range. All four LDOs have low
output noise and excellent dynamic response when
faced with sudden line and load changes.
The voltage detect pin is set for a threshold of 2.63V
(typical) and operates down to a minimum input voltage
of 1.0V. When the voltage on the detect pin rises above
the 2.63V threshold, the RESET output is held low for
300 ms (typical).
Additional integrated features include over-current protection and over-temperature protection providing full
protection from external load faults.
Package Types
QSOP
VDET
1
16 RESET
SHDN1
2
15 SHDN2
SELECT12
3
14 VOUT1
Description
VIN
4
The TC1307 combines four CMOS Low Dropout Linear
Regulators with a Microcontroller Monitor in a spacesaving 16-Pin QSOP package. Developed specifically
for battery powered portable applications, all four outputs of the TC1307 typically consume a total of 220 µA
supply current, hold the output voltage to a tolerance of
0.5% and require 100 mV of headroom for regulation at
the maximum output current of 150 mA. In addition to
the four high performance LDOs, the TC1307 also
includes a voltage detector with a delayed RESET output that can be configured for low battery detection or
Microcontroller Reset Generator.
VIN
5
12 VOUT3
GND
6
11 VOUT4
SHDN3
7
10 SELECT34
VIN
8
9
 2002 Microchip Technology Inc.
13 VOUT2
TC1307
SHDN4
DS21702A-page 1
TC1307
1.0
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
VDET
Voltage Detect Input
SHDN1
VDD..............................................................................6.5V
Shutdown for VOUT1
SELECT12
Input for setting VOUT1 and VOUT2.
All inputs and outputs w.r.t. ....... ...VIN + 0.3V to -0.3V
VIN
Input Voltage Connection
Output Short Circuit Current ...... ...............continuous
VIN
Input Voltage Connection
Storage temperature.................... .... -65°C to +150°C
GND
Ground connection
SHDN3
Shutdown for V OUT3
VIN
Input Voltage Connection
1.1
Maximum Ratings*
Operating Junction Temperature,
TJ..................................................-40°C < T J < +150°C
Maximum Junction Temperature, TJ..................150°C
ESD protection on all pins...................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
SHDN4
Shutdown for V OUT4
SELECT34
Input for setting VOUT3 and VOUT4.
VOUT4
LDO4 Output
VOUT3
LDO3 Output
VOUT2
LDO2 Output
VOUT1
LDO1 Output
SHDN2
Shutdown for V OUT2
RESET
Reset Output
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all limits are established for VIN = VR+1, IL = 100 µA, C L = 3.3 µF, SHDN > VIH , TA = 25°C.
Boldface type specifications apply for junction temperatures, TJ (Note 9) of -40°C to +125°C.
Parameter
Sym
Min
Typ
Max
Units
Conditions
VIN
2.7
—
6.0
V
Input Quiescent Current
IIN
—
220
370
µA
SHDN = VIH , IL = 0
Input Shutdown Current
IIN_SHDN
—
0.1
0.5
µA
SHDN = 0V
IOUT_MAX
150
—
mA
IOUT_SC
—
—
mA
VR+2.5%
V
Input Characteristics:
Input Operating Voltage
Note 1
Output Characteristics:
Maximum Output Current
Output Short Circuit Current
(Average)
Voltage Regulation
LDO1/LDO2/LDO3/LDO4
VOUT
360
VR-2.5% VR ±0.5
V OUT = 0V
Note 2
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.7V and VIN ≥ (VR + 2.5%) + VDROPOUT.
2: VR is the nominal regulator output voltage. For example: VR = 1.8V, 2.5V, 2.8V or 3.0V.
3: TCVOUT = (V OUT-HIGH - VOUT-LOW) * 106 / (VR * ∆Temperature), VOUT-HIGH = Highest voltage measured over the temperature range. VOUT-LOW = Lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is
tested over a load range from 1mA to the maximum specified output current. Changes in output voltage due to heating
effects are determined using thermal regulation specification TCVOUT.
5: Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied.
Specifications are for a current pulse equal to ILMAX at VIN = 6.0V for t = 10 msec.
6: Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its nominal value
with a 1V differential applied.
7: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction
temperatures above 150°C can impact the device reliability.
8: VTH-MIN = 2.55V and V TH-MAX = 2.70V.
9: The Junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the Ambient temperature is not significant.
DS21702A-page 2
 2002 Microchip Technology Inc.
TC1307
Unless otherwise specified, all limits are established for VIN = VR+1, IL = 100 µA, C L = 3.3 µF, SHDN > VIH , TA = 25°C.
Boldface type specifications apply for junction temperatures, TJ (Note 9) of -40°C to +125°C.
Parameter
Sym
Min
Typ
Max
TCVOUT
—
20
40
—
∆VOUT/(VOUT x∆VIN )
—
0.05
0.2
%/V
Load Regulation
LDO1/LDO2/LDO3/LDO4
∆VOUT/VOUT
—
—
2.0
%
Thermal Regulation
LDO1/LDO2/LDO3/LDO4
∆VOUT/∆PD
—
0.04
—
V/W
Dropout Voltage
LDO1/LDO2/LDO3/LDO4
VIN-VOUT
mV
VOUT Temperature Coefficient
LDO1/LDO2/LDO3/LDO4
Line Regulation LDO1/LDO2/
LDO3/LDO4
Output Noise
LDO1/LDO2/LDO3/LDO4
eN
Units
Conditions
ppm/°C Note 3
(V R+1) ≤ VIN ≤ 6.0V
IL = 0.1 mA to IOUT_MAX
Note 4
Note 5
—
2
—
—
15
—
IL = 20 mA, Note 6
—
35
90
IL = 50 mA, Note 6
—
100
280
—
1.2
—
IL = 100 µA, Note 6
IL = 150 mA, Note 6
µV/(Hz)½ IOUT = 100 mA, f = 10 kHz
C OUT = 1 µF to noise
Over Temperature Protection Characteristics:
Thermal Shutdown Protection
TSD
—
150
—
°C
Thermal Shutdown Hysteresis
∆TSD
—
10
—
°C
Note 7
SHDN Input High Threshold
VIH
60
—
—
% of VIN VIN = 2.7V to 6.0V
SHDN Input Low Threshold
VIL
—
—
15
% of VIN VIN = 2.7V to 6.0V
Wake-up Time
(from SHDN mode)
tWK
—
10
—
µsec
V IN = 5V, IL = 100 mA,
C OUT = 1 µF, CIN = 1 µF,
see Figure 4-1
Settling Time
(from SHDN mode)
tS
—
40
—
µsec
V IN = 5V, IL = 100 mA,
C OUT = 1 µF, CIN = 1 µF,
See Figure 4-1
ISHDN
—
±0.01
—
nA
V SHDN = VIN or GND
SELECT Input High Threshold
V SELH
VIN -0.2
—
—
V
V IN = 2.7V to 6.0V
SELECT Input Low Threshold
VSELL
—
—
0.2
V
VIN = 2.7V to 6.0V
ISELECT
—
—
±0.11
±0.06
—
—
µA
VSELECT = VIN
VSELECT = GND
VDET
1.0
1.2
—
—
6.0
6.0
V
TA = 0°C to +70°C
TA = -40°C to +125°C
SHDN Input Characteristics:
Shutdown Leakage Current
SELECT Input Characteristics:
SELECT Input Leakage
Current
RESET Output Characteristics:
Detect Operating
Voltage Range
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.7V and VIN ≥ (VR + 2.5%) + VDROPOUT.
2: VR is the nominal regulator output voltage. For example: VR = 1.8V, 2.5V, 2.8V or 3.0V.
3: TCVOUT = (V OUT-HIGH - VOUT-LOW) * 106 / (VR * ∆Temperature), VOUT-HIGH = Highest voltage measured over the temperature range. VOUT-LOW = Lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is
tested over a load range from 1mA to the maximum specified output current. Changes in output voltage due to heating
effects are determined using thermal regulation specification TCVOUT.
5: Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied.
Specifications are for a current pulse equal to ILMAX at VIN = 6.0V for t = 10 msec.
6: Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its nominal value
with a 1V differential applied.
7: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction
temperatures above 150°C can impact the device reliability.
8: VTH-MIN = 2.55V and V TH-MAX = 2.70V.
9: The Junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the Ambient temperature is not significant.
 2002 Microchip Technology Inc.
DS21702A-page 3
TC1307
Unless otherwise specified, all limits are established for VIN = VR+1, IL = 100 µA, C L = 3.3 µF, SHDN > VIH , TA = 25°C.
Boldface type specifications apply for junction temperatures, TJ (Note 9) of -40°C to +125°C.
Parameter
Reset Threshold Voltage
Reset Circuit Supply Current
Sym
Min
Typ
Max
Units
Conditions
V TH
2.59
2.55
2.63
—
2.66
2.70
V
V
TA = +25°C
TA = -40°C to +125°C
See Figure 4-2
RESET = Open
IVDET
—
20
40
µA
VTH-TEMP
—
30
—
ppm/°C
TVDET-RESET
—
135
—
µsec
V DET = VTH to VTH - 100 mV,
See Figure 4-2
Reset Time-out Period
TRESET
140
300
560
msec
See Figure 4-2
RESET Output Voltage Low
VOL-RES
—
—
0.3
V
VDET = VTH-min
ISINK = 1.2 mA
—
—
0.4
VDET = VTH-min
ISINK = 3.2 mA
—
—
0.3
VDET > 1.0V ISINK = 50 µA
Note 8, See Figure 4-2
V OH-RES
0.8*VDET
VDET1.5V
—
—
V
Maximum Junction Temperature
Range
TJ
-40
—
+150
°C
Maximum Junction Temperature
Range
TJ
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
θJA
—
112.4
—
°C/W
Reset Threshold Voltage
Temperature Coefficient
Detect Threshold to RESET
Active Time Delay
RESET Output Voltage High
ISOURCE = 500 µA
Isource = 800 µA
VDET>VTH-max (Both cases),
See Figure 4-2
Temperature Ranges:
Thermal Package Resistances:
Thermal Resistance, 16L-QSOP
EIA/JEDEC JESD51-751-7
4 Layer Board
Note 1: The minimum VIN must meet two conditions: VIN ≥ 2.7V and VIN ≥ (VR + 2.5%) + VDROPOUT.
2: VR is the nominal regulator output voltage. For example: VR = 1.8V, 2.5V, 2.8V or 3.0V.
3: TCVOUT = (V OUT-HIGH - VOUT-LOW) * 106 / (VR * ∆Temperature), VOUT-HIGH = Highest voltage measured over the temperature range. VOUT-LOW = Lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is
tested over a load range from 1mA to the maximum specified output current. Changes in output voltage due to heating
effects are determined using thermal regulation specification TCVOUT.
5: Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied.
Specifications are for a current pulse equal to ILMAX at VIN = 6.0V for t = 10 msec.
6: Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its nominal value
with a 1V differential applied.
7: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction
temperatures above 150°C can impact the device reliability.
8: VTH-MIN = 2.55V and V TH-MAX = 2.70V.
9: The Junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the Ambient temperature is not significant.
DS21702A-page 4
 2002 Microchip Technology Inc.
TC1307
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, V IN = 3.8V, CIN = 10 µF ceramic (X5R), COUT = 1 µF ceramic (X5R), ILOAD = 100 µA,
SELECT12 = NC, SELECT34 = VIN, SHDN1/2/3/4 = VIN, TA = 25°C.
Junction temperature (T J) is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
Ambient temperature is not significant.
1.830
3.000
VIN = 2.8V
TJ = +125°C
2.996
Output Voltage (V)
Output Voltage (V)
VIN = 4.0V
2.998
1.825
TJ = +125°C
1.820
TJ = +25°C
1.815
TJ = -40°C
1.810
2.994
2.992
TJ = +25°C
2.990
TJ = -40°C
2.988
2.986
2.984
2.982
1.805
2.980
2.978
1.800
0
25
50
75
100
125
0
150
25
50
FIGURE 2-1:
VOUT vs. Load Current.
FIGURE 2-4:
125
150
VOUT vs. Load Current.
I LOAD = 100 µA
VIN = 3.5V
2.506
1.814
TJ = +125°C
2.502
Output Voltage (V)
TJ = +125°C
2.504
TJ = +25°C
2.500
2.498
TJ = -40°C
2.496
2.494
2.492
1.812
TJ = +25°C
1.810
1.808
1.806
1.804
TJ = -40°C
2.490
1.802
2.488
0
25
50
75
100
125
2.7
150
3.0
3.3
3.6
Load Current (mA)
FIGURE 2-2:
3.9
4.2
4.5
4.8
5.1
5.4
5.7
6.0
5.4
5.7
6.0
Input Voltage (V)
VOUT vs. Load Current.
FIGURE 2-5:
VOUT vs. Input Voltage.
2.502
2.805
VIN = 3.8V
ILOAD = 100 µA
TJ = +125°C
2.5
Output Voltage (V)
2.8
Output Voltage (V)
100
1.816
2.508
Output Voltage (V)
75
Load Current (mA)
Load Current (mA)
TJ = +25°C
2.795
TJ = -40°C
2.79
2.785
TJ = +125°C
2.498
2.496
TJ = +25°C
2.494
2.492
2.49
2.78
TJ = -40°C
2.488
0
25
50
75
100
125
150
2.7
3.0
Load Current (mA)
FIGURE 2-3:
VOUT vs. Load Current.
 2002 Microchip Technology Inc.
3.3
3.6
3.9
4.2
4.5
4.8
5.1
Input Voltage (V)
FIGURE 2-6:
VOUT vs. Input Voltage.
DS21702A-page 5
TC1307
Note: Unless otherwise indicated, V IN = 3.8V, CIN = 10 µF ceramic (X5R), COUT = 1 µF ceramic (X5R), ILOAD = 100 µA,
SELECT12 = NC, SELECT34 = VIN, SHDN1/2/3/4 = VIN, TA = 25°C.
Junction temperature (T J) is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
Ambient temperature is not significant.
29.0
2.796
ILOAD = 100 µA
2.792
IVDET Supply Current (µA)
Output Voltage (V)
2.794
TJ = +125°C
2.790
TJ = +25°C
2.788
2.786
2.784
TJ = -40°C
2.782
2.780
VDET = 2.8V
RESET = OPEN
27.0
25.0
23.0
21.0
19.0
17.0
15.0
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
5.7
-40
6.0
-25
-10
5
Input Voltage (V)
FIGURE 2-7:
VOUT vs. Input Voltage.
35
50
65
80
95
110
125
FIGURE 2-10: VDET Supply Current vs. Junction
Temperature.
30.0
280
VIN = 3.8V
ILOAD1/2/3/4 = 0 mA
IVDET Supply Current (µA)
260
IIN Supply Current (µA)
20
Junction Temperature (°C)
240
220
200
180
160
140
VIN = 0V
SHDN1/2/3/4 = 0V
25.0
TJ = +125°C
TJ = +25°C
20.0
TJ = -40°C
15.0
10.0
5.0
120
0.0
100
-40
-25
-10
5
20
35
50
65
80
95
110
0.0
125
1.0
2.0
FIGURE 2-8:
Temperature.
VIN
Supply
Current
270
3.0
4.0
5.0
6.0
V DET Input Voltage (V)
Junction Temperature (°C)
vs.
Junction
FIGURE 2-11: VDET Supply Current vs. VDET Input
Voltage.
I LOAD1/2/3/4 = 0 mA
1.40
240
Shutdown Supply Current (µA)
IIN Supply Current (µA)
SHDN1/2/3/4 = 0V
TJ = +125°C
TJ = +25°C
210
TJ = -40°C
180
2.7
3
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
5.7
6
Input Voltage (V)
1.20
VIN = 6.0V
1.00
VIN = 3.8V
0.80
VIN = 2.7V
0.60
0.40
0.20
0.00
-40
-25
-10
5
20
35
50
65
80
95
110
125
Junction Temperature (°C)
FIGURE 2-9:
Supply Current vs. Input Voltage, VIN.
DS21702A-page 6
FIGURE 2-12: Supply
Temperature.
Current
vs.
Junction
 2002 Microchip Technology Inc.
TC1307
Note: Unless otherwise indicated, V IN = 3.8V, CIN = 10 µF ceramic (X5R), COUT = 1 µF ceramic (X5R), ILOAD = 100 µA,
SELECT12 = NC, SELECT34 = VIN, SHDN1/2/3/4 = VIN, TA = 25°C.
Junction temperature (T J) is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
Ambient temperature is not significant.
0.160
VOUT = 2.8V
Droput Voltage (V)
0.140
TJ = +125°C
0.120
0.100
TJ = +25°C
0.080
TJ = -40°C
0.060
0.040
0.020
0.000
0
25
50
75
100
125
150
Load Current (mA)
FIGURE 2-13: Dropout Voltage vs. Load Current.
FIGURE 2-16: Crosstalk
VOUT2, and VOUT3.
Characteristics
VOUT1,
FIGURE 2-14: Dropout Voltage vs. Load Current.
FIGURE 2-17: Crosstalk
VOUT2, and VOUT3.
Characteristics
VOUT1,
FIGURE 2-15: Crosstalk
VOUT2 and V OUT3.
FIGURE 2-18: Crosstalk
VOUT2, and VOUT3.
Characteristics
VOUT1,
0.140
VOUT = 3.0V
Dropout Voltage (V)
0.120
TJ = +125°C
0.100
TJ = +25°C
0.080
TJ = +40°C
0.060
0.040
0.020
0.000
0
25
50
75
100
125
150
Load Current (mA)
Characteristics
 2002 Microchip Technology Inc.
VOUT1,
DS21702A-page 7
TC1307
Note: Unless otherwise indicated, V IN = 3.8V, CIN = 10 µF ceramic (X5R), COUT = 1 µF ceramic (X5R), ILOAD = 100 µA,
SELECT12 = NC, SELECT34 = VIN, SHDN1/2/3/4 = VIN, TA = 25°C.
Junction temperature (T J) is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
Ambient temperature is not significant.
70
VIN = 4.1V
VOUT = 2.8V
COUT = 10µF Ceramic
ILOAD = 100 mA
60
PSSR (dB)
50
40
30
20
10
0
1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Ripple Voltage Frequency (Hz)
FIGURE 2-19: Line Step Response.
FIGURE 2-22: Power Supply Rejection Ratio vs.
Ripple Voltage Frequency.
FIGURE 2-20: Line Step Response.
FIGURE 2-23: Output Noise.
70
VIN = 4.1V
VOUT = 2.8V
COUT = 1 µF Ceramic
ILOAD = 100 mA
60
PSRR (dB)
50
40
30
20
10
0
1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
Ripple Voltage Frequency (Hz)
FIGURE 2-21: Power Supply Rejection Ratio vs.
Ripple Voltage Frequency.
DS21702A-page 8
FIGURE 2-24: Output Noise.
 2002 Microchip Technology Inc.
TC1307
Note: Unless otherwise indicated, V IN = 3.8V, CIN = 10 µF ceramic (X5R), COUT = 1 µF ceramic (X5R), ILOAD = 100 µA,
SELECT12 = NC, SELECT34 = VIN, SHDN1/2/3/4 = VIN,TA = 25°C.
Junction temperature (T J) is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
Ambient temperature is not significant.
375
VDET = 0V to 2.7V
Reset Delay Time (ms)
350
325
300
275
250
225
200
-40
-25
-10
5
20
35
50
65
80
95
110
125
Junction Temperature (°C)
FIGURE 2-25: Response From SHDN.
FIGURE 2-28: Power-Up Reset Time-out Period vs.
Junction Temperature.
3
2.634
RESET = OPEN
Output Voltage (V)
2.5
Reset Threshold Voltage (V)
COUT = 1 µF
VOUT = Set to 2.8V
2
1.5
1
0.5
0
2.633
2.632
2.631
2.63
2.629
2.628
2.627
2.626
50
100
150
200
250
300
350
400
-40
-25
-10
FIGURE 2-26: Output Voltage vs. Current.
20
35
50
65
80
95
110
125
FIGURE 2-29: Reset Threshold Voltage vs. Junction
Temperature.
160
500
400
Time to Reset Output (µs)
COUT = 1 µF
ROUT < 0.1 ohm
VOUT = Set to 2.8V
450
Short Circuit Current (mA)
5
Junction Temperature (°C)
Output Current (mA)
350
300
250
200
150
100
140
120
100
80
60
50
40
0
1
2
3
4
5
6
Input Voltage (V)
FIGURE 2-27: Short Circuit Current vs. Input Voltage.
 2002 Microchip Technology Inc.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
Overdrive Voltage (V below VTH)
FIGURE 2-30: Reset Delay vs. Overdrive Voltage.
DS21702A-page 9
TC1307
Note: Unless otherwise indicated, V IN = 3.8V, CIN = 10 µF ceramic (X5R), COUT = 1 µF ceramic (X5R), ILOAD = 100 µA,
SELECT12 = NC, SELECT34 = VIN, SHDN1/2/3/4 = VIN, TA = 25°C.
Junction temperature (T J) is approximated by soaking the device under test at an ambient temperature equal to the
desired Junction temperature. The test time is small enough such that the rise in the Junction temperature over the
Ambient temperature is not significant.
0.80
5.97
VDET = 2.55V
VDET = 6.0V
0.70
ISOURCE = 500 µA
5.96
RESET VOH (V)
Reset V OL (V)
0.60
0.50
0.40
0.30
5.95
5.94
ISOURCE = 800 µA
5.93
0.20
5.92
0.10
0.00
5.91
0.0
2.0
4.0
6.0
8.0
-40
10.0
-25
-10
Sink Current (mA)
5
20
35
50
65
80
95
110
125
Junction Temperature (°C)
FIGURE 2-31: Reset VOL-RES vs. ISINK.
FIGURE 2-34: Reset
Temperature.
VOH-RES
vs.Junction
0.35
VDET = 2.55V
0.3
I SINK = 1.2 mA
Reset V OL (V)
0.25
0.2
0.15
I SINK = 3.2 mA
0.1
0.05
0
-40
-25
-10
5
20
35
50
65
80
95
110
125
Junction Temperature (°C)
FIGURE 2-32: Reset
Temperature.
VOL-RES
vs.
Junction
FIGURE 2-35: Power-Up RESET Timing.
4.00
325
Ground Current (µA)
3.60
Reset V OH (V)
VDET = VIN = 3 .8V
VDET = 3.80V
3.80
3.40
3.20
3.00
2.80
2.60
2.40
300
275
250
225
2.20
2.00
0.00
200
2.00
4.00
6.00
8.00
Source Current (mA)
FIGURE 2-33: Reset VOH-RES vs. ISOURCE.
DS21702A-page 10
10.00
0
25
50
75
100
125
150
Load Current (mA)
FIGURE 2-36: Ground Current vs. Load Current.
 2002 Microchip Technology Inc.
TC1307
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Name
Function
VDET
Voltage Detect Input
SHDN1
Shutdown for VOUT1
SELECT12
Input for setting VOUT1 and VOUT2.
VIN
Input Voltage Connection
VIN
Input Voltage Connection
GND
Ground connection
SHDN3
Shutdown for V OUT3
VIN
Input Voltage Connection
SHDN4
Shutdown for V OUT4
SELECT34
Input for setting VOUT3 and VOUT4.
VOUT4
LDO4 Output
VOUT3
LDO3 Output
VOUT2
LDO2 Output
VOUT1
LDO1 Output
SHDN2
Shutdown for V OUT2
RESET
Reset Output
TABLE 3-1:
3.1
Pin Description Table.
3.5
Ground (GND)
Connect this pin to the circuit ground. NOTE: This pin
does not carry high current and should be connected to
quiet circuit ground.
3.6
Shutdown Control Input for VOUT3
(SHDN3)
LDO#3 output is enabled when a logic high is applied
to the SHDN3 input. LDO#3 output is disabled with a
logic low tied to the SHDN3 pin. When shutdown,
LDO#3 enters a low quiescent current state and the linear pass P-Channel MOSFET is off. The RESET output remains valid and is independent of SHDN3.
3.7
Shutdown Control Input for VOUT4
(SHDN4)
LDO#4 output is enabled when a logic high is applied
to the SHDN4 input. LDO#4 output is disabled with a
logic low tied to the SHDN4 pin. When shutdown,
LDO#4 enters a low quiescent current state and the linear pass P-Channel MOSFET is off. The RESET output remains valid and is independent of SHDN4.
3.8
Voltage Detect Input (VDET)
SELECT Control Input for Setting
VOUT3 and VOUT4 (SELECT34)
Input pin that is compared to internal threshold voltage
(typically 2.63V). When the VDET input is below the
2.63V threshold, the RESET output is held in its normal
low state. When the input voltage on the VDET pin rises
above the threshold voltage, the RESET output pin
remains low for 300 mS (Typical). After the delay, the
RESET pin changes to a logic high state.
Input pin used to select the output voltage of LDO#3
and LDO#4. When SELECT is tied to VIN, V OUT3 =
VOUT4 = 2.8V. When SELECT is tied to GND, VOUT3 =
VOUT4 = 1.8V. If the SELECT input is not connected,
VOUT3 = VOUT4 = 2.5V.
3.2
Output voltage selected by tri-state input SELECT34.
Output can be set to 1.80V, 2.50V or 2.80V
Shutdown Control Input for VOUT1
(SHDN1)
LDO#1 output is enabled when a logic high is applied
to the SHDN1 input. LDO#1 output is disabled with a
logic low tied to the SHDN1 pin. When shutdown,
LDO#1 enters a low quiescent current state and the linear pass P-Channel MOSFET is off. The RESET output remains valid and is independent of SHDN1.
3.3
SELECT Control Input for Setting
VOUT1 and VOUT2 (SELECT12)
Input pin used to select the output voltage of LDO#1
and LDO#2. When SELECT is tied to VIN, VOUT1 =
VOUT2 = 3.0V. When SELECT is tied to GND, VOUT1 =
VOUT2 = 2.5V. If the SELECT input is not connected,
VOUT1 = VOUT2 = 2.8V.
3.4
3.9
3.10
Regulated Output Voltage #4 (VOUT4)
Regulated Output Voltage #3 (VOUT3)
Output voltage selected by tri-state input SELECT34.
Output can be set to 1.80V, 2.50V or 2.80V
3.11
Regulated Output Voltage #2 (VOUT2)
Output voltage selected by tri-state input SELECT12.
Output can be set to 2.50V, 2.80V or 3.00V
3.12
Regulated Output Voltage #1 (VOUT1)
Output voltage selected by tri-state input SELECT12.
Output can be set to 2.50V, 2.80V or 3.00V.
Input Voltage VIN
Connect input source to this pin. All VIN pins must be
tied together.
 2002 Microchip Technology Inc.
DS21702A-page 11
TC1307
3.13
Shutdown Control Input for VOUT2
(SHDN2)
LDO#2 output is enabled when a logic high is applied
to the SHDN2 input. LDO#2 output is disabled with a
logic low tied to the SHDN2 pin. When shutdown,
LDO#2 enters a low quiescent current state and the linear pass P-Channel MOSFET is off. The RESET output remains valid and is independent of SHDN2.
DS21702A-page 12
3.14
RESET Output (RESET)
Logic low output when voltage on VDET pin is below the
RESET Threshold Voltage. When the voltage on the
VDET pin rises above the RESET Threshold Voltage,
the RESET output will remain low for the RESET Timeout Period and then transition to a logic high.
 2002 Microchip Technology Inc.
TC1307
4.0
DEVICE OVERVIEW
The TC1307 integrates four high performance linear
Low Dropout Regulators and a microcontroller reset
function.
As shown in the block diagram (Figure 4-3) using
dashed lines, each LDO has an independent shutdown, error amplifier, P-MOS pass transistor and feedback divider resistors. All four LDOs share a common
voltage reference. LDO output numbers one and two
share a tri-state select input while LDO numbers three
and four share a tri-state select input. The select input
is used to program the LDO output voltage.
ommended to lower the source impedance. For applications that have more than 1 µF of capacitance on the
LDO outputs, higher input capacitance (4.7 µF) may be
needed to ensure stability.
4.1.3
SHUTDOWN OPERATION
4.1
Low Dropout Out Linear Regulators
Each LDO output can be enabled and disabled using
its respective shutdown input pin. For example, when
the level on SHDN1 is below the logic low level threshold (VIL), LDO#1 output is disabled (P-Channel MOSFET is turned OFF). If all four shutdown inputs are
below VIL, the bandgap reference is turned off and the
shutdown current is typically less than 0.1 µA. The LDO
output will typically wake-up in 10 µs and the output will
settle in approximately 40 µs when brought out of shutdown mode. See Figure 4-1 for timing definition. The
microcontroller RESET output function is independent
of all SHDN input pins.
4.1.1
OUTPUT
4.2
Also shown in the block diagram is the microcontroller
reset monitor. The reset monitor voltage detect input is
independent of the LDO input or output voltages.
The TC1307 integrates four low drop out linear regulators. Each regulator has 150 mA output current capability. A minimum of 1 µF output capacitance is required
on each of the LDOs for circuit stability. The output
capacitor type can be ceramic, tantalum or aluminum.
The esr range required for the output capacitor is 0 Ω
to 2 Ω. To improve the dynamic performance of the
LDO in cases where sudden input voltage changes or
load current changes are present, larger capacitors can
be used.
The output voltage of the LDO can be selected using
the SELECT input pins. Table 4-1 summarizes how to
select the desired LDO output voltage for VOUT1 and
VOUT2. Table 4-2 summarizes how to select the desired
LDO output voltage for V OUT3 and VOUT4.
SELECT12
VOUT1
VOUT2
GND
2.50V
2.50V
No Connect
2.80V
2.80V
VIN
3.00V
3.00V
TABLE 4-1:
SELECT12 MODE settings.
SELECT34
VOUT3
VOUT4
GND
1.80V
1.80V
No Connect
2.50V
2.50V
VIN
2.80V
2.80V
TABLE 4-2:
4.1.2
Voltage Reset Monitor
The independent voltage reset output of the TC1307
can be used for low battery input voltage detect or
microcontroller power on reset function. The voltage
reset function monitors the voltage on the VDET pin.
The active low RESET output is capable of sourcing
and sinking current (Push-Pull). When the voltage on
the VDET pin is below the 2.63V typical threshold, the
RESET output pin is active low and capable of sinking
3.2 mA while holding the RESET output voltage below
0.4V. When the voltage on the VDET pin rises above the
2.63V typical threshold, the RESET output will remain
low for the TRESET time period. After the RESET time
out period, the RESET output voltage will transition to
the high output state (> VDET-1.5V when sourcing
800 µA), if the VDET pin remains above the threshold
voltage. The RESET output is current limited. The maximum source or sink current recommended for normal
operation is 10 mA.
The RESET output will be driven low within 100 µsec of
VDET pin going below the RESET voltage threshold of
2.63V typical. The RESET output will remain valid for
VDET voltages greater than 1.0V. See Figure 4-2 for
VDET and RESET output timing diagram.
SELECT34 MODE Settings.
INPUT
The TC1307, like all low drop out linear regulators,
requires a relatively low source impedance (< 10 Ω)
tied to the VIN pin of the device to ensure circuit stability. For battery applications or in applications that have
long lead length from the input voltage source to the
LDO VIN pin, a minimum capacitance of 2.2 µF is rec-
 2002 Microchip Technology Inc.
DS21702A-page 13
TC1307
VIH
SHDN
VIL
tS
90%
10%
VOUT
tWK
FIGURE 4-1:
Wake-up From SHDN.
VTH
VDD
TRESET
TVDET-RESET
VOH_RES
RESET
VOL_RES
1V
FIGURE 4-2:
RESET Timing Diagram.
DS21702A-page 14
 2002 Microchip Technology Inc.
TC1307
1
VDET
+
-
tDELAY
C
RESET
16
(300ms)
OVERTEMPERATURE
8
VIN
VREF2
VIN
SHDN1
2
SHDN1
VIN
VREF
SEL12
VREF
+
SHDN
A
VOUT1
14
VIN
15
SHDN2
SHDN2
3
VIN
VREF
SELECT12
+
A
VOUT2
13
VIN
7
SHDN3
SEL34
VREF
SHDN3
+
9
4
SEL12
A
VOUT3
12
VIN
SHDN4
SHDN4
VIN
5
SEL34
10
SELECT34
VREF
+
6
A
VOUT4
11
GND
FIGURE 4-3:
TC1307 Block Diagram.
 2002 Microchip Technology Inc.
DS21702A-page 15
TC1307
5.0
APPLICATIONS
5.3
5.1
Load Partitioning
A minimum output capacitance of 1 µF for the TC1307
is required for stability. The esr requirements on the
output capacitor are between 0 and 2 ohms. The output
capacitor should be located as close to the LDO output
as practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the acceptable esr range required. A typical 1 µF X5R 0805
capacitor has an esr of 50 milli-ohms. Larger output
capacitors can be used with the TC1307 to improve
dynamic behavior, noise and ripple rejection performance.
The TC1307 can be used to power two separate channels for a wide range of applications. Each channel can
be turned ON and OFF independently of the other. In
this example, the SELECT12 pin is tied to V IN and the
SELECT34 pin is tied to GND. The output voltages of
VOUT1 and VOUT2 are 3.0V and the output voltage of
VOUT3 and VOUT4 are 1.8V. If V OUT1 and V OUT3 were
powering 1 Channel and V OUT2 and V OUT4 were powering an identical Channel, either Channel could be
powered independent of the other Channel. The output
voltage of V OUT1 is being monitored by the internal voltage detection circuit. When the output of V OUT1 is
below the typical 2.63V threshold voltage, the RESET
output will transition low.
5.2
5.4
Output Capacitor
Power Dissipation
The internal power loading within the TC1307 is a function of input voltage, output voltage, output current, quiescent current and RESET output dissipation. For
many applications the power dissipation within the linear P-Channel device can be used as a good approximation of total power dissipation. This is due to the low
quiescent current consumed even when the LDO output is providing full load current (150 mA).
Input Capacitor
Low input source impedance is necessary for the LDO
to operate properly. When operating off of batteries or
in applications with long lead length (>10”) between the
input source and the LDO, some input capacitance is
required. A minimum of 2.2 µF is recommended for
most applications and the capacitor should be placed
as close to the input of the LDO as practical (>0.2”).
Larger input capacitors will help reduce the input
impedance and further reduce any high frequency
noise on the input and output of the LDO. If more than
1 µF of capacitance is used on the LDO outputs, a
4.7 µF input capacitor is recommended.
Shutdown #2
Micro
Controller
VDET
Shutdown #1
SHDN1
SELECT12
VIN
4.7 µF
VIN
GND
Battery
Input
SHDN3
VIN
1
16
2
15
TC1307
3
14
4
13
5
12
6
11
7
10
8
9
RESET
MCLR
or
RESET
SHDN2
VOUT1
+3.0V
VOUT2
+3.0V
VOUT3
VOUT4
+1.8V
+1.8V
SELECT34
VDD
1 µF
1 µF
1 µF
1 µF
SHDN4
Shutdown #3
Shutdown #4
FIGURE 5-1:
Typical 4 Output with RESET Application.
DS21702A-page 16
 2002 Microchip Technology Inc.
TC1307
5.4.1
P-CHANNEL LINEAR PASS DEVICE
P RESET = ( V DET – V SOURCE ) × I SOUR CE
P Li near = ( V IN ( MAX ) – V OU T ( MIN ) ) × I OUT ( MAX )
Where:
PLinear = Power dissipated in the LDO P-Channel
linear pass element.
VIN(MAX) = Maximum input voltage (VIN)
VOUT(MAX) = Minimum LDO output Voltage (VOUT)
IOUT(MAX) = Maximum LDO output current
5.4.2
QUIESCENT CURRENT
The quiescent current consumed by the TC1307 has
two components. The quiescent current required to
bias the LDO regulators and the quiescent current
required to bias the voltage detection circuitry. To determine the power dissipation as a result of the total
device quiescent current both the maximum input voltage on the VIN and VDET inputs should be used.
P Q = V IN × I IN + V DET × I D ET
Where:
PQ = Power internal to the LDO as a result of internal biasing
VIN = Input voltage
Where:
PRESET = Power dissipation as a result of RESET
output while in the high state
VDET = Detect Voltage
VSOURCE = RESET output pin voltage while in the
high state
ISOURCE = Output current being sourced
5.4.4
The total power dissipated within the TC1307 is the
sum of the power dissipated in each of the four LDOs,
the PQ term and the PRESET term (either sinking or
sourcing). Because of the CMOS construction, the typical IIN for the TC1307 is 220 µA. When operating at a
maximum of 5V this results is a power dissipation of
1.2 milli-Watts. For most applications this is small compared to the LDO pass device power dissipation and
can be neglected. The PRESET term for a typical 3.2 mA
sinking application will dissipate a maximum of 3.2 mA
x 0.4V or 1.28 milli-Watts. A typical sourcing application of 800 µA will have a maximum 1.5V drop from the
VDET voltage will dissipate a maximum of 800 µA x
1.5V or 1.2 milli-Watts. Again for most applications this
is small compared to the LDO pass device power dissipation and can be neglected.
IIN = Input current when all load currents = 0 mA
P TOTAL = P Li ne ar + P Q + P RESET
VDET = Detect Input Voltage
IVDET = Voltage detect input pin current
5.4.3
RESET OUTPUT
The power dissipation for the RESET output driver can
be a result of the sinking current or sourcing current
depending on the state of the output.
P RESE T = V OL × I SINK
Where:
PRESET = Power dissipated as a result of the
RESET output.
VOL = RESET low output voltage
ISINK = RESET sink current
The power dissipation internal to the RESET output
due to sourcing current can be calculated by using the
following equation.
 2002 Microchip Technology Inc.
TOTAL INTERNAL POWER DISSIPATION
5.4.5
MAXIMUM JUNCTION TEMPERATURE
The operating junction temperature (TJ) specified for
the TC1307 is 125°C. To estimate the internal junction
temperature of the TC1307, the total internal power dissipation (PTOTAL) is multiplied by the thermal resistance
from junction to ambient (θJA) of the device. The thermal resistance from junction to ambient for the QSOP
16-pin package is estimated at 112.4°C/W. The actual
thermal resistance from junction to air can vary from
application to application for the QSOP16 depending
on board copper area, copper thickness, airflow and
other external environmental factors.
T J ( MAX ) = P TO TAL × θ JA
The maximum power dissipation capability for a package (PD(MAX)) can be calculated given the junction to
air thermal resistance and the maximum ambient temperature (TA(MAX)) for the application. The following
equation can be used to determine the package maximum internal power dissipation.
DS21702A-page 17
TC1307
P D ( MAX )
5.5
( T J ( MAX ) – T A ( MAX ) )
= --------------------------------------------------θ JA
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power dissipation as a result of quiescent current and RESET
output are small enough to be neglected.
Input Voltage:
VIN = 3.1V to 4.1V
LDO Output Voltages and Currents:
Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The thermal resistance from junction to air (θJA) is derived from
an EIA/JEDEC standard for measuring thermal resistance for small surface mount packages. The EIA/
JEDEC specification is JESD51-7 “High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages”. The standard describes the test method
and board specifications for measuring the thermal
resistance from junction to case. The actual thermal
resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792 for more information regarding
this subject.
TJRISE = PTOTAL x θJA
VOUT1 = 3.0V
TJRISE = 516.4 milli-Watts x 112.4°C/Watt
IIOUT1 = 100 mA
TJRISE = 58.1°C
VOUT2 = 3.0V
IIOUT2 = 100 mA
Junction Temperature Estimate
VOUT3 = 1.8V
To estimate the internal junction temperature (TJ), the
calculated junction temperature rise (TJRISE) is added
to the ambient or offset temperature (TAMBIENT). For
this example the worst case junction temperature is
estimated below.
IIOUT3 = 60 mA
VOUT4 = 1.8V
IIOUT4 = 60 mA
TJ =T JRISE + TAMBIENT
Maximum Ambient Temperature:
TA(MAX)= 50°C
Internal Power Dissipation:
Internal Power dissipation is the sum of the power dissipation for each LDO pass device.
PLDO1 = (VIN(MAX)-VOUT1(MIN)) x IOUT1(MAX)
PLDO1 = (4.1V - (0.975 x 3.0V)) x 100 mA
PLDO1 = 117.5 milli-Watts
PLDO2 = (4.1V - (0.975 x 3.0V)) x 100 mA
PLDO2 = 117.5 milli-Watts
TJ =108.1°C
Maximum Package Power Dissipation
The maximum power dissipation capability for the
TC1307 can be approximated by finding the maximum
allowable temperature rise from junction to case and
dividing that by the estimated thermal resistance of the
application. For this example, the maximum allowable
junction temperature rise is 125°C - 50°C or 75°C. By
dividing 75°C by the estimated thermal resistance
(112.4°C/Watt), the maximum allowable power dissipation is calculated to be 667.3 milli-Watts.
PLDO3 = (4.1V - (0.975 x 1.8V)) x 60 mA
5.6
Device Protection
PLDO3 = (2.35V x 60 mA)
5.6.1
OVER CURRENT LIMIT
PLDO3 = 140.7 milli-Watts
PLDO4 = (4.1V - (0.975 x 1.8V)) x 60 mA
PLDO4 = 140.7 milli-Watts
PTOTAL = PLDO1 + PLDO2 + PLDO3 + PLDO4
PTOTAL = 516.4 milli-Watts
DS21702A-page 18
In the event of a faulted output load, the maximum current the LDO will permit to flow is limited internally. For
each of the four LDO’s internal to the TC1307, the limit
in the event of a short circuit will be 360 mA typical.
This limit can be used to prevent damage to the circuit
board or connectors. The over current protection for
each LDO output is independent. For example, if LDO1
output is shorted to ground, the over current protection
will limit the output current for LDO1. If the junction temperature does not rise above the typical 150°C thermal
shutdown point the other three LDO outputs (LDO2,
LDO3, LDO4) will remain within regulation.
 2002 Microchip Technology Inc.
TC1307
5.6.2
OVER TEMPERATURE PROTECTION
If the internal power dissipation within the TC1307 is
excessive due to a faulted load or higher than specified
line voltage, an internal temperature sensing element
will prevent the junction temperature from exceeding
approximately 150°C. If the junction temperature does
exceed approximately 150°C, all LDO outputs will be
disabled until the junction temperature cools to approximately 140°C, at which point the device will resume
normal operation. The RESET output will continue to
operate normally in the event of a thermal shutdown.
5.7
Recommended Physical Layout
Figure 5-2 represents a typical layout using the
TC1307 16-pin QSOP package. C1, C2, C3 and C 4 are
1 µF X5R 0603 ceramic output capacitors and C IN is a
2.2 µF X5R 0805 ceramic capacitor. No other components are required for this quad output LDO with microcontroller reset function. Utilizing the highly integrated
TC1307, the total board area required is less than
0.300 square inches.
to be wide. It is more important for the GND pins to be
connected to a quiet circuit ground. Noise on the GND
pins may result in noise at the output of the LDO. In
Figure 5-2, a ground plane is used to connect the
TC1307 Pins to the GND plane that has the VOUT
capacitor return tied to it. For applications that have ripple voltage on the input, the CIN capacitor return can be
separated from the ground plane by running a trace
from the capacitor to the ground plane. This impedance
will help to reduce the noise on the output of the LDO.
The output voltage regulation uses the GND pins of the
TC1307 as the return path for the internal bandgap reference. Any voltage drops between the load and the
respective VOUT pin and GND pin will show up as regulation losses. It is important to size the VOUT and GND
conductors for minimum voltage drops. The maximum
application load current will determine how large these
traces should be. As shown in Figure 5-2, a ground
plane can be used minimize the trace resistance from
the load to the TC1307 GND pin.
For CMOS LDOs, the GND or quiescent current is
small when compared to the maximum output current
capability. The GND pins connected to the TC1307 do
not carry high current and it is not necessary for them
SHDN2
SHDN1
Pin 1
C1
C2
CIN
SHDN3
Backplane Traces
C4 C3
RESET
VOUT1
VOUT2
VOUT3
VOUT4
SHDN4
= GND Plane
= Top Metal Layer
FIGURE 5-2:
TC1307 Typical Layout.
 2002 Microchip Technology Inc.
DS21702A-page 19
TC1307
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
1
16
2
15
3
14
4
5
Legend:
Note:
*
XX...X
YY
WW
NNN
13
TC1307
YYWW
NNN
12
6
11
7
10
8
9
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line thus limiting the number of available
characters for customer specific information.
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
DS21702A-page 20
 2002 Microchip Technology Inc.
TC1307
6.2
Taping Form
Component Taping Orientation for 16-Pin QSOP (Narrow) Devices
User Direction of Feed
User Direction of Feed
PIN 1
W
PIN 1
Standard Reel Component Orientation
for TR Suffix Device
P
Reverse Reel Component Orientation
for RT Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size:
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
12 mm
8 mm
2500
13 in.
16-Pin QSOP (N)
6.3
Packaging Information
16-Pin QSOP (Narrow)
PIN 1
.157 (3.99)
.244 (6.20)
.150 (3.81)
.228 (5.80)
.196 (3.05)
.189 (2.67)
.010 (0.25)
.004 (0.10)
.069 (1.75)
.053 (1.35)
.025
(0.635)
TYP.
.012 (0.31)
.008 (0.21)
 2002 Microchip Technology Inc.
8°
MAX.
.010 (0.25)
.007 (0.19)
.050 (1.27)
.015 (0.40)
DS21702A-page 21
TC1307
NOTES:
DS21702A-page 22
 2002 Microchip Technology Inc.
TC1307
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
013001
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 2002 Microchip Technology Inc.
DS21702A-page 23
TC1307
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: TC1307
Y
N
Literature Number: DS21702A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS21702A-page 24
 2002 Microchip Technology Inc.
TC1307
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
X
-XX
X
X
Device Threshold LDO
Temp. Packaging # Leads
Type
Voltage Output Range
Voltages
Device:
TC1307:
Threshold Voltage:
R
=
LDO Output Voltages:
XY
XY
XY
XY
=
=
=
=
Temperature Range:
V
=
Package:
QR = QSOP Package, 16-lead
Tape and Reel:
TR = Tape and Reel
XX
Tape &
Reel
Examples:
a)
TC1307R-XYVQRTR
4-Channel LDO w/Select Mode, Shutdown and
Independent Reset
2.63V
1.8V
2.5V
2.8V
3.0V
-40°C to +125°C (Extended)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2002 Microchip Technology Inc.
DS21702A-page25
TC1307
NOTES:
DS21702A-page 26
 2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,
PRO MATE, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microID,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
DS21702A - page 27
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
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01/18/02
*DS21702A*
DS21702A-page 28
 2002 Microchip Technology Inc.