MOTOROLA MPC9229

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
400 MHz Low Voltage PECL
Clock Synthesizer
The MPC9229 is a 3.3V compatible, PLL based clock synthesizer
targeted for high performance clock generation in mid-range to
high-performance telecom, networking and computing applications. With
output frequencies from 25 MHz to 400 MHz and the support of differential
PECL output signals the device meets the needs of the most demanding
clock applications.
Order Number: MPC9229/D
Rev 1 03/2003
MPC9229
400 MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
Freescale Semiconductor, Inc...
Features
25 MHz to 400 MHz synthesized clock output signal
•
•
•
•
•
•
•
•
•
•
•
•
•
Differential PECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
3.3V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32 lead LQFP and 28 PLCC packaging
FN SUFFIX
28--LEAD PLCC PACKAGE
CASE 776
SiGe Technology
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MC12429
Functional Description
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. The frequency of the internal crystal
oscillator is divided by 16 and then multiplied by the PLL. The VCO within
the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by
a divider that is configured by either the serial or parallel interfaces. The
crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL
post-divider N determine the output frequency.
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 4⋅M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50Ω to VCC – 2.0V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
 Motorola, Inc. 2003
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MPC9229
XTAL_IN
XTAL_OUT
XTAL
Ref
÷16
VCO
10 -- 20 MHz
00
01
10
11
÷1
÷2
÷4
÷8
÷4
PLL
800-1600 MHz
Sync
FB
÷0 to ÷511
9-Bit M-Divider
VCC
Test
TEST
9
2
3
M-Latch
N-Latch
T-Latch
LE
P_LOAD
S_LOAD
P/S
0
1
0
S_DATA
S_CLOCK
1
Bit 3-4
Bit 5-13
Bit 0-2
14 Bit Shift Register
VCC
M[0:8]
N[1:0]
OE
18
N[1]
M[4]
19
M[5]
20
M[6]
21
M[7]
GND
22
M[8]
TEST
23
N[0]
VCC
24
N[1]
GND
25
NC
FOUT
26
FOUT
S_CLOCK
VCC
Figure 1. MPC9229 Logic Diagram
24
23
22
21
20
19
18
17
GND
25
16
NC
TEST
26
15
M[3]
14
M[2]
13
M[1]
12
M[0]
S_DATA
27
17
N[0]
S_LOAD
28
16
M[8]
VCC
27
VCC_PLL
1
15
M[7]
VCC
28
NC
2
14
M[6]
GND
29
NC
3
13
M[5]
FOUT
30
11
P_LOAD
XTAL_IN
4
M[4]
FOUT
31
10
12
OE
VCC
32
MOTOROLA
M[0]
M[1]
M[2]
M[3]
2
3
4
5
6
7
XTAL_OUT
8
XTAL_IN
P_LOAD
Figure 2. MPC9229 28--Lead PLCC Pinout
(Top View)
9
1
NC
11
NC
10
VCC_PLL
9
VCC_PLL
8
S_LOAD
7
S_DATA
6
MPC9229
S_CLOCK
5
OE
MPC9229
XTAL_OUT
Freescale Semiconductor, Inc...
FOUT
FOUT
OE
Figure 3. MPC9229 32--Lead LQFP Pinout
(Top View)
2
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9229
Table 1. Pin Configuration
Pin
I/O
Default
Type
Freescale Semiconductor, Inc...
XTAL_IN, XTAL_OUT
Analog
Function
Crystal oscillator interface
FOUT, FOUT
Output
LVPECL
Differential clock output
TEST
Output
LVCMOS
Test and device diagnosis output
S_LOAD
Input
0
LVCMOS
Serial configuration control input.
This inputs controls the loading of the configuration latches with the contents of
the shift register. The latches will be transparent when this signal is high, thus the
data must be stable on the high-to-low transition.
P_LOAD
Input
1
LVCMOS
Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive
S_DATA
Input
0
LVCMOS
Serial configuration data input.
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input.
M[0:8]
Input
1
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
OE
Input
1
LVCMOS
Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of
runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state
(FOUT = L, FOUT = H)
GND
Supply
Supply
Ground
VCC
Supply
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the
positive power supply for correct operation
VCC_PLL
Supply
Supply
VCC
PLL positive power supply (analog power supply)
Negative power supply (GND)
Table 2. Output frequency range and PLL Post-divider N
N
TIMING SOLUTIONS
O
Output
di
division
i i
O
Output
ffrequency range
0
1
200 - 400 MHz
1
2
100 - 200 MHz
1
0
4
50 - 100 MHz
1
1
8
25 - 50 MHz
1
0
0
0
3
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MOTOROLA
Freescale Semiconductor, Inc.
MPC9229
Table 3. General Specifications
Symbol
Characteristics
Min
VTT
Output Termination Voltage
MM
ESD protection (Machine Model)
200
HBM
Max
Unit
V
ESD protection (Human Body Model)
2000
V
Latch-Up Immunity
200
mA
CIN
Input Capacitance
θJA
LQFP 32 Thermal resistance junction to ambient
JESD 51-3, single layer test board
θJC
4.0
LQFP 32 Thermal resistance junction to case
Condition
V
LU
JESD 51-6, 2S2P multilayer test board
Freescale Semiconductor, Inc...
Typ
VCC - 2
pF
Inputs
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
23.0
26.3
°C/W
MIL-SPEC 883E
Method 1012.1
Table 4. Absolute Maximum Ratingsa
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
3.9
V
VIN
DC Input Voltage
-0.3
VCC + 0.3
V
DC Output Voltage
-0.3
VCC + 0.3
V
DC Input Current
±20
mA
DC Output Current
±50
mA
125
°C
VOUT
IIN
IOUT
TS
Storage Temperature
-65
Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VCC + 0.3
V
LVCMOS
0.8
V
LVCMOS
±200
µA
VIN = VCC or GND
LVCMOS control inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1], OE)
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input
2.0
Currenta
Differential clock output
FOUTb
VOH
Output High Voltagec
VCC--1.02
VCC--0.74
V
LVPECL
VOL
Voltagec
VCC--1.95
VCC--1.60
V
LVPECL
Output Low
Test and diagnosis output TEST
VOH
Output High Voltagec
VOL
Output Low Voltagec
2.0
V
IOH = -0.8 mA
0.55
V
IOL = 0.8 mA
Maximum PLL Supply Current
20
mA
VCC_PLL Pins
Maximum Supply Current
100
mA
All VCC Pins
Supply current
ICC_PLL
ICC
a. Inputs have pull-down resistors affecting the input current.
b. Outputs terminated 50Ω to VTT = VCC - 2V.
c. The MPC9229 TEST output levels are compatible to the MC12429 output levels.
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9229
Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to +70°C)a
Symbol
Crystal interface frequency range
fVCO
VCO frequency rangeb
fMAX
Output Frequency
DC
Output duty cycle
tr, tf
Output Rise/Fall Time
fS_CLOCK
tP,MIN
Freescale Semiconductor, Inc...
Characteristics
fXTAL
Min
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
Max
Unit
10
20
MHz
800
1600
MHz
200
100
50
25
400
200
100
50
MHz
MHz
MHz
MHz
55
%
45
Typ
50
0.05
0.3
ns
Serial interface programming clock frequencyc
0
10
MHz
Minimum pulse width
(S_LOAD, P_LOAD)
50
ns
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
tJIT(CC)
Cycle--to--cycle jitter
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
90
130
160
190
ps
ps
ps
ps
tJIT(PER)
Period Jitter
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
70
120
140
170
ps
ps
ps
ps
10
ms
tLOCK
Maximum PLL Lock Time
Condition
20% to 80%
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ M ÷ 4.
c. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See application section for more details.
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MPC9229
to match the VCO frequency range of 800 to 1600 MHz in
order to achieve stable PLL operation:
Programming the MPC9229
Programming the MPC9229 amounts to properly
configuring the internal PLL dividers to produce the desired
synthesized frequency at the output. The output frequency
can be represented by this formula:
fOUT = (fXTAL ÷ 16) ⋅ (4 ⋅ M) ÷ (4 ⋅ N) or
fOUT = (fXTAL ÷ 16) ⋅ M ÷ N
MMIN = 4⋅fVCO,MIN ÷ fXTAL and
MMAX = 4⋅fVCO,MAX ÷ fXTAL
(3)
(4)
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between M=200
and M = 400. Table 7 shows the usable VCO frequency and
M divider range for other example input frequencies.
(1)
(2)
where fXTAL is the crystal frequency, M is the PLL
feedback-divider and N is the PLL post-divider. The input
frequency and the selection of the feedback divider M is limited
by the VCO-frequency range. fXTAL and M must be configured
Assuming that a 16 MHz input frequency is used, equation (2)
reduces to:
fOUT = M ÷ N
(5)
Table 7. MPC9229 Frequency Operating Range
Freescale Semiconductor, Inc...
VCO frequency for an crystal interface frequency of
M
M[8:0]
12
14
16
18
2
160
010100000
800
170
010101010
850
180
010110100
810
900
190
010111110
855
950
200
011001000
800
900
210
011010010
840
945
1000
200
100
50
25
1050
210
105
52.5
26.25
220
011011100
880
230
011100110
805
920
990
1100
220
110
55
27.50
1035
1150
230
115
57.5
28.75
240
011110000
840
960
250
011111010
875
100
1080
1200
240
120
60
30
1125
1250
250
125
62.5
31.25
260
100000100
910
270
100001110
810
945
1040
1170
1300
260
130
65
32.50
1080
1215
1350
270
135
67.5
33.75
280
100011000
840
290
100100010
870
980
1120
1260
1400
280
140
70
35
1015
1160
1305
1450
290
145
72.5
36.25
300
100101100
900
310
100110110
930
1050
1200
1350
1500
300
150
75
37.5
1085
1240
1395
1550
310
155
77.5
38.75
320
101000000
800
330
101001010
825
960
1120
1280
1440
1600
320
160
80
40
990
1155
1320
1485
330
165
82.5
41.25
340
101010100
850
350
101011110
875
1020
1190
1360
1530
340
170
85
42.5
1050
1225
1400
1575
350
175
87.5
43.75
360
101101000
370
101110010
900
1080
1260
1440
360
180
90
45
925
1110
1295
1480
370
185
92.5
46.25
380
390
101111100
950
1140
1330
1520
380
190
95
47.5
110000110
975
1170
1365
1560
390
195
97.5
48.75
400
410
110010000
1000
1200
1400
1600
400
200
100
50
110011010
1025
1230
1435
420
110100100
1050
1260
1470
430
110101110
1075
1290
1505
440
110111000
1100
1320
1540
450
111000010
1125
1350
1575
510
111111110
1275
1530
6
20
Output frequency for fXTAL=16 MHz and for N =
1
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Using the test and diagnosis output TEST
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. Although it is possible to select the node that
represents FOUT, the CMOS output is not able to toggle fast
enough for higher output frequencies and should only be used
for test and diagnosis. The T2, T1 and T0 control bits are
preset to ‘000’ when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter–free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter of the
PECL output pair. In normal operations, jitter specifications are
only guaranteed if the TEST output is static. The serial
configuration port can be used to select one of the alternate
functions for this pin. Most of the signals available on the TEST
output pin are useful only for performance verification of the
MPC9229 itself. However the PLL bypass mode may be of
interest at the board level for functional debug. When T[2:0] is
set to 110 the MPC9229 is placed in PLL bypass mode. In this
mode the S_CLOCK input is fed directly into the M and N
dividers. The N divider drives the FOUT differential pair and the
M counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving FOUT
directly gives the user more control on the test clocks sent
through the clock tree. Figure 6 shows the functional setup of
the PLL bypass mode. Because the S_CLOCK is a CMOS
level the input frequency is limited to 200 MHz. This means the
fastest the FOUT pin can be toggled via the S_CLOCK is 100
MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1).
Note that the M counter output on the TEST output will not be
a 50% duty cycle.
Table 8. Output Frequency Range for fXTAL = 16 MHz
N
FOUT
FOUT range
g
FOUT step
p
1
0
Value
0
0
1
M
200 - 400 MHz
1 MHz
0
1
2
M÷2
100 - 200 MHz
500 kHz
1
0
4
M÷4
50 - 100 MHz
250 kHz
1
1
8
M÷8
25 - 50 MHz
125 kHz
Freescale Semiconductor, Inc...
Example frequency calculation for an 16 MHz input
frequency
If an output frequency of 131 MHz was desired the following
steps would be taken to identify the appropriate M and N
values. According to Table 8, 131 MHz falls in the frequency
set by an value of 2 so N[1:0] = 01. For N = 2 the output
frequency is FOUT = M ÷ 2 and M = FOUT x 2. Therefore M =
2 x 131 = 262, so M[8:0] = 100000110. Following this
procedure a user can generate any whole frequency between
25 MHz and 400 MHz. Note than for N > 2 fractional values of
can be realized. The size of the programmable frequency
steps (and thus the indicator of the fractional output
frequencies achievable) will be equal to:
fSTEP = fXTAL ÷ 16 ÷ N
(6)
Using the parallel and serial interface
Table 9. Test and Debug Configuration for TEST
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW to HIGH transition will
latch the information present on the M[8:0] and N[1:0] inputs
into the M and N counters. When the P_LOAD signal is LOW
the input latches will be transparent and any changes on the
M[8:0] and N[1:0] inputs will affect the FOUT output pair. To
use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and the
M register with the final eight bits of the data stream on the
S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters. Figure
4 illustrates the timing diagram for both a parallel and a serial
load of the MPC9229 synthesizer. M[8:0] and N[1:0] are
normally specified once at power–up through the parallel
interface, and then possibly again through the serial interface.
This approach allows the application to come up at one
frequency and then change or fine–tune the clock as the ability
to control the serial interface becomes available.
TIMING SOLUTIONS
MPC9229
T[2:0]
TEST output
p
T2
T1
T0
0
0
0
14-bit shift register outa
0
0
1
Logic 1
0
1
0
fXTAL ÷ 16
0
1
1
M-Counter out
1
0
0
FOUT
1
0
1
Logic 0
1
1
0
M-Counter out in PLL-bypass mode
1
1
1
FOUT ÷ 4
a. Clocked out at the rate of S_CLOCK
Table 10. Debug Configuration for PLL bypassa
Output
Configuration
FOUT
S_CLOCK ÷ N
TEST
M-Counter outb
a. T[2:0]=110. AC specifications do not apply in PLL bypass
mode
b. clocked out at the rate of S_CLOCK÷(4⋅N)
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Freescale Semiconductor, Inc.
MPC9229
S_CLOCK
S_DATA
T2
S_LOAD
First
Bit
M[8:0]
N[1:0]
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M0
M1
Last
Bit
M, N
P_LOAD
Figure 4. Serial Interface Timing Diagram
Freescale Semiconductor, Inc...
Power Supply Filtering
The MPC9229 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCC_PLL pin impacts the device characteristics. The
MPC9229 provides separate power supplies for the digital
circuitry (VCC) and the internal PLL (VCC_PLL) of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively
sensitive internal analog phase–locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system environment
where it is more difficult to minimize noise on the power
supplies a second level of isolation may be required. The
simplest form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9229. Figure 5 illustrates a typical
power supply filter scheme. The MPC9229 is most susceptible
to noise with spectral content in the 1 kHz to 1 MHz range.
Therefore, the filter should be designed to target this range.
The key parameter that needs to be met in the final filter design
is the DC voltage drop that will be seen between the VCC
supply and the MPC9229 pin of the MPC9229. From the data
sheet, the VCC_PLL current (the current sourced through the
VCC_PLL pin) is maximum 20 mA, assuming that a minimum
of 2.835 V must be maintained on the VCC_PLL pin. The
resistor shown in Figure 5 must have a resistance of 10-15 Ω
to meet the voltage drop criteria. The RC filter pictured will
provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above 20 kHz.
As the noise frequency crosses the series resonant point of an
individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Generally, the resistor/capacitor
filter will be cheaper, easier to implement and provide an
adequate level of supply filtering. A higher level of attenuation
can be achieved by replacing the resistor with an appropriate
valued inductor. A 1000 µH choke will show a significant
impedance at 10 kHz frequencies and above. Because of the
current draw and the voltage that must be maintained on the
VCC_PLL pin, a low DC resistance inductor is required (less
than 15 Ω).
MOTOROLA
VCC
RF = 10-- 15 Ω
CF = 22 µF
VCC_PLL
C2
MPC9229
VCC
C1, C2 = 0.01...0.1 µF
C1
Figure 5. VCC PLL Power Supply Filter
Layout Recommendations
The MPC9229 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 6 shows a representative board layout for the
MPC9229. There exists many different potential board layouts
and the one pictured is but one. The important aspect of the
layout in Figure 6 is the low impedance connections between
VCC and GND for the bypass capacitors. Combining good
quality general purpose chip capacitors with good PCB layout
techniques will produce effective capacitor resonances at
frequencies adequate to supply the instantaneous switching
current for the MPC9229 outputs. It is imperative that low
inductance chip capacitors are used; it is equally important
that the board layout does not introduce back all of the
inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power
plane should be avoided and multiple large vias should be
used to tie the capacitors to the buried power planes. Fat
interconnect and large vias will help to minimize layout
induced inductance and thus maximize the series resonant
point of the bypass capacitors. Note the dotted lines circling
the crystal oscillator connection to the device. The oscillator is
a series resonant circuit and the voltage amplitude across the
crystal is relatively small. It is imperative that no actively
switching signals cross under the crystal as crosstalk energy
coupled to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on–board oscillator. Although the MPC9229
has several design features to minimize the susceptibility to
8
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
surface mount crystals are recommended, but not required.
Because the series resonant design is affected by capacitive
loading on the xtal terminals loading variation introduced by
crystals from different vendors could be a potential issue. For
crystals with a higher shunt capacitance it may be required to
place a resistance across the terminals to suppress the third
harmonic. Although typically not required it is a good idea to
layout the PCB with the provision of adding this external
resistor. The resistor value will typically be between 500 and
1KΩ.
The oscillator circuit is a series resonant circuit and thus for
optimum performance a series resonant crystal should be
used. Unfortunately most crystals are characterized in a
parallel resonant mode. Fortunately there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result a parallel resonant crystal can be
used with the MPC9229 with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified, a few hundred ppm
translates to kHz inaccuracies. In a general computer
application this level of inaccuracy is immaterial. Table 11
below specifies the performance requirements of the crystals
to be used with the MPC9229.
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which overall
performance is being degraded due to system power supply
noise. The power supply filter and bypass schemes discussed
in this section should be adequate to eliminate power supply
noise related problems in most designs.
C1
C1
Freescale Semiconductor, Inc...
1
CF
C2
Xtal
= VCC
= GND
= Via
Table 11. Recommended Crystal Specifications
Parameter
Figure 6. PCB Board Layout Recommendation for
the PLCC28 Package
Using the On--Board Crystal Oscillator
The MPC9229 features a fully integrated on--board crystal
oscillator to minimize system implementation costs. The
oscillator is a series resonant, multivibrator type design as
opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs the user is advised
to mount the crystal as close to the MPC9229 as possible to
avoid any board level parasitics. To facilitate co--location
TIMING SOLUTIONS
MPC9229
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150pm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5--7pF
Equivalent Series Resistance (ESR)
50 to 80Ω
Correlation Drive Level
100µW
Aging
5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
9
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MOTOROLA
Freescale Semiconductor, Inc.
MPC9229
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776--02
ISSUE D
- N--
0.007 (0.180)
B
Y BRK
T L-- M
M
0.007 (0.180)
U
M
N
S
T L-- M
S
S
N
S
D
Z
- M--
Freescale Semiconductor, Inc...
- L--
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L-- M
S
T L-- M
N
S
J
0.007 (0.180)
H
S
S
N
M
T L-- M
N
S
S
K1
- T--
K
SEATING
PLANE
F
VIEW S
G1
T L-- M
N
S
S
0.004 (0.100)
G
0.007 (0.180)
M
T L-- M
S
N
S
VIEW S
S
NOTES:
1. DATUMS - L-- , - M-- , AND - N-- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM - T-- , SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MOTOROLA
S
N
E
S
T L-- M
S
VIEW D-- D
Z
0.010 (0.250)
0.010 (0.250)
G1
10
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2_
10_
0.410
0.430
0.040
---
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2_
10_
10.42
10.92
1.02
---
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9229
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-03
ISSUE B
4X
0.20 H A-- B D
6
D1
e/2
D1/2
PIN 1 INDEX
32
3
25
1
A
E1/2
F
B
Freescale Semiconductor, Inc...
6 E1
E
4
F
DETAIL G
17
8
9
7
E/2
DETAIL G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-- mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-- mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-- mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-- mm AND
0.25-- mm FROM THE LEAD TIP.
D
D/2
4
D
4X
0.20 C A-- B D
H
SEATING
PLANE
28X
e
C
32X
0.1 C
DETAIL AD
BASE
METAL
PLATING
b1
c
8X
c1
b
( θ1_)
0.20
R R2
A2
0.25
GAUGE PLANE
A1
(S)
L
θ_
(L1)
DETAIL AD
TIMING SOLUTIONS
M
11
5
C A-- B D
SECTION F-- F
R R1
A
A, B, D
8
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
θ
θ1
R1
R2
S
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MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
0_
7_
12 _REF
0.08
0.20
0.08
--0.20 REF
MOTOROLA
Freescale Semiconductor, Inc...
MPC9229
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective
owners.
E Motorola Inc. 2003
HOW TO REACH US:
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
852--26668334
USA/EUROPE/LOCATIONS NOT LISTED:
TECHNICAL INFORMATION CENTER:
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JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center,
3--20--1, Minami--Azabu, Minato--ku, Tokyo 106--8573 Japan
81--3--3440--3569
MOTOROLA
HOME PAGE: http://motorola.com/semiconductors
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12
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MPC9229/D
TIMING
SOLUTIONS