MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Preliminary Information 900 MHz Low Voltage LVDS Clock Synthesizer The MPC9259 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 900 MHz and the support of differential LVDS output signals the device meets the needs of the most demanding clock applications. Order Number: MPC9259/D Rev 0, 12/2002 MPC9259 900 MHZ LOW VOLTAGE CLOCK SYNTHESIZER Features Freescale Semiconductor, Inc... • 50 MHz to 900 MHz synthesized clock output signal • Differential LVDS output • LVCMOS compatible control inputs • On-chip crystal oscillator for reference frequency generation • Alternative LVCMOS compatible reference input • 3.3V power supply • Fully integrated PLL • Minimal frequency overshoot FA SUFFIX 32–LEAD LQFP PACKAGE CASE 873A • Serial 3-wire programming interface • Parallel programming interface for power-up • 32 Pin LQFP Package • SiGe Technology • Ambient temperature range 0°C to + 70° C Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Motorola, Inc. 2002 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC9259 XTAL_IN XTAL_OUT XTAL 1 ÷2 10-20 MHz Ref PLL 0 FREF_EXT ÷1 ÷2 ÷4 ÷8 ÷2 VCO 800 – 1800 MHz VCC ÷0 to ÷127 7-Bit M-Divider 1 OE 0 ÷2 FOUT FOUT TEST Test 2 3 N-Latch T-Latch 9 VCC M-Latch LE P/S 0 1 0 1 Bit 3-4 Bit 11-5 S_DATA S_CLOCK Bit 0-2 12 Bit Shift Register VCC M[0:6] N[1:0] PWR_DOWN OE NC N[1] N[0] NC XTAL_SEL M[6] M[5] M[4] Figure 1. MPC9259 Logic Diagram 24 23 22 21 20 19 18 17 GND 25 16 NC TEST 26 15 M[3] VCC 27 14 M[2] VCC 28 13 M[1] GND 29 12 M[0] FOUT 30 11 P_LOAD FOUT 31 10 OE VCC 32 MPC9259 2 3 4 5 6 7 8 S_DATA S_LOAD VCC_PLL VCC_PLL PWR_DOWN FREF_EXT XTAL_IN 9 1 S_CLOCK Freescale Semiconductor, Inc... ÷16 FB XTAL_SEL P_LOAD S_LOAD 11 00 01 10 XTAL_OUT Figure 2. MPC9259 32–Lead LQFP Pinout (Top View) MOTOROLA For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9259 Table 1. Pin Configuration Pin I/O Default XTAL_IN, XTAL_OUT Freescale Semiconductor, Inc... FREF_EXT Type Function Analog Input 0 FOUT, FOUT Output TEST Output Crystal oscillator interface LVCMOS Alternative PLL reference input LVDS Differential clock output LVCMOS Test and device diagnosis output XTAL_SEL Input 1 LVCMOS PLL reference select input PWR_DOWN Input 0 LVCMOS Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. S_LOAD Input 0 LVCMOS Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. P_LOAD Input 1 LVCMOS Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. S_DATA Input 0 LVCMOS Serial configuration data input. S_CLOCK Input 0 LVCMOS Serial configuration clock input. M[0:6] Input 1 LVCMOS Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. N[1:0] Input 1 LVCMOS Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD OE Input 1 LVCMOS Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state (FOUT = L, FOUT = H). GND Supply Ground VCC Supply VCC Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. VCC_PLL Supply VCC PLL positive power supply (analog power supply). Table 2. Output frequency range and PLL Post-divider N PWR_DOWN TIMING SOLUTIONS N VCO Output f di i i frequency division FOUT frequency range 1 0 0 0 0 2 200 - 450 MHz 0 0 1 4 100 - 225 MHz 0 1 0 8 50 - 112.5 MHz 0 1 1 1 400 - 900 MHz 1 0 0 32 12.5 - 28.125 MHz 1 0 1 64 6.25 - 14.0625 MHz 1 1 0 128 3.125 - 7.03125 MHz 1 1 1 16 25 - 56.25 MHz For More Information On This Product, 3 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9259 Table 3. Function Table Input 0 1 XTAL_SEL FREF_EXT XTAL interface OE Outputs disabled. FOUT is stopped in the logic low state (FOUT = L, FOUT = H) Outputs enabled PWR_DOWN Output divider ÷ 1 Output divider ÷16 Table 4. General Specifications Freescale Semiconductor, Inc... Symbol Characteristics Min Typ Max Unit MM ESD protection (Machine model) 200 HBM ESD protection (Human body model) 2000 V LU Latch-up immunity 200 mA CIN Input capacitance Condition V 4.0 pF Inputs Table 5. Absolute Maximum Ratingsa Symbol Min Max Unit VCC Supply Voltage -0.3 3.9 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 V DC Input Current ±20 mA DC Output Current ±50 mA VOUT IIN IOUT a Characteristics Condition TS Storage temperature -65 125 °C Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. MOTOROLA For More Information On This Product, 4 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9259 Table 6. DC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to + 70°C)a Symbol Characteristics Min Typ Max Unit Condition LVCMOS control inputs (FREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:6], N[0:1], OE) VIH Input high voltage VIL Input low voltage IIN Input Currentb 2.0 VCC + 0.3 V LVCMOS 0.8 V LVCMOS ±200 µA VIN = VCC or GND mV LVDS mV LVDS Differential clock output FOUT VPP Output Differential Voltage (peak–to–peak) 250 VOS Output Offset Voltage 1125 1275 Freescale Semiconductor, Inc... Test and diagnosis output TEST VOH Output High Voltage VOL Output Low Voltage 2.0 V IOH =-0.8 mA 0.55 V IOL = 0.8 mA 20 mA VCC_PLL Pins 110 mA All VCC Pins Supply current ICC_PLL a. b. Maximum PLL Supply Current ICC Maximum Supply Current All AC characteristics are design targets and subject to change upon device characterization. Inputs have pull-down resistors affecting the input current. Table 7. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to + 70°C)a Symbol Unit 20 MHz 800 1800 MHz 400 200 100 50 900 450 225 112.5 MHz MHz MHz MHz Serial interface programming clock frequencyc 0 10 MHz Minimum pulse width 50 fVCO VCO frequency rangeb fMAX Output Frequency tP,MIN DC Output duty cycle tr, tf Output Rise/Fall Time Min N = 11 (÷1) N = 00 (÷2) N = 01 (÷4) N = 10 (÷8) (S_LOAD, P_LOAD) 45 Typ 0.05 55 % TBD ns Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD 20 20 20 ns ns ns tS Hold Time S_DATA to S_CLOCK M, N to P_LOAD 20 20 ns ns tJIT(PER) Cycle-to-cycle jitter Period Jitter RMS (1 σ)d Condition PWR_DOWN = 0 ns 50 tS tJIT(CC) d. Max 10 Crystal interface frequency range fS_CLOCK a. b. c. Characteristics fXTAL TBD RMS (1 σ) TBD ps ±25 ps 20% to 80% tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ 2 ⋅ M. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See application section for more details. See application section for a jitter calculation for other confidence factors than 1 σ. TIMING SOLUTIONS For More Information On This Product, 5 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9259 Table 8. MPC9259 Frequency Operating Range (in MHz) Freescale Semiconductor, Inc... VCO frequency for an crystal interface frequency of M M[6:0] 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 20 0010100 800 21 0010101 840 22 0010110 880 Output frequency for fXTAL=16 MHz and for N = 1 2 4 8 23 0010111 828 24 0011000 864 960 25 0011001 800 900 1000 400 200 100 50 26 0011010 832 936 1040 416 208 104 52 27 0011011 864 972 1080 432 216 108 54 28 0011100 812 896 1008 1120 448 224 112 56 29 0011101 840 928 1044 1160 464 232 116 58 30 0011110 875 960 1080 1200 480 240 120 60 31 0011111 868 992 1116 1240 496 248 124 62 32 0100000 896 1024 1152 1280 512 256 128 64 33 0100001 924 1056 1188 1320 528 264 132 66 34 0100010 816 952 1088 1224 1360 544 272 136 68 35 0100011 840 980 1120 1260 1400 560 280 140 70 36 0100100 864 1008 1152 1296 1440 576 288 144 72 37 0100101 888 1036 1184 1332 1480 592 296 148 74 38 0100110 912 1064 1216 1368 1520 608 304 152 76 39 0100111 936 1092 1248 1404 1560 624 312 156 78 40 0101000 800 960 1120 1280 1440 1600 640 320 160 80 41 0101001 820 984 1148 1312 1476 1640 656 328 164 82 42 0101010 840 1008 1176 1344 1512 1680 672 336 168 84 43 0101011 860 1032 1204 1376 1548 1720 688 344 172 86 44 0101100 880 1056 1232 1408 1584 1760 704 352 176 88 45 0101101 900 1080 1260 1440 1620 1800 720 360 180 90 46 0101110 920 1104 1288 1472 1656 736 368 184 92 47 0101111 940 1128 1316 1504 1692 752 376 188 94 48 0110000 960 1152 1344 1536 1728 768 384 192 96 49 0110001 980 1176 1372 1568 1764 784 392 196 98 50 0110010 1000 1200 1400 1600 1800 800 400 200 100 51 0110011 1020 1224 1428 1632 816 408 204 102 52 0110100 1040 1248 1456 1664 832 416 208 104 53 0110101 1060 1272 1484 1696 848 424 212 106 54 0110110 1080 1296 1512 1728 864 432 216 108 55 0110111 1100 1320 1540 1760 880 440 220 110 56 0111000 1120 1344 1568 1792 896 448 224 112 57 0111001 1140 1368 1596 58 0111010 1160 1392 1624 59 0111011 1180 1416 1652 60 0111100 1200 1440 1680 61 0111101 1220 1488 1736 62 0111110 1260 1512 1764 63 0111111 1260 1512 1764 64 1000000 1280 1536 1792 ... ... ... ... MOTOROLA 920 For More Information On This Product, 6 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9259 Programming the MPC9259 Using the parallel and serial interface Programming the MPC9259 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 3 illustrates the timing diagram for both a parallel and a serial load of the MPC9259 synthesizer. M[6:0] and N[1:0] are normally specified once at power–up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine–tune the clock as the ability to control the serial interface becomes available. Freescale Semiconductor, Inc... fOUT = (fXTAL ÷ 2) ⋅ (M ⋅ 4) ÷ (N ⋅ 2) or fOUT = fXTAL ⋅ M ÷ N (1) (2) where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 800 to 1800 MHz in order to achieve stable PLL operation: MMIN = fVCO,MIN ÷ (2⋅fXTAL) and MMAX = fVCO,MAX ÷ (2⋅fXTAL) (3) (4) For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = 16 M ÷ N (5) Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 16 MHz N FOUT FOUT range FOUTstep 1 0 Value 0 0 2 8⋅M 200-450 MHz 8 MHz 0 1 4 4⋅M 100-225 MHz 4 MHz 1 0 8 2⋅M 50-112.5 MHz 2 MHz 1 1 1 16⋅M 400-900 MHz 16 MHz Example calculation for an 16 MHz input frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, FOUT = 8⋅M and M = FOUT÷8. Therefore, M = 384 ÷ 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: fSTEP = fXTAL ÷ N TIMING SOLUTIONS (6) Using the test and diagnosis output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and dignosis. The T2, T1 and T0 control bits are preset to ‘000’ when P_LOAD is LOW so that the PECL FOUT outputs are as jitter–free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9259 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9259 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clocktree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. For More Information On This Product, 7 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9259 Table 11. Debug Configuration for PLL bypassa Table 10. Test and Debug Configuration for TEST T[2:0] T2 Freescale Semiconductor, Inc... T0 0 0 0 12-bit shift register outa 0 0 1 Logic 1 a. 0 1 0 fXTAL ÷ 2 b. 0 1 1 M-Counter out 1 0 0 FOUT 1 0 1 Logic 0 1 1 0 M-Counter out in PLL-bypass mode 1 a. T1 Configuration Output TEST output FOUT S_CLOCK ÷ N TEST M-Counter outb T[2:0] = 110. AC specifications do not apply in PLL bypass mode Clocked out at the rate of S_CLOCK ÷ (2⋅N) 1 1 FOUT ÷ 4 Clocked out at the rate of S_CLOCK S_CLOCK S_DATA T2 S_LOAD First Bit M[6:0] N[1:0] T1 T0 N1 N0 M6 M5 M4 M3 M2 M0 M1 Last Bit M, N P_LOAD Figure 3. Serial Interface Timing Diagram Power Supply Filtering The MPC9259 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC9259 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase–locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9259. Figure 4 illustrates a typical power supply filter scheme. The MPC9259 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9259 pin of the MPC9259. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is typically TBD mA (TBD maximum), assuming that a minimum of 3.135V must be maintained on the VCC_PLL pin, very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 4 must have a resistance of TBD Ω to MOTOROLA meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 µH choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than TBD Ω). R1 = TBD Ω R1 C3 = TBD µF C2 = 10 nF VCC_PLL VCC C3 MPC9259 VCC C1 = 33...100 nF Figure 4. VCC_PLL Power Supply Filter For More Information On This Product, 8 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9259 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE H W K X DETAIL AD TIMING SOLUTIONS Q_ 0.250 (0.010) C E GAUGE PLANE Freescale Semiconductor, Inc... P NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X For More Information On This Product, 9 Go to: www.freescale.com MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MOTOROLA Freescale Semiconductor, Inc. MPC9259 Freescale Semiconductor, Inc... NOTES MOTOROLA For More Information On This Product, 10 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9259 Freescale Semiconductor, Inc... NOTES TIMING SOLUTIONS For More Information On This Product, 11 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MPC9259 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. E Motorola, Inc. 2002. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T. Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ More Information For On This Product, 12 Go to: www.freescale.com MPC9259/D TIMING SOLUTIONS