MOTOROLA MC12429

MOTOROLA
Order this document
by MC12429/D
SEMICONDUCTOR TECHNICAL DATA
High Frequency Clock
Synthesizer
The MC12429 is a general purpose synthesized clock source. Its
internal VCO will operate over a range of frequencies from 200 to
400MHz. The differential PECL output can be configured to be the VCO
frequency divided by 1, 2, 4, or 8. With the output configured to divide the
VCO frequency by 1, and with a 16.000MHz external quartz crystal used
to provide the reference frequency, the output frequency can be specified
in 1MHz steps. The PLL loop filter is fully integrated so that no external
components are required. The output frequency is configured using a
parallel or serial interface.
•
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MC12429
HIGH FREQUENCY PLL
CLOCK SYNTHESIZER
25 to 400MHz Differential PECL Outputs
±25ps Peak–to–Peak Output Jitter
Fully Integrated Phase–Locked Loop
FN SUFFIX
28–LEAD PLCC PACKAGE
CASE 776–02
Minimal Frequency Over–Shoot
Synthesized Architecture
Serial 3–Wire Interface
Parallel Interface for Power–Up
Quartz Crystal Interface
28–Lead PLCC and 32–Lead LQFP Packages
Operates from 3.3V or 5.0V Power Supply
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
Functional Description
The internal oscillator uses the external quartz crystal as the basis of
its frequency reference. The output of the reference oscillator is divided
by 16 before being sent to the phase detector. With a 16MHz crystal, this
provides a reference frequency of 1MHz. Although this data sheet
illustrates functionality only for a 16MHz crystal, any crystal in the
10–25MHz range can be used.
The VCO within the PLL operates over a range of 200 to 400MHz. Its output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or
8). This divider extends performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated
in 50Ω to VCC – 2.0V. The positive reference for the output driver and the internal logic is separated from the power supply for the
phase–locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
06/01
 Motorola, Inc. 2001
1
REV 7
MC12429
VCC
FOUT
25
24
FOUT GND
22
23
VCC
TEST GND
21
20
19
S_CLOCK
26
18
N[1]
S_DATA
27
17
N[0]
S_LOAD
28
16
M[8]
PLL_VCC
1
15
M[7]
NC
2
14
M[6]
NC
3
13
M[5]
XTAL1
4
12
M[4]
28–Lead PLCC
5
XTAL2
6
7
8
OE P_LOAD M[0]
9
10
11
M[1]
M[2]
M[3]
N[1:0]
Output Division
00
01
10
11
1
2
4
8
Figure 1. 28–Lead (Top View)
VCC FOUT FOUT GND
32
31
30
29
VCC
Vcc
28
27
TEST GND
26
25
S_CLOCK
1
24
N/C
S_DATA
2
23
N[1]
S_LOAD
3
22
N[0]
PLL–VCC
4
21
M[8]
PLL–Vcc
5
20
M[7]
N/C
6
19
M[6]
N/C
7
18
M[5]
XTAL1
8
17
M[4]
32–Lead LQFP
9
10
11
12
XTAL2 OE P_LOAD M[0]
13
14
15
16
M[1]
M[2]
M[3]
N/C
Figure 2. 32–Lead Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
MC12429
PIN DESCRIPTIONS
Pin Name
Function
Inputs
XTAL1, XTAL2
These pins form an oscillator when connected to an external series–resonant crystal.
S_LOAD
(Int. Pulldown)
This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent when this
signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper operation.
S_DATA
(Int. Pulldown)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK
(Int. Pulldown)
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.
P_LOAD
(Int. Pullup)
This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent when this
signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD for proper operation.
P_LOAD is state sensitive.
M[8:0]
(Int. Pullup)
These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of P_LOAD. M[8]
is the MSB, M[0] is the LSB.
N[1:0]
(Int. Pullup)
These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition of
P_LOAD.
OE
(Int. Pullup)
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the FOUT output.
Outputs
FOUT, FOUT
These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.
TEST
The function of this output is determined by the serial configuration bits T[2:0].
Power
VCC
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or 5.0V
(VCC = PLL_VCC). Current drain through VCC ≈ 85mA.
PLL_VCC
This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This supply is
connected to +3.3V or 5.0V (VCC = PLL_VCC). Current drain through PLL_VCC ≈ 15mA.
GND
These pins are the negative supply for the chip and are normally all connected to ground.
TIMING SOLUTIONS
3
MOTOROLA
MC12429
+3.3 or 5.0V
1MHz
FREF
DIV 16
4
16MHz
PHASE
DETECTOR
+3.3 or 5.0V
VCO
VCC0
25
XTAL1
9–BIT DIV M
COUNTER
OSC
5
PLL_VCC
200–400
MHz
XTAL2
24
23
DIV N
(1, 2, 4, 8)
20
6
OE
LATCH
FOUT
FOUT
TEST
LATCH
28
S_LOAD
LATCH
7
P_LOAD
0
27
S_DATA
1
0
9–BIT SR
1
2–BIT SR
3–BIT SR
26
S_CLOCK
VCC1
21
8
17, 18
16
+3.3 or 5.0V
22, 19
9
2
M[8:0]
N[1:0]
Figure 3. MC12429 Block Diagram (28–Lead PLCC Pinout)
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring
the internal dividers to produce the desired frequency at the
outputs. The output frequency can by represented by this
formula:
FOUT = (FXTAL ÷ 16) x M ÷ N
From these ranges the user will establish the value of N
required, then the value of M can be calculated based on the
appropriate equation above. For example if an output
frequency of 131MHz was desired the following steps would
be taken to identify the appropriate M and N values. 131MHz
falls within the frequency range set by an N value of 2 so N
[1:0] = 01. For N = 2 FOUT = M ÷ 2 and M = 2 x FOUT.
Therefore M = 131 x 2 = 262, so M[8:0] = 100000110.
Following this same procedure a user can generate any
whole frequency desired between 25 and 400MHz. Note that
for N > 2 fractional values of FOUT can be realized. The size
of the programmable frequency steps (and thus the indicator
of the fractional output frequencies acheivable) will be equal
to FXTAL ÷ 16 ÷ N.
(1)
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200 ≤ M ≤ 400 for a 16MHz input reference.
Assuming that a 16MHz reference frequency is used the
above equation reduces to:
FOUT = M ÷ N
For input reference frequencies other than 16MHz the set
of appropriate equations can be deduced from equation 1.
For computer applications another useful frequency base
would be 16.666MHz. From this reference one can generate
a family of output frequencies at multiples of the 33.333MHz
PCI clock. As an example to generate a 133.333MHz clock
from a 16.666MHz reference the following M and N values
would be used:
Substituting the four values for N (1, 2, 4, 8) yields:
TABLE A: Output Frequency Range
N
FOUT
1
2
4
8
M
M/2
M/4
M/8
MOTOROLA
OUTPUT FREQUENCY RANGE
200 – 400 MHZ
100 – 200 MHZ
50 – 100 MHZ
25 – 50 MHZ
FOUT = 16.666 ÷ 16 x M ÷ N = 1.0416 x M ÷ N
4
TIMING SOLUTIONS
MC12429
Let N = 2, M = 133.3333 ÷ 1.0416 x 2 = 256
that represents FOUT, the CMOS output may not be able to
toggle fast enough for some of the higher output frequencies.
The T2, T1 and T0 control bits are preset to ‘000’ when
P_LOAD is LOW so that the PECL FOUT outputs are as
jitter–free as possible. Any active signal on the TEST output
pin will have detrimental affects on the jitter of the PECL
output pair. In normal operations, jitter specifications are only
guaranteed if the TEST output is static. The serial
configuration port can be used to select one of the alternate
functions for this pin.
The value for M falls within the constraints set for PLL
stability, therefore N[1:0] = 01 and M[8:0} = 10000000. If the
value for M fell outside of the valid range a different N value
would be selected to try to move M in the appropriate
direction.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW to HIGH transition
will latch the information present on the M[8:0] and N[1:0]
inputs into the M and N counters. When the P_LOAD signal is
LOW the input latches will be transparent and any changes
on the M[8:0] and N[1:0] inputs will affect the FOUT output
pair. To use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and
the M register with the final eight bits of the data stream on
the S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin
after the shift register is fully loaded will transfer the divide
values into the counters. The HIGH to LOW transition on the
S_LOAD input will latch the new divide values into the
counters. Figure 4 illustrates the timing diagram for both a
parallel and a serial load of the MC12429 synthesizer.
Most of the signals available on the TEST output pin are
useful only for performance verification of the MC12429
itself. However the PLL bypass mode may be of interest at
the board level for functional debug. When T[2:0] is set to 110
the MC12429 is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers. The
N divider drives the FOUT differential pair and the M counter
drives the TEST output pin. In this mode the S_CLOCK input
could be used for low speed board level functional test or
debug. Bypassing the PLL and driving FOUT directly gives
the user more control on the test clocks sent through the
clock tree. Figure 5 shows the functional setup of the PLL
bypass mode. Because the S_CLOCK is a CMOS level the
input frequency is limited to 250MHz or less. This means the
fastest the FOUT pin can be toggled via the S_CLOCK is
125MHz as the minimum divide ratio of the N counter is 2.
Note that the M counter output on the TEST output will not be
a 50% duty cycle due to the way the divider is implemented.
M[8:0] and N[1:0] are normally specified once at power–up
through the parallel interface, and then possibly again
through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine–tune the clock as the ability to control the serial interface
becomes available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. Although it is possible to select the node
T2
T1
T0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TEST (Pin 20)
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
FOUT
LOW
MCNT
FOUT/4
S_CLOCK
S_DATA
T2
S_LOAD
First
Bit
M[8:0]
N[1:0]
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
Last
Bit
M, N
P_LOAD
Figure 4. Timing Diagram
TIMING SOLUTIONS
5
MOTOROLA
MC12429
FREF
MCNT
VCO
PLL 12429
0
SCLOCK
FOUT
(VIA ENABLE GATE)
N DIVIDE
(2, 4, 8, 16)
1
SEL_CLK
M COUNTER
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
LATCH
SDATA
SHIFT
REG
14–BIT
Reset
SLOAD
PLOADB
T0
T1
T2
7
TEST
MUX
TEST
0
DECODE
• T2=T1=1, T0=0: Test Mode (PLL bypass)
• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
Figure 5. Serial Test Clock Block Diagram (PLL bypass)
DC CHARACTERISTICS (VCC = 3.3V ±5%)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
2.2
Min
Typ
70°C
Max
2.2
Min
Typ
Max
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
0.8
0.8
V
IIN
Input Current
1.0
1.0
1.0
mA
VOH
Output HIGH Voltage
TEST
VOL
Output LOW Voltage
TEST
VOH
Output HIGH Voltage1. FOUT, FOUT
2.28
2.60
2.32
2.49
VOL
Output LOW Voltage1. FOUT, FOUT
1.35
1.67
1.35
1.67
ICC
Power Supply Current
2.5
2.2
Unit
2.5
VCC
PLL_VCC
85
15
V
2.5
0.4
V
IOH = –0.8mA
0.4
V
IOL = 0.8mA
2.38
2.565
V
VCCO = 3.3V2.
1.35
1.70
V
VCCO = 3.3V2.
100
20
mA
Max
Unit
0.4
100
20
85
15
Condition
100
20
85
15
1. 50Ω to VCC – 2.0V termination.
2. Output levels will vary 1:1 with VCC0 variation.
DC CHARACTERISTICS (VCC = 5.0V ±5%)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
3.5
Min
Typ
70°C
Max
Typ
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
0.8
0.8
V
IIN
Input Current
1.0
1.0
1.0
mA
VOH
Output HIGH Voltage
TEST
VOL
Output LOW Voltage
TEST
VOH
Output HIGH Voltage1. FOUT, FOUT
3.98
4.30
4.02
4.19
VOL
Output LOW Voltage1. FOUT, FOUT
3.05
3.37
3.05
3.37
ICC
Power Supply Current
VCC
PLL_VCC
3.5
Min
2.5
3.5
2.5
85
15
100
20
V
2.5
0.4
V
IOH = –0.8mA
0.4
V
IOL = 0.8mA
4.08
4.265
V
3.05
3.40
V
VCCO = 5.0V2.
VCCO = 5.0V2.
100
20
mA
0.4
85
15
100
20
Condition
85
15
1. 50Ω to VCC – 2.0V termination.
2. Output levels will vary 1:1 with VCC0 variation.
MOTOROLA
6
TIMING SOLUTIONS
MC12429
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V ±5%)
Symbol
FMAXI
Characteristic
Maximum Input Frequency
Min
Max
Unit
Condition
S_CLOCK
Xtal Oscillator
10
20
MHz
Note 3.
10
VCO (Internal)
FOUT
200
25
400
400
MHz
Note 4.
FMAXO
Maximum Output Frequency
tLOCK
Maximum PLL Lock Time
10
ms
tjitter
Period Deviation (Peak–to–Peak)
±25
ps
ts
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
th
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
tpwMIN
Minimum Pulse Width
S_LOAD
P_LOAD
50
50
ns
Note 4.
tr, tf
Output Rise/Fall
FOUT
300
ps
20%–80%, Note 4.
800
Note 4.,
See Applications Section
3. 10MHz is the maximum frequency to load the feedback devide registers. S_CLOCK can be switched at higher frequencies when used as a
test clock in TEST_MODE 6.
4. 50Ω to VCC – 2.0V pulldown.
APPLICATIONS INFORMATION
characterized. As a result a parallel resonant crystal can be
used with the MC12429 with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified, a few hundred ppm
translates to kHz inaccuracies. In a general computer
application this level of inaccuracy is immaterial. Table 1
below specifies the performance requirements of the crystals
to be used with the MC12429.
Using the On–Board Crystal Oscillator
The MC12429 features a fully integrated on–board crystal
oscillator to minimize system implementation costs. The
oscillator is a series resonant, multivibrator type design as
opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs the user is
advised to mount the crystal as close to the MC12429 as
possible to avoid any board level parasitics. To facilitate
co–location surface mount crystals are recommended, but
not required. Because the series resonant design is affected
by capacitive loading on the xtal terminals loading variation
introduced by crystals from different vendors could be a
potential issue. For crystals with a higher shunt capacitance it
may be required to place a resistance across the terminals to
suppress the third harmonic. Although typically not required it
is a good idea to layout the PCB with the provision of adding
this external resistor. The resistor value will typically be
between 500 and 1KΩ.
Table 1. Recommended Crystal Specifications
Parameter
The oscillator circuit is a series resonant circuit and thus
for optimum performance a series resonant crystal should be
used. Unfortunately most crystals are characterized in a
parallel resonant mode. Fortunately there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
TIMING SOLUTIONS
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150pm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR)
50 to 80Ω
Correlation Drive Level
100µW
Aging
5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
7
MOTOROLA
MC12429
inductor is required (less than 15Ω). Generally the
resistor/capacitor filter will be cheaper, easier to implement
and provide an adequate level of supply filtering.
The MC12429 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 7 shows a representaive board layout for the
MC12429. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 7 is the low impedance connections
between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors with
good PCB layout techniques will produce effective capacitor
resonances at frequencies adequate to supply the
instantaneous switching current for the 12429 outputs. It is
imperative that low inductance chip capacitors are used; it is
equally important that the board layout does not introduce
back all of the inductance saved by using the leadless
capacitors. Thin interconnect traces between the capacitor
and the power plane should be avoided and multiple large
vias should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
Power Supply Filtering
The MC12429 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MC12429 provides separate
power supplies for the digital ciruitry (VCC) and the internal
PLL (PLL_VCC) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the PLL_VCC pin for the MC12429.
Figure 6 illustrates a typical power supply filter scheme.
The MC12429 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the
PLL_VCC pin of the MC12429. From the data sheet the
IPLL_VCC current (the current sourced through the PLL_VCC
pin) is typically 15mA (20mA maximum), assuming that a
minimum of 3.0V must be maintained on the PLL_VCC pin
very little DC voltage drop can be tolerated when a 3.3V VCC
supply is used. The resistor shown in Figure 6 must have a
resistance of 10–15Ω to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20KHz. As the noise frequency crosses the
series resonant point of an individual capacitor it’s overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL.
3.3V or
5.0V
C1
ÉÉ
ÉÉ
L=1000µH
R=15Ω
1
C3
C2
ÉÉ
ÉÉ
= VCC
= GND
= Via
22µF
Figure 7. PCB Board Layout for MC12429 (28 PLCC)
0.01µF
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the device.
Special attention should be paid to the layout of the crystal to
ensure a stable, jitter free interface between the crystal and
the on–board oscillator. Note the provisions for placing a
resistor across the crystal oscillator terminals as discussed in
the crystal oscillator section of this data sheet.
Although the MC12429 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
VCC
0.01µF
Figure 6. Power Supply Filter
A higher level of attenuation can be acheived by replacing
the resistor with an appropriate valued inductor. Figure 6
shows a 1000µH choke, this value choke will show a
significant impedance at 10KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_VCC pin a low DC resistance
MOTOROLA
C1
R1
Xtal
PLL_VCC
MC12429
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
R1 = 10–15Ω
C1 = 0.01µF
C2 = 22µF
C3 = 0.01µF
3.3V or
5.0V
RS=10–15Ω
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
8
TIMING SOLUTIONS
MC12429
The typical method of measuring the jitter is to accumulate
a large number of cycles, create a histogram of the edge
placements and record peak–to–peak as well as standard
deviations of the jitter. Care must be taken that the measured
edge is the edge immediately following the trigger edge. All of
the jitter data reported on the MC12429 was collected in this
manner.
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
Jitter Performance of the MC12429
The MC12429 exhibits long term and cycle–to–cycle jitter
which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility one gets with a
synthesizer over a fixed frequency oscillator.
Figure 9 shows the jitter as a function of the output
frequency. For the 12429 this information is probably of more
importance. The flat line represents an RMS jitter value that
corresponds to an 8 sigma ±25ps peak–to–peak long term
period jitter. The graph shows that for output frequencies
from 87.5 to 400MHz the jitter falls within the ±25ps
peak–to–peak specification. The general trend is that as the
output frequency is decreased the output edge jitter will
increase.
25
N=1
N=2
N=4
N=8
15
25
20
10
RMS Jitter (ps)
RMS Jitter (ps)
20
5
0
200
15
6.25ps Reference
10
5
250
300
350
400
0
VCO Frequency (MHz)
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
Figure 8. RMS PLL Jitter versus VCO Frequency
Output Frequency (MHz)
Figure 9. RMS Jitter versus Output Frequency
Figure 8 illustrates the RMS jitter performance of the
MC12429 across its specified VCO frequency range. Note
that the jitter is a function of both the output frequency as well
as the VCO frequency, however the VCO frequency shows a
much stronger dependence. The data presented has not
been compensated for trigger jitter, this fact provides a
measure of guardband to the reported data.
TIMING SOLUTIONS
The jitter data presented should provide users with
enough information to determine the effect on their overall
timing budget. The jitter performance meets the needs of
most system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.
9
MOTOROLA
MC12429
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
B
T L–M
M
N
S
T L–M
S
S
Y BRK
–N–
0.007 (0.180)
U
M
N
S
D
Z
–M–
–L–
W
28
D
X
G1
0.010 (0.250)
T L–M
S
N
S
S
V
1
VIEW D–D
A
0.007 (0.180)
R
0.007 (0.180)
M
T L–M
S
N
S
C
M
T L–M
S
N
0.007 (0.180)
H
Z
M
T L–M
N
S
S
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
–T–
T L–M
S
N
S
M
T L–M
S
N
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MOTOROLA
0.007 (0.180)
10
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10_
0.410
0.430
0.040
–––
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10_
10.42
10.92
1.02
–––
TIMING SOLUTIONS
MC12429
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
PLASTIC LQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
M
N
D
0.20 (0.008)
SEATING
PLANE
SECTION AE–AE
W
K
X
DETAIL AD
TIMING SOLUTIONS
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
11
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MOTOROLA
MC12429
Revision History
Revision
Min
Date
Rev 6
06/00
PECL VOH and VOL values in DC output characteristics table were changed from
100E to 10E (10H) style. Output levels represent a greater differential output swing
and reflect actual temperature dependency. PECL compatibility of output levels is
fully maintained. Control input VIH and VIL values in DC characteristic table were
changed. The control input logic threshold is approximately VCC/2. N–divider values
and reference frequency divider were updated on the datasheet to reflect actual
device architecture without affecting device functionality.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the
part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MOTOROLA
◊
12
TIMING
SOLUTIONS
MC12429/D