MOTOROLA MPC952

SEMICONDUCTOR TECHNICAL DATA
The MPC952 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree applications. The device
features a fully integrated PLL with no external components required.
With output frequencies of up to 180MHz and eleven low skew outputs
the MPC952 is well suited for high performance designs. The device
employs a fully differential PLL design to optimize jitter and noise
rejection performance. Jitter is an increasingly important parameter as
more microprocessors and ASiC’s are employing on chip PLL clock
distribution.
•
•
•
•
LOW VOLTAGE
PLL CLOCK DRIVER
Fully Integrated PLL
Output Frequency up to 180MHz
High Impedance Disabled Outputs
Compatible with PowerPC, Intel and High Performance RISC
Microprocessors
• Output Frequency Configurable
• TQFP Packaging
• ±100ps Cycle–to–Cycle Jitter
FA SUFFIX
TQFP PACKAGE
CASE 873A-02
The MPC952 features three banks of individually configurable outputs.
The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide
circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The
output frequency relationship is controlled by the fsel frequency control
pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL
compatible inputs.
The MPC952 uses external feedback to the PLL. This features allows
for the use of the device as a “zero delay” buffer. Any of the eleven
outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL
stability and jitter performance. The MR/OE pin allows the user to force the outputs into high impedance for board level test.
For system debug the PLL of the MPC952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the
design for debug purposes.
The outputs of the MPC952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.
For applications using series terminated transmission lines each MPC952 output can drive two lines. This capability provides an
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines
consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
2/98
 Motorola, Inc. 1998
1
REV 3
MPC952
Figure 1. MPC952 Logic Diagram
PLL_En
REFCLK
VCO
200–480MHz
PHASE
DETECTOR
÷4/÷6
÷2
Qa0
Qa1
FBin
Qa2
LPF
VCO_Sel
fsela
(Int Pull Down)
Qa3
(Int Pull Down)
Qa4
÷4/÷2
Qb0
Qb1
Qb2
fselb
(Int Pull Down)
Qb3
÷2/÷4
GNDO
Qa3
Qa4
VCCO
(Int Pull Down)
VCCO
Qb1
GNDO
MR/OE
Qc1
(Int Pull Down)
Qb0
fselc
Qc0
FUNCTION TABLES
24
23
22
21
20
19
18
17
VCCO
25
16
VCCO
Qb2
26
15
Qa2
Qb3
27
14
Qa1
GNDO
28
13
GNDO
GNDO
29
12
Qa0
Qc0
30
11
VCCI
Qc1
31
10
VCCA
VCCO
32
9
MPC952
8
FBin
7
GNDI
6
REFCLK
5
MR/OE
4
fsela
3
fselb
2
fselc
VCO_Sel
1
PLL_En
fsela
Qan
fselb
Qbn
fselc
Qcn
0
1
÷4
÷6
0
1
÷4
÷2
0
1
÷2
÷4
Control Pin
Logic ‘0’
Logic ‘1’
VCO_Sel
fVCO
fVCO/2
MR/OE
Output Enable
High Z
PLL_En
Enable PLL
Disable PLL
Pin Name
Description
VCCA
PLL Power Supply
VCCO
Output Buffer Power Supply
VCCI
Internal Core Logic Power Supply
GNDI
Internal Ground
GNDO
Output Buffer Ground
Figure 2. 32–Lead Pinout (Top View)
MOTOROLA
2
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MPC952
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
–40
125
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
VIH
Input HIGH Voltage
2.0
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
CIN
Input Capacitance
2.7
Cpd
Power Dissipation Capacitance
25
ICC
Maximum Quiescent Supply Current
Max
Unit
3.6
V
0.8
V
2.4
Condition
V
IOH = –20mA (Note 1.)
0.5
V
IOL = 20mA (Note 1.)
±120
µA
Note 2.
4
pF
pF
160
mA
Total ICC Static Current
ICCA
PLL Supply Current
15
20
mA
1. The MPC952 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
2. Inputs have pull–up, pull–down resistors which affect input current.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
tr, tf
TCLK Input Rise/Falls
fref
Reference Input Frequency
Min
Note 3.
Max
Unit
3.0
ns
Note 3.
MHz
frefDC
Reference Input Duty Cycle
25
75
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
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Condition
%
MOTOROLA
MPC952
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
tr, tf
Output Rise/Fall Time (Note 4.)
tpw
Output Pulse Width (Note 4.)
tos
Output-to-Output Skew
(Note 4.)
fVCO
PLL VCO Lock Range
fmax
Maximum Output Frequency
tpd
REFCLK to FBIN Delay
tPLZ, tPHZ
Output Disable Time
tPZL, tPLH
Output Enable Time
tjitter
Cycle–to–Cycle Jitter (Peak–to–Peak)
tlock
Maximum PLL Lock Time
Typ
0.10
tCYCLE/2
–750
tCYCLE/2
±500
Excluding Qa0
All Outputs
All Outputs
Feedback = VCO/4
Feedback = VCO/6
Feedback = VCO/8
Feedback = VCO/12
Qc,Qb (÷2)
Qa,Qb,Qc (÷4)
Qa (÷6)
200
200
200
200
Max
Unit
1.0
ns
tCYCLE/2
+750
ps
350
450
550
ps
480
480
480
480
MHz
VCO_Sel = 0
VCO_Sel = 0
VCO_Sel = 1
VCO_Sel = 1
MHz
(Note 4.)
180
120
80
–200
0
Condition
0.8 to 2.0V
Same Frequencies
Same Frequencies
Different Frequencies
200
ps
Notes 4., 5.
2
8
ns
50Ω to VCC/2
2
10
ns
50Ω to VCC/2
10
ms
±100
ps
4. 50Ω to VCC/2.
5. tpd is specified for 50MHz input ref, the window will shrink/grow proportionally from the minimum limit with shorter/longer input reference periods.
The tpd does not include jitter.
APPLICATIONS INFORMATION
Driving Transmission Lines
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC952 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 3 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC952 clock
driver is effectively doubled due to its capability to drive
multiple lines.
The MPC952 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
MPC952
OUTPUT
BUFFER
IN
7Ω
MPC952
OUTPUT
BUFFER
IN
RS = 43Ω
ZO = 50Ω
The waveform plots of Figure 4 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC952 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC952. The output waveform
in Figure 4 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
OutA
RS = 43Ω
ZO = 50Ω
OutB0
7Ω
RS = 43Ω
ZO = 50Ω
OutB1
Figure 3. Single versus Dual Transmission Lines
MOTOROLA
4
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MPC952
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC952 provides separate
power supplies for the output buffers (VCCO) and the internal
PLL (VCCA) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC952.
VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
VOLTAGE (V)
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
3.3V
1.0
RS=5–15Ω
0.5
VCCA
22µF
0
MPC952
2
4
6
8
TIME (nS)
10
12
14
VCC
0.01µF
Figure 4. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 5 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC952
OUTPUT
BUFFER
RS = 36Ω
ZO = 50Ω
RS = 36Ω
ZO = 50Ω
Figure 6. Power Supply Filter
Figure 6 illustrates a typical power supply filter scheme.
The MPC952 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC952. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 6 must have a resistance of 10–15Ω to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
7Ω
7Ω + 36Ω k 36Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
Although the MPC952 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
Power Supply Filtering
The MPC952 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
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0.01µF
5
MOTOROLA
MPC952
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
TQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
D
SECTION AE–AE
W
K
X
DETAIL AD
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
MOTOROLA
M
N
0.20 (0.008)
SEATING
PLANE
6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
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