MOTOROLA MPC947

SEMICONDUCTOR TECHNICAL DATA
! The MPC947 is a 1:9 low voltage clock distribution chip. The device
features the capability to select between two LVTTL compatible inputs
and fans the signal out to 9 LVCMOS or LVTTL compatible outputs.
These 9 outputs were designed and optimized to drive 50Ω series
terminated transmission lines. With output–to–output skews of 500ps, the
MPC947 is ideal as a clock distribution chip for synchronous systems
which need a tight level of skew at a relatively low cost. For a similar
product targeted at a higher price/performance point, consult the
MPC948 data sheet.
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LOW VOLTAGE
1:9 CLOCK
DISTRIBUTION CHIP
Clock Distribution for PowerPC 620 L2 Cache
2 Selectable LVCMOS/LVTTL Clock Inputs
500ps Maximum Output–to–Output Skew
Drives Up to 18 Independent Clock Lines
Maximum Output Frequency of 110MHz
Synchronous Output Enable
Tristatable Outputs
32–Lead TQFP Packaging
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
3.3V VCC Supply Voltage
With an output impedance of approximately 7Ω, in both the HIGH and
LOW logic states, the output buffers of the MPC947 are ideal for driving
series terminated transmission lines. More specifically, each of the 9
MPC947 outputs can drive two series terminated 50Ω transmission lines.
With this capability, the MPC947 has an effective fanout of 1:18 in
applications using point–to–point distribution schemes. With this level of
fanout, the MPC947 provides enough copies of low skew clocks for high
performance synchronous systems, including use as a clock distribution
chip for the L2 cache of a PowerPC 620 based system.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the select input pulled HIGH, the
TTL_CLK1 input will be selected.
All of the control inputs are LVCMOS/LVTTL compatible. The MPC947 provides a synchronous output enable control to allow
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into
high impedance. Note that all of the MPC947 inputs have internal pullup resistors.
The MPC947 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
PowerPC is a trademark of International Business Machines Corporation.
1/97
 Motorola, Inc. 1997
1
REV 3
MPC947
TTL_CLK0
0
TTL_CLK1
1
9
Q0–Q8
TTL_CLK1_Sel
D
Q
Sync_OE
Tristate
GND
Q3
VCCO
Q4
GND
Q5
VCCO
GND
Figure 1. Logic Diagram
24
23
22
21
20
19
18
17
FUNCTION TABLES
GND
25
16
GND
Q2
26
15
Q6
VCCO
27
14
VCCO
Q1
28
13
Q7
GND
29
12
GND
Q0
30
11
Q8
VCCO
31
10
VCCO
GND
32
9
GND
1
2
3
4
5
6
7
8
GND
TTL_CLK1_Sel
TTL_CLK0
TTL_CLK1
Sync_OE
Tristate
VCCI
GND
MPC947
TTL_CLK1_Sel
0
1
Sync_OE
0
1
Tristate
0
1
Input
TTL_CLK0
TTL_CLK1
Outputs
Disabled
Enabled
Outputs
Tristate
Enabled
Figure 2. 32–Lead Pinout (Top View)
TTL_CLK
Sync_OE
Q
Figure 3. Sync_OE Timing Diagram
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — Rev 6
MPC947
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
4.6
V
VI
Input Voltage
–0.3
VDD + 0.3
V
IIN
Input Current
±20
mA
TStor
Storage Temperature Range
–40
125
°C
(CMOS Inputs)
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V)
Symbol
Characteristic
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
ICC
Maximum Quiescent Supply Current
CIN
Input Capacitance
Typ
2.0
Max
Unit
3.6
V
0.8
V
2.5
V
IOH = –20mA (Note 1.)
V
IOL = 20mA (Note 1.)
–100
µA
Note 2.
28
mA
4
pF
0.4
21
Condition
Cpd
Power Dissipation Capacitance
25
pF
Per Output
1. The MPC947 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
2. IIN current is a result of internal pull–up resistors.
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V)
Symbol
Characteristic
Fmax
Maximum Input Frequency
tpd
Propagation Delay
tsk(o)
Min
Typ
Max
110
Unit
Condition
MHz
Note 3.
9.25
ns
Note 3.
Output–to–Output Skew
500
ps
Note 3.
tsk(pr)
Part–to–Part Skew
2.0
ns
Notes 3., 4.
tpwo
Output Pulse Width
tCYCLE/2
+ 800
ps
Note 3.,
Measured at VCC/2
ts
Setup Time
Sync_OE to Input Clk
0.0
ns
Notes 3., 5.
th
Hold Time
Input Clk to Sync_OE
1.0
ns
Notes 3., 5.
tPZL, tPZH
Output Enable Time
tPLZ, tPHZ
Output Disable Time
TCLK to Q
4.75
tCYCLE/2
– 800
tr, tf
Output Rise/Fall Time
0.2
3. Driving 50Ω terminated to VCC/2.
4. Part–to–part skew at a given temperature and voltage.
5. Setup and Hold times are relative to the falling edge of the input clock.
TIMING SOLUTIONS
BR1333 — Rev 6
3
11
ns
11
ns
1.0
ns
0.8V to 2.0V
MOTOROLA
MPC947
APPLICATIONS INFORMATION
line impedances. The voltage wave launched down the two
lines will equal:
Driving Transmission Lines
The MPC947 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC947 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC947 clock
driver is effectively doubled due to its capability to drive
multiple lines.
VOLTAGE (V)
2.5
OutA
tD = 3.8956
2.0
In
1.5
1.0
0.5
0
2
MPC947
OUTPUT
BUFFER
IN
7Ω
MPC947
OUTPUT
BUFFER
IN
OutB
tD = 3.9386
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Waveforms
RS = 43Ω
ZO = 50Ω
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
OutA
RS = 43Ω
ZO = 50Ω
OutB0
7Ω
RS = 43Ω
ZO = 50Ω
MPC947
OUTPUT
BUFFER
OutB1
ZO = 50Ω
RS = 36Ω
ZO = 50Ω
7Ω
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC947 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC947. The output waveform
in Figure 5 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
MOTOROLA
RS = 36Ω
7Ω + 36Ω k 36Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
4
TIMING SOLUTIONS
BR1333 — Rev 6
MPC947
OUTLINE DIMENSIONS
A
–T–, –U–, –Z–
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A1
32
0.20 (0.008) AB T–U Z
25
1
–U–
–T–
B
V
AE
P
B1
DETAIL Y
17
8
V1
AE
DETAIL Y
9
4X
–Z–
9
0.20 (0.008) AC T–U Z
S1
S
DETAIL AD
G
–AB–
0.10 (0.004) AC
AC T–U Z
–AC–
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
ÉÉ
F
8X
M_
R
J
M
N
D
0.20 (0.008)
SEATING
PLANE
SECTION AE–AE
W
K
X
DETAIL AD
TIMING SOLUTIONS
BR1333 — Rev 6
Q_
GAUGE PLANE
H
0.250 (0.010)
C E
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MOTOROLA
MPC947
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MOTOROLA
◊
6
MPC947/D
TIMING SOLUTIONS
BR1333 — Rev 6