SEMICONDUCTOR TECHNICAL DATA ! ! The MPC903, MPC904 and MPC905 are six output clock generation devices targeted to provide the clocks required in a 3.3V or 5.0V PCI environment. The device operates from a 3.3V supply and can interface to either a TTL input or an external crystal. The inputs to the device can be driven with 5.0V when the VCC is at 3.3V. The outputs of the MPC903/904/905 meet all of the specifications of the PCI standard. The three devices are identical except in the function of the Output Enables. • • • • • • 1:6 PCI CLOCK GENERATOR/ FANOUT BUFFER Six Low Skew Outputs Synchronous Output Enables for Power Management Low Voltage Operation XTAL Oscillator Interface 16-Lead SOIC Package 5.0V Tolerant Enable Inputs 16 The MPC903/904/905 device is targeted for PCI bus or processor bus environments with up to 12 clock loads. Each of the six outputs on the MPC903/904/905 can drive two series terminated 50Ω transmission lines. This capability effectively makes the MPC903/904/905 a 1:12 fanout buffer. 1 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 The MPC903 offers two synchronous enable inputs to allow users flexibility in developing power management features for their designs. Both enable signals are active HIGH inputs. A logic ‘0’ on the Enable1 input will pull all of the outputs into the logic ‘0’ state and shut down the internal oscillator for a zero power sleep state. A logic ‘0’ on the Enable2 input will disable only the BCLK5 output. The Enable2 input can be used to disable any high power device for system power savings during periods of inactivity. Both enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already LOW. This feature guarantees no runt pulses will be generated during enabling and disabling. Note that when the MPC903 is re-enabled via the Enable1 pin, the user must allow for the oscillator to regain stability. Thus, the re-enabling of the chip cannot occur instantaneously. The MPC904 and MPC905 Enable functions are slightly different than the 903 and are outlined in the function tables on the following page. VDD (3) GND (3) Pinout: 16-Lead Plastic Package (Top View) BCLK0 BCLK1 XTAL_IN BCLK2 BCLK3 XTAL_OUT Enable1 BCLK4 SYNCHRONIZE BCLK5 Enable2 SYNCHRONIZE XTAL_OUT 1 16 XTAL_IN Enable2 2 15 Enable1 GND1 3 14 BCLK5 BCLK0 4 13 VDD3 VDD1 5 12 BCLK4 BCLK1 6 11 GND3 GND2 7 10 BCLK3 BCLK2 8 9 VDD2 10/96 Motorola, Inc. 1996 1 REV 3 MPC903 MPC904 MPC905 FUNCTION TABLE Outputs 0 to 4 Output 5 OSC (On/Off) ENABLE1 ENABLE2 MPC903 MPC904 MPC905 MPC903 MPC904 MPC905 MPC903 MPC904 MPC905 0 0 1 1 0 1 0 1 Low Low Toggling Toggling Low Low Toggling Toggling Low Low Toggling Toggling Low Low Low Toggling Low Toggling Low Toggling Low Toggling Low Toggling OFF OFF ON ON OFF ON ON ON ON ON ON ON ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VDD Supply Voltage –0.5 4.6 V VIN Input Voltage –0.5 VCC + 0.5 V Toper Operating Temperature Range 0 +70 °C Tstg Storage Temperature Range –65 +150 °C Tsol Soldering Temperature Range (10 Sec) +260 °C Tj Junction Temperature Range +125 °C P(E1=1) Power Dissipation TBD mW P(E1=0) Power Dissipation 40 µW ESD Static Discharge Voltage ILatch Latch Up Current 2000 V 50 mA * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter TA Ambient Temperature Range VDD Positive Supply Voltage (Functional Range) tDCin Thigh (at XTAL_IN Input) Tlow (at XTAL_IN Input) Min Max Unit 0 70 °C 3.0 3.6 V 0.44T1 0.44T1 0.56T1 0.56T1 T = Period 1. When using External Source for reference, requirement to meet PCI clock duty cycle requirement on the output. DC CHARACTERISTICS (TA = 0–70°C; VDD = 3.3V ±0.3V) Symbol Characteristic Min Typ Unit 5.52 V 0.8 V VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage VOL Low Level Output Voltage 0.4 V IIH Input High Current 2.52 µA IIL Input Low Current 2.5 µA ICC Power Supply Current 45 95 µA mA mA CIN Input Capacitance 2.0 Max 2.4 DC 33MHz 66MHz V 20 37 78 XTAL_IN Others 9.0 4.5 Condition IOH = –36mA1 IOL = 36mA1 pF 1. The MPC903/904/905 outputs can drive series terminated or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info). 2. XTAL_IN input will sink up to 10mA when driven to 5.5V. There are no reliability concerns associated with the condition. Note that the Enable1 input must be a logic HIGH. Do not take the Enable1 input to a logic LOW with >VCC volts on the XTAL_IN input. MOTOROLA 2 TIMING SOLUTIONS BR1333 — REV 5 MPC903 MPC904 MPC905 AC CHARACTERISTICS (TA = 0–70°C; VDD = 3.3V ±0.3V) Symbol Characteristic Min Using External Crystal Using External Clock Source Typ Max Unit TBD DC 50 100 MHz 0.40T1 0.40T1 0.45T2 0.45T2 0.60T1 0.60T1 0.55T2 0.55T2 Condition Fmax Maximum Operating Frequency tpw Output Pulse Width tper Output Period tos Output-to-Output Skew tr, tf Rise/Fall Times (Slew Rate) tEN Enable Time tDIS Disable Time Aosc XTAL_IN to XTAL_OUT Oscillator Gain 6 db Phase Loop Phase Shift Modulo 360° + 30 Degrees HIGH (Above 2.0V) LOW (Below 0.8V) HIGH (Above 2.0V) LOW (Below 0.8V) T = Periods T – 400ps T = Desired Period Rising Edges Falling Edges 400 500 ps 4 V/ns Enable1 Enable2 5 4 ms Cycles Enable1 Enable2 4 4 Cycles 1 Series Terminated Transmission Lines 1. Assuming input duty cycle specs from Recommended Operationg Conditions table are met. 2. Assuming external crystal or 50% duty cycle external reference is used. Pin 16 Pin 1 Pin 16 100Ω Y1 10pF C3 fFUND 11.1111MHz 16pF C1 Figure 1. Crystal Oscillator Interface (Fundamental) 10pF + Ǹ 1 2p LTRAP CTRAP CTRAP Y1 33.3333MHz C1 Pin 1 C3 LTRAP 16pF Figure 2. Crystal Oscillator Interface (3rd Overtone) Table 1. Crystal Specifications Parameter TIMING SOLUTIONS BR1333 — REV 5 Value Crystal Cut Fundamental AT Cut Resonance Parallel Resonance* Frequency Tolerance ±75ppm at 25°C Frequency/Temperature Stability ±150pm 0 to 70°C Operating Range 0 to 70°C Shunt Capacitance 5–7pF Equivalent Series Resistance (ESR) 50 to 80Ω Correlation Drive Level 100µW Aging 5ppm/Yr (First 3 Years) 3 MOTOROLA MPC903 MPC904 MPC905 BCLK5 BCLK0–4 ENABLE2 ENABLE1 Figure 3. Enable Timing Diagram APPLICATIONS INFORMATION Driving Transmission Lines MPC903 OUTPUT BUFFER The MPC903/904/905 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). IN MPC903 OUTPUT BUFFER In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC903/904/905 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC903/904/905 clock driver is effectively doubled due to its capability to drive multiple lines. MOTOROLA 7Ω IN RS = 43Ω ZO = 50Ω OutA RS = 43Ω ZO = 50Ω OutB0 7Ω RS = 43Ω ZO = 50Ω OutB1 Figure 4. Single versus Dual Transmission Lines The waveform plots of Figure 5 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC903/904/905 output buffers is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line 4 TIMING SOLUTIONS BR1333 — REV 5 MPC903 MPC904 MPC905 driving need not be used exclusively to maintain the tight output–to–output skew of the MPC903. The output waveform in Figure 5 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). MPC903 OUTPUT BUFFER VOLTAGE (V) OutA tD = 3.8956 ZO = 50Ω RS = 36Ω ZO = 50Ω 7Ω 3.0 2.5 RS = 36Ω OutB tD = 3.9386 7Ω + 36Ω k 36Ω = 50Ω k 50Ω 25Ω = 25Ω 2.0 In Figure 6. Optimized Dual Line Termination 1.5 SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 Figure 5. Single versus Dual Waveforms TIMING SOLUTIONS BR1333 — REV 5 5 MOTOROLA MPC903 MPC904 MPC905 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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