SEMICONDUCTOR TECHNICAL DATA The MPC946 is a low voltage CMOS, 10 output clock buffer. The 10 outputs can be configured into a standard fanout buffer or into 1X and 1/2X combinations. The ten outputs were designed and optimized to drive 50Ω series or parallel terminated transmission lines. With output to output skews of 350ps the MPC946 is an ideal clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs. For a similar product with more outputs consult the MPC949 data sheet. • • • • • • • • LOW VOLTAGE 1:10 CMOS CLOCK DRIVER Clock Distribution for Pentium Systems with PCI 2 Selectable LVCMOS/LVTTL Clock Inputs 350ps Output to Output Skew Drives up to 20 Independent Clock Lines Maximum Input/Output Frequency of 150MHz Tristatable Outputs 32–Lead TQFP Packaging 3.3V VCC Supply With an output impedance of approximately 7Ω, in both the HIGH and the LOW logic states, the output buffers of the MPC946 are ideal for FA SUFFIX driving series terminated transmission lines. More specifically each of the TQFP PACKAGE 10 MPC946 outputs can drive two series terminated transmission lines. CASE 873A–02 With this capability, the MPC946 has an effective fanout of 1:20 in applications using point–to–point distribution schemes. The MPC946 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability to allow the user to select the ratio of 1X outputs to 1/2X outputs. Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the TCLK1 input is selected. All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced HIGH. The MPC946 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. Pentium is a trademark of Intel Corporation. 10/96 Motorola, Inc. 1996 1 REV 1 MPC946 LOGIC DIAGRAM TCLK_Sel TCLK0 TCLK1 Dsela (Int Pull Down) (Int Pull Up) ÷1 0 (Int Pull Up) ÷2 1 R 0 3 Qa0:2 1 (Int Pull Down) 0 3 Qb0:2 1 Dselb (Int Pull Down) 0 4 Qc0:3 1 Dselc MR/OE (Int Pull Down) (Int Pull Down) GNDb Qb0 VCCb Qb1 GNDb Qb2 VCCb VCCc Pinout: 32–Lead TQFP (Top View) 24 23 22 21 20 19 18 17 FUNCTION TABLES VCCa 25 16 Qc3 Qa2 26 15 GNDc GNDa 27 14 Qc2 Qa1 28 13 VCCc VCCa 29 12 Qc1 Qa0 30 11 GNDc GNDa 31 10 Qc0 MR/OE 32 MPC946 MOTOROLA 2 3 4 5 6 7 8 TCLK_Sel VCCI TCLK0 TCLK1 Dsela Dselb Dselc GNDI 9 1 TCLK_Sel Input 0 1 TCLK0 TCLK1 Dselx Outputs 0 1 MR/OE 0 1 1x 1/2x Outputs Enabled Hi–Z VCCc 2 TIMING SOLUTIONS BR1333 — Rev 6 MPC946 ABSOLUTE MAXIMUM RATINGS* Symbol Parameter Min Max Unit VCC Supply Voltage –0.3 4.6 V VI Input Voltage –0.3 VDD + 0.3 V IIN Input Current ±20 mA TStor Storage Temperature Range –40 125 °C (CMOS Inputs) * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V) Symbol Characteristic Min VIH Input HIGH Voltage VIL Input LOW Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIN Input Current ICC Maximum Quiescent Supply Current CIN Input Capacitance Typ 2.0 Max Unit 3.6 V 0.8 V V IOH = –20mA1 IOL = 20mA1 ±120 µA Note 2. 85 mA 4 pF 2.5 V 0.4 70 Condition Cpd Power Dissipation Capacitance 25 pF Per Output 1. The MPC946 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications Info section). 2. IIN current is a result of internal pull–up/pull–down resistors. AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V) Symbol Characteristic Min Fmax Maximum Input Frequency tPLH, tPHL Propagation Delay tsk(o) Output–to–Output Skew Same Frequency Outputs Different Frequency Outputs Same Frequency Outputs Different Frequency Outputs Typ Max 150 TCLK to Q 5.0 4.5 Unit MHz 8.0 7.5 12.0 11.5 Condition Note 1. ns Note 1., 3. ps Note 1., 3. Fmax < 100MHz Fmax < 100MHz Fmax > 100MHz Fmax > 100MHz 350 350 350 450 tsk(pr) Part–to–Part Skew 2.0 4.5 ns Note 2. tPZL, tPZH Output Enable Time 3 11 ns Note 3. tPLZ, tPHZ Output Disable Time 3 11 ns Note 3. 0.5 1.0 ns 0.8V to 2.0V, Note 3. tr, tf Output Rise/Fall Time 1. Driving 50Ω transmission lines. 2. Part–to–part skew at a given temperature and voltage. 3. Termination is 50Ω to VCC/2. 0.1 TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA MPC946 APPLICATIONS INFORMATION line impedances. The voltage wave launched down the two lines will equal: Driving Transmission Lines The MPC946 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC946 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 1 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC946 clock driver is effectively doubled due to its capability to drive multiple lines. VOLTAGE (V) 2.5 OutA tD = 3.8956 2.0 In 1.5 1.0 0.5 0 2 MPC946 OUTPUT BUFFER IN 7Ω MPC946 OUTPUT BUFFER IN OutB tD = 3.9386 4 6 8 TIME (nS) 10 12 14 Figure 2. Single versus Dual Waveforms RS = 43Ω ZO = 50Ω Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 3 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. OutA RS = 43Ω ZO = 50Ω OutB0 7Ω RS = 43Ω ZO = 50Ω MPC946 OUTPUT BUFFER OutB1 ZO = 50Ω RS = 36Ω ZO = 50Ω 7Ω Figure 1. Single versus Dual Transmission Lines The waveform plots of Figure 2 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC946 output buffers is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the MPC946. The output waveform in Figure 2 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43Ω series resistor plus the output impedance does not match the parallel combination of the MOTOROLA RS = 36Ω 7Ω + 36Ω k 36Ω = 50Ω k 50Ω 25Ω = 25Ω Figure 3. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. 4 TIMING SOLUTIONS BR1333 — Rev 6 MPC946 OUTLINE DIMENSIONS A –T–, –U–, –Z– FA SUFFIX TQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE–AE W K X DETAIL AD TIMING SOLUTIONS BR1333 — Rev 6 Q_ GAUGE PLANE H 0.250 (0.010) C E 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MOTOROLA MPC946 Motorola reserves the right to make changes without further notice to any products herein. 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