19-2514; Rev 3; 8/04 Dual-Phase, Parallelable, Average Current-Mode Controllers The MAX5038/MAX5041 dual-phase, PWM controllers provide high-output-current capability in a compact package with a minimum number of external components. The MAX5038/MAX5041 utilize a dual-phase, average current-mode control that enables optimal use of low RDS(ON) MOSFETs, eliminating the need for external heatsinks even when delivering high output currents. Differential sensing enables accurate control of the output voltage, while adaptive voltage positioning provides optimum transient response. An internal regulator enables operation with input voltage ranges of +4.75V to +5.5V or +8V to +28V. The high switching frequency, up to 500kHz per phase, and dual-phase operation allow the use of low-output inductor values and input capacitor values. This accommodates the use of PC boardembedded planar magnetics achieving superior reliability, current sharing, thermal management, compact size, and low system cost. The MAX5038/MAX5041 also feature a clock input (CLKIN) for synchronization to an external clock, and a clock output (CLKOUT) with programmable phase delay (relative to CLKIN) for paralleling multiple phases. The MAX5038 offers a variety of factory-trimmed preset output voltages (see Selector Guide) and the MAX5041 offers an adjustable output voltage from +1.0V to +3.3V. The MAX5038/MAX5041 operate over the extended industrial temperature range (-40°C to +85°C) and are available in a 28-pin SSOP package. Refer to the MAX5037 data sheet for a VRM 9.0-compatible, VIDcontrolled output voltage controller in a 44-pin MQFP or QFN package. Applications Features ♦ +4.75V to +5.5V or +8V to +28V Input Voltage Range ♦ Up to 60A Output Current ♦ Internal Voltage Regulator for a +12V or +24V Power Bus ♦ True Differential Remote Output Sensing ♦ Two Out-Of-Phase Controllers Reduce Input Capacitance Requirement and Distribute Power Dissipation ♦ Average Current-Mode Control Superior Current Sharing Between Individual Phases and Paralleled Modules Accurate Current Limit Eliminates MOSFET and Inductor Derating ♦ Integrated 4A Gate Drivers ♦ Selectable Fixed Frequency 250kHz or 500kHz Per Phase (Up to 1MHz for 2 Phases) ♦ Fixed (MAX5038) or Adjustable (MAX5041) Output Voltages ♦ 0.5% Accurate Reference (MAX5041B) ♦ External Frequency Synchronization from 125kHz to 600kHz ♦ Internal PLL with Clock Output for Paralleling Multiple DC-DC Converters ♦ Thermal Protection ♦ 28-Pin SSOP Package Servers and Workstations Point-Of-Load High-Current/High-Density Telecom DC-DC Regulators Ordering Information PART TEMP RANGE Networking Systems Large-Memory Arrays RAID Systems High-End Desktop Computers PINPACKAGE OUTPUT VOLTAGE MAX5038EAI12 -40°C to +85°C 28 SSOP Fixed +1.2V MAX5038EAI15 -40°C to +85°C 28 SSOP Fixed +1.5V MAX5038EAI18 -40°C to +85°C 28 SSOP Fixed +1.8V MAX5038EAI25 -40°C to +85°C 28 SSOP Fixed +2.5V MAX5038EAI33 -40°C to +85°C 28 SSOP Fixed +3.3V MAX5041EAI -40°C to +85°C 28 SSOP Adj +1.0V to +3.3V MAX5041BEAI -40°C to +85°C 28 SSOP Adj +1.0V to +3.3V Pin Configuration appears at end of data sheet. ________________________________________________________________Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5038/MAX5041 General Description MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers ABSOLUTE MAXIMUM RATINGS IN to SGND.............................................................-0.3V to +30V BST_ to SGND…………………………………….…-0.3V to +35V DH_ to LX_ ................................-0.3V to [(VBST_ - VLX_) + 0.3V] DL_ to PGND ..............................................-0.3V to (VCC + 0.3V) BST_ to LX_ ..............................................................-0.3V to +6V VCC to SGND............................................................-0.3V to +6V VCC to PGND............................................................-0.3V to +6V SGND to PGND .....................................................-0.3V to +0.3V All Other Pins to SGND...............................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.5mW/°C above +70°C) ............762mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SYSTEM SPECIFICATIONS 8 28 4.75 5.5 Input Voltage Range VIN Short IN and VCC together for +5V input operation Quiescent Supply Current IQ EN = VCC or SGND 4 Efficiency η ILOAD = 52A (26A per phase) 90 10 V mA % OUTPUT VOLTAGE MAX5038 only, no load Nominal Output Voltage Accuracy MAX5038 only, no load, VIN = VCC = +4.75V to +5.5V or VIN = +8V to +28V (Note 2) MAX5041 only, no load MAX5041 only, no load, VIN = VCC = +4.75V to +5.5V or VIN = +8V to +28V MAX5041B only, no load SENSE+ to SENSE- Voltage Accuracy MAX5041B only, no load, VIN = +8V to +28V -0.8 +0.8 -1 +1 0.992 1.008 0.990 1.010 0.995 1.005 0.995 1.005 % V STARTUP/INTERNAL REGULATOR VCC Undervoltage Lockout UVLO VCC falling 4.0 VCC Undervoltage Lockout Hysteresis 4.15 4.5 200 VCC Output Accuracy VIN = +8V to +28V, ISOURCE = 0 to 80mA 4.85 V mV 5.1 5.30 V 1 3 Ω MOSFET DRIVERS Output Driver Impedance RON Output Driver Source/Sink Current IDH_, IDL_ Non-Overlap Time 2 tNO Low or high output CDH_/DL_ = 5nF 4 A 60 ns _______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers (VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX CLKIN = SGND 238 250 262 CLKIN = VCC 475 500 525 UNITS OSCILLATOR AND PLL Switching Frequency fSW PLL Lock Range fPLL PLL Locking Time tPLL CLKOUT Phase Shift (at fSW = 125kHz) φCLKOUT 125 600 200 kHz µs PHASE = VCC 115 120 125 PHASE = unconnected 85 90 95 PHASE = SGND 55 60 65 ICLKIN 3 5 7 CLKIN High Threshold VCLKINH 2.4 CLKIN Low Threshold VCLKINL CLKIN Input Pulldown Current kHz degrees µA V 0.8 V CLKIN High Pulse Width tCLKIN 200 ns PHASE High Threshold VPHASEH 4 V PHASE Low Threshold VPHASEL PHASE Input Bias Current IPHASEBIA CLKOUT Output Low Level VCLKOUTL CLKOUT Output High Level VCLKOUTH ISOURCE = 2mA (Note 2) -50 ISINK = 2mA (Note 2) 1 V +50 µA 100 mV 4.5 V CURRENT LIMIT Average Current-Limit Threshold Cycle-by-Cycle Current Limit Cycle-by-Cycle Overload Response Time VCL VCLPK tR CSP_ to CSN_ 45 48 51 mV CSP_ to CSN_ (Note 3) 90 112 130 mV VCSP_ to VCSN_ = +150mV 260 ns 4 kΩ CURRENT-SENSE AMPLIFIER CSP_ to CSN_ Input Resistance Common-Mode Range Input Offset Voltage RCS_ VCMR(CS) -0.3 +3.6 V VOS(CS) -1 +1 mV Amplifier Gain AV(CS) 18 V/V 3dB Bandwidth f3dB 4 MHz 550 µS 50 dB CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER) Transconductance gmca Open-Loop Gain AVOL(CE) No load DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF) Common-Mode Voltage Range VCMR(DIFF) DIFF Output Voltage VCM Input Offset Voltage VOS(DIFF) Amplifier Gain AV(DIFF) -0.3 VSENSE+ = VSENSE- = 0 +1.0 V +1 mV 0.6 -1 V MAX5038/MAX5041 (+1.2V, +1.5V, +1.8V output versions) 0.997 1 1.003 MAX5038 (+2.5V and +3.3V output versions) 0.495 0.5 0.505 V/V _______________________________________________________________________________________ 3 MAX5038/MAX5041 ELECTRICAL CHARACTERISTICS (continued) MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers ELECTRICAL CHARACTERISTICS (continued) (VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER 3dB Bandwidth Minimum Output Current Drive SENSE+ to SENSE- Input Resistance SYMBOL f3dB CONDITIONS MIN CDIFF = 20pF TYP MAX 3 IOUT(DIFF) 1.0 RVS_ 50 UNITS MHz mA 100 kΩ VOLTAGE-ERROR AMPLIFIER (EAOUT) Open-Loop Gain AVOL(EA) 70 dB Unity-Gain Bandwidth fUGEA 3 MHz EAN Input Bias Current IB(EA) Error-Amplifier Output Clamping Voltage VEAN = +2.0V VCLAMP(EA) With respect to VCM -100 +100 nA 810 918 mV THERMAL SHUTDOWN Thermal Shutdown TSHDN Thermal-Shutdown Hysteresis 150 °C 8 °C EN INPUT EN Input Low Voltage VENL EN Input High Voltage VENH 3 IEN 4.5 EN Pullup Current 1 5 Note 1: Specifications from -40°C to 0°C are guaranteed by characterization but not production tested. Note 2: Guaranteed by design. Not production tested. Note 3: See Peak-Current Comparator section. 4 V V _______________________________________________________________________________________ 5.5 µA Dual-Phase, Parallelable, Average Current-Mode Controllers EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE f = 500kHz 60 VIN = +5V VOUT = +1.8V 40 30 30 20 VOUT = +1.8V fSW = 250kHz 0 IOUT (A) EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE SUPPLY CURRENT vs. FREQUENCY AND INPUT VOLTAGE 80 VOUT = +1.5V 70 η (%) VOUT = +1.1V 60 50 40 40 30 30 20 VOUT = +1.8V 12.0 11.5 11.0 10.5 ICC (mA) VOUT = +1.8V 90 MAX5038/41 toc05 VOUT = +1.5V 100 VOUT = +1.1V 20 VIN = +12V fSW = 250kHz 10 0 VIN = +5V fSW = 500kHz 0 MAX5038/41 toc06 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A) 50 VIN = +24V 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 VIN = +12V VIN = +5V EXTERNALCLOCK NO DRIVER LOAD 0 4 8 12 16 20 24 28 32 36 40 44 48 52 0 4 8 12 16 20 24 28 32 36 40 44 48 52 100 150 200 250 300 350 400 450 500 550 600 IOUT (A) IOUT (A) FREQUENCY (kHz) SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY SUPPLY CURRENT vs. LOAD CAPACITANCE PER DRIVER 600kHz 150 70 500kHz 90 80 70 ICC (mA) 125kHz 50 ICC (mA) 125 60 MAX5038/41 toc09 250kHz 100 MAX5038/41 toc08 90 80 175 MAX5038/41 toc07 100 100 40 60 50 40 75 30 0 VIN = +24V VOUT = +1.8V fSW = 125kHz 10 IOUT (A) 60 10 50 0 4 8 12 16 20 24 28 32 36 40 44 48 52 70 20 60 40 0 80 η (%) 50 0 4 8 12 16 20 24 28 32 36 40 44 48 52 90 ICC (mA) 70 VIN = +5V 60 10 100 10 80 20 MAX5038/41 toc04 40 90 η (%) η (%) f = 250kHz 70 50 VIN = +12V 70 80 η (%) 90 80 EFFICIENCY vs. OUTPUT CURRENT 100 MAX5038/41 toc02 90 100 MAX5038/41 toc01 100 MAX5038/41 toc03 EFFICIENCY vs. OUTPUT CURRENT AND INTERNAL OSCILLATOR FREQUENCY VIN = +12V CDL_ = 22nF CDH_ = 8.2nF -40 -15 50 30 20 VIN = +5V CDL_ = 22nF CDH_ = 8.2nF 25 10 35 TEMPERATURE (°C) 60 85 VIN = +12V fSW = 250kHz 10 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 1 3 5 7 9 11 13 15 CDRIVER (nF) _______________________________________________________________________________________ 5 MAX5038/MAX5041 Typical Operating Characteristics (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C, unless otherwise noted.) OUTPUT VOLTAGE vs. OUTPUT CURRENT AND ERROR AMP GAIN (RF / RIN) 53 VIN = +12V VOUT = +1.8V RF / RIN = 15 1.80 DIFFERENTIAL AMPLIFIER BANDWIDTH MAX5038/41 toc12 3.5 90 45 3.0 PHASE 0 2.5 52 VOUT (V) 51 50 49 PHASE 2 48 PHASE 1 GAIN (V/V) RF / RIN = 12.5 1.75 1.70 RF / RIN = 7.5 47 -90 1.5 -135 GAIN 1.0 RF / RIN = 10 1.65 -45 2.0 -180 0.5 46 1.3 1.4 1.5 1.6 1.7 0 DIFF OUTPUT ERROR vs. SENSE+ TO SENSE- VOLTAGE VCC LOAD REGULATION vs. INPUT VOLTAGE 0.150 1 10 FREQUENCY (MHz) ILOAD (A) VCC LINE REGULATION 5.20 VIN = +24V 5.15 0.1 0.01 5 10 15 20 25 30 35 40 45 50 55 VOUT (V) VIN = +12V NO DRIVER 0.175 1.8 VIN = +12V 5.10 5.25 MAX5038/41 toc15 1.2 MAX5038/41 toc13 0.200 1.1 -270 0 1.60 1.0 MAX5038/41 toc14 45 -225 5.20 ICC = 0 5.15 0.100 5.00 0.075 4.95 0.050 4.90 0.025 4.85 0 4.80 VCC (V) 5.05 VCC (V) ERROR (%) 5.10 0.125 VIN = +8V ICC = 40mA 5.05 5.00 4.95 4.90 4.85 4.80 DC LOAD 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VCC LINE REGULATION DRIVER RISE TIME vs. DRIVER LOAD CAPACITANCE DRIVER FALL TIME vs. DRIVER LOAD CAPACITANCE 5.00 4.95 4.90 DL_ DH_ 30 20 10 0 4.85 ICC = 80mA 9.0 80 70 60 50 40 10.0 11.0 VIN (V) 12.0 13.0 tF (ns) tR (ns) 5.05 6 11 16 21 CDRIVER (nF) 26 31 80 70 60 DL_ DH_ 50 40 30 20 10 0 VIN = +12V fSW = 250kHz 1 MAX5038/41 toc18 120 110 100 90 MAX5038/41 toc17 MAX5038/41 toc16 120 110 100 90 5.10 6 10 12 14 16 18 20 22 24 26 28 VIN (V) 5.15 8.0 8 ICC (mA) 5.20 4.75 15 30 45 60 75 90 105 120 135 150 ∆VSENSE (V) 5.25 4.80 4.75 0 36 VIN = +12V fSW = 250kHz 1 6 11 16 21 CDRIVER (nF) _______________________________________________________________________________________ 26 31 36 PHASE (deg) 54 (VCSP_ - VCSN_) (mV) 1.85 MAX5038/41 toc10 55 MAX5038/41 toc11 CURRENT-SENSE THRESHOLD vs. OUTPUT VOLTAGE VCC (V) MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers Dual-Phase, Parallelable, Average Current-Mode Controllers PLL LOCKING TIME 250kHz TO 350kHz AND 350kHz TO 250kHz MAX5038/41 toc21 LOW-SIDE DRIVER (DL_) SINK AND SOURCE CURRENT HIGH-SIDE DRIVER (DH_) SINK AND SOURCE CURRENT MAX5038/41 toc20 MAX5038/41 toc19 CLKOUT 5V/div 350kHz DH_ 1.6A/div PLLCMP 200mV/div DL_ 1.6A/div 250kHz 0 VIN = +12V NO LOAD VIN = +12V CDL_ = 22nF VIN = +12V CDH_ = 22nF 100µs/div 100ns/div 100ns/div PLL LOCKING TIME 250kHz TO 150kHz AND 150kHz TO 250kHz MAX5038/41 toc23 PLL LOCKING TIME 250kHz TO 500kHz AND 500kHz TO 250kHz MAX5038/41 toc22 HIGH-SIDE DRIVER (DH_) RISE TIME MAX5038/41 toc24 CLKOUT 5V/div CLKOUT 5V/div DH_ 2V/div 250kHz PLLCMP 200mV/div 500kHz PLLCMP 200mV/div 150kHz 0 250kHz VIN = +12V CDH_ = 22nF VIN = +12V NO LOAD VIN = +12V NO LOAD 0 40ns/div 100µs/div 100µs/div HIGH-SIDE DRIVER (DH_) FALL TIME LOW-SIDE DRIVER (DL_) RISE TIME MAX5038/41 toc25 DH_ 2V/div VIN = +12V CDH_ = 22nF MAX5038/41 toc27 DL_ 2V/div VIN = +12V CDL_ = 22nF 40ns/div LOW-SIDE DRIVER (DL_) FALL TIME MAX5038/41 toc26 DL_ 2V/div VIN = +12V CDL_ = 22nF 40ns/div 40ns/div _______________________________________________________________________________________ 7 MAX5038/MAX5041 Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C, unless otherwise noted.) MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C, unless otherwise noted.) OUTPUT RIPPLE INPUT STARTUP RESPONSE MAX5038/41 toc28 MAX5038/41 toc29 VPGOOD 1V/div VOUT 1V/div VOUT (AC-COUPLED) 10mV/div VIN 5V/div VIN = +12V VOUT = +1.75V IOUT = 52A VIN = +12V VOUT = +1.75V IOUT = 52A 500ns/div 2ms/div ENABLE STARTUP RESPONSE LOAD-TRANSIENT RESPONSE MAX5038/41 toc30 MAX5038/41 toc31 VPGOOD 1V/div VOUT 1V/div VIN = +12V VOUT = +1.75V IOUT = 52A 1ms/div 8 VEN 2V/div VOUT 50mV/div VIN = +12V VOUT = +1.75V ISTEP = 8A TO 52A tRISE = 1µs 40µs/div _______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers PIN NAME 1, 13 CSP2, CSP1 Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18. 2, 14 CSN2, CSN1 Current-Sense Differential Amplifier Negative Input. Senses the inductor current. 3 PHASE Phase-Shift Setting Input. Connect PHASE to VCC for 120°, leave PHASE unconnected for 90°, or connect PHASE to SGND for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1. 4 PLLCMP 5, 7 CLP2, CLP1 Current-Error Amplifier Output. Compensate the current loop by connecting an RC network to ground. 6 SGND Signal Ground. Ground connection for the internal control circuitry. 8 SENSE+ Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to VOUT+ at the load. The MAX5038 regulates the difference between SENSE+ and SENSE- according to the factory preset output voltage. The MAX5041 regulates the SENSE+ to SENSE- difference to +1.0V. 9 SENSE- Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to VOUT- or PGND at the load. 10 DIFF Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier. 11 EAN Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier. Referenced to SGND. 12 EAOUT 15 EN 16, 26 BST1, BST2 Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply. Connect 0.47µF ceramic capacitors between BST_ and LX_. 17, 25 DH1, DH2 High-Side Gate Driver Output. Drives the gate of the high-side MOSFET. 18, 24 LX1, LX2 Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for the high-side driver. 19, 23 DL1, DL2 Low-Side Gate Driver Output. Synchronous MOSFET gate drivers for the two phases. 20 VCC 21 IN 22 PGND 27 CLKOUT Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount specified by PHASE. Use CLKOUT to parallel additional MAX5038/MAX5041s. CLKIN CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and 600kHz. The PWM frequency defaults to the internal oscillator if CLKIN is connected to VCC or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or connect to VCC to set the internal oscillator to 500kHz. CLKIN has an internal 5µA pulldown current. 28 FUNCTION External Loop-Compensation Input. Connect compensation network for the phase lock loop (see PhaseLocked Loop section). Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error amplifier gain-setting resistors determine the amount of adaptive voltage positioning Output Enable. A logic low shuts down the power drivers. EN has an internal 5µA pullup current. Internal +5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7µF and 0.1µF ceramic capacitors. Supply Voltage Connection. Connect IN to VCC for a +5V system. Connect the VRM input to IN through an RC lowpass filter, a 2.2Ω resistor and a 0.1µF ceramic capacitor. Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and VCC bypass capacitor returns together. _______________________________________________________________________________________ 9 MAX5038/MAX5041 Pin Description Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041 Functional Diagram EN IN +5V LDO REGULATOR UVLO POR TEMP SENSOR VCC TO INTERNAL CIRCUITS CSP1 CSN1 CSP1 DRV_VCC SHDN CSN1 CLP1 DH1 CLP1 CLK SGND MAX5038 MAX5041 LX1 PHASE 1 DL1 GMIN PGND PHASELOCKED LOOP CLKIN BST1 RAMP1 CLKOUT PLLCMP RAMP GENERATOR DIFF SENSE- 0.6V DIFF AMP PGND SENSE+ EAOUT EAN ERROR AMP DRV_VCC VREF = VOUT for VOUT ≤ 1.8V (MAX5038) VREF = VOUT/2 for VOUT > 1.8V (MAX5038) VREF = +1.0V (MAX5041) CSN2 CSP2 10 PGND RAMP2 GMIN CLP2 SHDN CLK PHASE 2 DH2 LX2 CLP2 CSN2 CSP2 ______________________________________________________________________________________ DL2 BST2 Dual-Phase, Parallelable, Average Current-Mode Controllers output current capacity. For maximum ripple rejection at the input, set the phase shift between phases to 90° for two paralleled converters, or 60° for three paralleled converters. Paralleling the MAX5038/MAX5041s improves design flexibility in applications requiring upgrades (higher load). The MAX5038/MAX5041 (Figures 1 and 2) average current-mode PWM controllers drive two out-of-phase buck converter channels. Average current-mode control improves current sharing between the channels while minimizing component derating and size. Parallel multiple MAX5038/MAX5041 regulators to increase the SENSE SENSE + 3 PHASE CSN1 CSP1 9 8 14 13 VIN 15 EN R1 VIN = +12V C3–C7 21 IN C1, C2 C39 DH1 LX1 VCC 28 DL1 17 Q1 R2 L1 18 19 C12 Q2 CLKIN D1 MAX5038 BST1 16 4 PLLCMP R4 C25 D3 +1.8V AT 60A VOUT VCC 20 C32 C26 VCC R7 RX 10 11 R8 12 DIFF C31 VIN D4 C8–C11 EAOUT DH2 25 R6 7 CLP1 DL2 23 C16–C24, LOAD C33 Q1 L2 LX2 24 C29 C14, C15 EAN R3 C13 Q2 D2 C30 5 C28 C27 BST2 26 CLP2 R5 1 6 22 SGND PGND CSP2 CSN2 2 NOTE: SEE TABLE 1 FOR COMPONENT VALUES. Figure 1. MAX5038 Typical Application Circuit, VIN = +12V ______________________________________________________________________________________ 11 MAX5038/MAX5041 Detailed Description MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers Dual-phase converters with an out-of-phase locking arrangement reduce the input and output capacitor ripple current, effectively multiplying the switching frequency by the number of phases. Each phase of the MAX5038/MAX5041 consists of an inner average current loop controlled by a common outer-loop voltage- SENSE SENSE + 3 CSN1 PHASE CSP1 error amplifier (VEA) that corrects the output voltage errors. The MAX5038/MAX5041 utilize a single controlling VEA and an average current mode to force the phase currents to be equal. 9 8 14 13 VIN 15 EN R1 VIN = +12V C3–C7 21 IN C1, C2 C39 DH1 LX1 VCC 28 DL1 17 Q1 L1 18 19 C12 Q2 CLKIN R2 D1 MAX5041 BST1 16 4 PLLCMP R4 C25 D3 +1.8V AT 60A VOUT VCC 20 C32 C31 RH C26 R7 VCC 10 11 R8 RX 12 DIFF D4 VIN C8–C11 EAN EAOUT R6 7 CLP1 C16–C24, LOAD C33 RL DH2 25 Q1 L2 LX2 24 C29 C14, C15 DL2 23 R3 C13 Q2 D2 C30 5 C28 C27 BST2 26 CLP2 R5 1 6 22 SGND PGND CSP2 CSN2 2 NOTE: SEE TABLE 1 FOR COMPONENT VALUES. Figure 2. MAX5041 Typical Application Circuit, VIN = +12V 12 ______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers Internal Oscillator The internal oscillator generates the 180° out-of-phase clock signals required by the pulse-width modulation (PWM) circuits. The oscillator also generates the 2VP-P voltage ramp signals necessary for the PWM comparators. Connect CLKIN to SGND to set the internal oscillator frequency to 250kHz or connect CLKIN to VCC to set the internal oscillator to 500kHz. ICC = IQ + fSW x (QG1 + QG2 + QG3 + QG4) (2) where, Q G1, Q G2, Q G3, and Q G4 are the total gate charge of the low-side and high-side external MOSFETs, IQ is 4mA (typ), and fSW is the switching frequency of each individual phase. For applications utilizing a +5V input voltage, disable the VCC regulator by connecting IN and VCC together. Undervoltage Lockout (UVLO)/ Power-On Reset (POR)/Soft-Start The MAX5038/MAX5041 include an undervoltage lockout with hysteresis and a power-on reset circuit for converter turn-on and monotonic rise of the output voltage. The UVLO threshold is internally set between +4.0V and +4.5V with a 200mV hysteresis. Hysteresis at UVLO eliminates “chattering” during startup. Most of the internal circuitry, including the oscillator, turns on when the input voltage reaches +4V. The MAX5038/MAX5041 draw up to 4mA of current before the input voltage reaches the UVLO threshold. The compensation network at the current error amplifiers (CLP1 and CLP2) provides an inherent soft-start of the output voltage. It includes a parallel combination of capacitors (C28, C30) and resistors (R5, R6) in series with other capacitors (C27, C29) (see Figures 1 and 2). The voltage at CLP_ limits the maximum current available to charge output capacitors. The capacitor on CLP_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus the output voltage. CLKIN is a CMOS logic clock input for the phaselocked loop (PLL). When driven externally, the internal oscillator locks to the signal at CLKIN. A rising edge at CLKIN starts the ON cycle of the PWM. Ensure that the external clock pulse width is at least 200ns. CLKOUT provides a phase-shifted output with respect to the rising edge of the signal at CLKIN. PHASE sets the amount of phase shift at CLKOUT. Connect PHASE to VCC for 120° of phase shift, leave PHASE unconnected for 90° of phase shift, or connect PHASE to SGND for 60° of phase shift with respect to CLKIN. The MAX5038/MAX5041 require compensation on PLLCMP even when operating from the internal oscillator. The device requires an active PLL in order to generate the proper clock signal required for PWM operation. Control Loop The MAX5038/MAX5041 use an average current-mode control scheme to regulate the output voltage (Figures 3a and 3b). The main control loop consists of an inner current loop and an outer voltage loop. The inner loop controls the output currents (IPHASE1 and I PHASE2 ) while the outer loop controls the output voltage. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a singlepole system. The current loop consists of a current-sense resistor (RS), a current-sense amplifier (CA_), a current-error amplifier (CEA_), an oscillator providing the carrier ramp, and a PWM comparator (CPWM_). The precision CA_ amplifies the sense voltage across RS by a factor of 18. The inverting input to the CEA_ senses the CA_ output. The CEA_ output is the difference between the voltage-error amplifier output (EAOUT) and the gainedup voltage from the CA_. The RC compensation network connected to CLP1 and CLP2 provides external frequency compensation for the respective CEA_. The start of every clock cycle enables the high-side drivers and initiates a PWM ON cycle. Comparator CPWM_ compares the output voltage from the CEA_ with a 0 to +2V ramp from the oscillator. The PWM ON cycle terminates when the ramp voltage exceeds the error voltage. ______________________________________________________________________________________ 13 MAX5038/MAX5041 VIN and VCC The MAX5038/MAX5041 accept a wide input voltage range of +4.75V to +5.5V or +8V to +28V. All internal control circuitry operates from an internally regulated nominal voltage of +5V (VCC). For input voltages of +8V or greater, the internal VCC regulator steps the voltage down to +5V. The VCC output voltage regulates to +5V while sourcing up to 80mA. Bypass VCC to SGND with 4.7µF and 0.1µF low-ESR ceramic capacitors for highfrequency noise rejection and stable operation (Figures 1 and 2). Calculate power dissipation in the MAX5038/MAX5041 as a product of the input voltage and the total VCC regulator output current (ICC). ICC includes quiescent current (IQ) and gate drive current (IDD): PD = VIN x ICC (1) MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers CCF CLP1 CSP1 CSN1 RCF MAX5038 CCFF CA1 VIN R F* IPHASE1 CEA1 SENSE+ DRIVE 1 CPWM1 RS RIN* DIFF AMP VEA SENSE- VOUT VIN COUT CEA2 VREF CPWM2 IPHASE2 DRIVE 2 RS LOAD CSN2 CSP2 CLP2 CA2 CCF RCF *RF AND RIN ARE EXTERNAL TO MAX5038 (RF = R8, RIN = R7, FIGURE 1) CCCF Figure 3a. MAX5038 Control Loop CCF MAX5041 CLP1 CSP1 CSN1 RCF CCFF CA1 R F* VIN IPHASE1 CEA1 SENSE+ CPWM1 DIFF AMP DRIVE 1 RS RIN* VEA SENSE- VOUT VIN CEA2 VREF = +1.0V CPWM2 DRIVE 2 IPHASE2 RS COUT LOAD CLP2 CSP2 CSN2 CA2 CCF RCF *RF AND RIN ARE EXTERNAL TO MAX5041 (RF = R8, RIN = R7, FIGURE 2) CCCF Figure 3b. MAX5041 Control Loop 14 ______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers than the average current limit (48mV). Proper inductor selection ensures that only extreme conditions trip the peak-current comparator, such as a cracked output inductor. The 112mV voltage threshold for triggering the peak-current limit is twice the full-scale average current-limit voltage threshold. The peak-current comparator has a delay of only 260ns. Current-Error Amplifier Current-Sense Amplifier The differential current-sense amplifier (CA_) provides a DC gain of 18. The maximum input offset voltage of the current-sense amplifier is 1mV and the common-mode voltage range is -0.3V to +3.6V. The current-sense amplifier senses the voltage across a current-sense resistor. Each phase of the MAX5038/MAX5041 has a dedicated transconductance current-error amplifier (CEA_) with a typical gm of 550µS and 320µA output sink and source current capability. The current-error amplifier outputs, CLP1 and CLP2, serve as the inverting input to the PWM comparator. CLP1 and CLP2 are externally accessible to provide frequency compensation for the inner current loops (Figures 3a and 3b). Compensate CEA_ such that the inductor current down slope, which becomes the up slope to the inverting input of the PWM comparator, is less than the slope of the internally generated voltage ramp (see the Compensation section). Peak-Current Comparator The peak-current comparator provides a path for fast cycle-by-cycle current limit during extreme fault conditions such as an output inductor malfunction (Figure 4). Note that the average current-limit threshold of 48mV still limits the output current during short-circuit conditions. To prevent inductor saturation, select an output inductor with a saturation current specification greater PWM Comparator and R-S Flip-Flop The PWM comparator (CPWM) sets the duty cycle for each cycle by comparing the output of the current-error amplifier to a 2VP-P ramp. At the start of each clock cycle, an R-S flip-flop resets and the high-side driver (DH_) turns on. The comparator sets the flip-flop as soon as the ramp voltage exceeds the CLP_ voltage, thus terminating the ON cycle (Figure 4). DRV_VCC PEAK-CURRENT COMPARATOR 112mV CLP_ CSP_ AV = 18 Gm = 500µS CSN_ BST_ PWM COMPARATOR GMIN S Q DH_ RAMP LX_ 2 x fs (V/s) CLK R Q DL_ PGND SHDN Figure 4. Phase Circuit (Phase 1/Phase 2) ______________________________________________________________________________________ 15 MAX5038/MAX5041 The outer voltage control loop consists of the differential amplifier (DIFF AMP), reference voltage, and VEA. The unity-gain differential amplifier provides true differential remote sensing of the output voltage. The differential amplifier output connects to the inverting input (EAN) of the VEA. The noninverting input of the VEA is internally connected to an internal precision reference voltage. The MAX5041 reference voltage is set to +1.0V and the MAX5038 reference is set to the preset output voltage. The VEA controls the two inner current loops (Figures 3a and 3b). Use a resistive feedback network to set the VEA gain as required by the adaptive voltage-positioning circuit (see the Adaptive Voltage Positioning section). MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers Differential Amplifier The differential amplifier (DIFF AMP) facilitates output voltage remote sensing at the load (Figures 3a and 3b). It provides true differential output voltage sensing while rejecting the common-mode voltage errors due to highcurrent ground paths. Sensing the output voltage directly at the load provides accurate load voltage sensing in high-current environments. The VEA provides the difference between the differential amplifier output (DIFF) and the desired output voltage. The differential amplifier has a bandwidth of 3MHz. The difference between SENSE+ and SENSE- regulates to the preset output voltage for the MAX5038 and regulates to +1V for the MAX5041. Voltage-Error Amplifier The VEA sets the gain of the voltage control loop and determines the error between the differential amplifier output and the internal reference voltage (VREF). VREF equals VOUT(NOM) for the +1.8V or lower voltage versions of the MAX5038 and VREF equals VOUT(NOM)/2 for the +2.5V and +3.3V versions. For MAX5041, VREF equals +1V. An offset is added to the output voltage of the MAX5038/MAX5041 with a finite gain (RF/RIN) of the VEA such that the no-load output voltage is higher than the nominal value. Choose R F and R IN from the Adaptive Voltage Positioning section and use the following equations to calculate the no-load output voltage. MAX5038: ⎛ R ⎞ VOUT(NL) = ⎜1 + IN ⎟ × VOUT(NOM ) RF ⎠ ⎝ (3) ⎛ R ⎞ ⎛R +R ⎞ L ×V VOUT(NL) = ⎜1 + IN ⎟ × ⎜ H ⎟ REF RF ⎠ ⎝ RL ⎠ ⎝ (4) MAX5041: where RH and RL are the feedback resistor network (Figure 2). Some applications require VOUT equal to VOUT(NOM) at no load. To ensure that the output voltage does not exceed the nominal output voltage (VOUT(NOM)), add a resistor RX from VCC to EAN. 16 Use the following equations to calculate the value of RX. For MAX5038 versions of VOUT(NOM) ≤ +1.8V: RX = [VCC − (VNOM + 0.6)] × RF VNOM (5) For MAX5038 versions of VOUT(NOM) > +1.8V: RX = [2VCC − (VNOM + 1.2)] × RF VNOM (6) For MAX5041: RX = [VCC − 1.6] × RF (7) VREF The VEA output clamps to +0.9V (plus the commonmode voltage of +0.6V), thus limiting the average maximum current from individual phases. The maximum average current-limit threshold for each phase is equal to the maximum clamp voltage of the VEA divided by the gain (18) of the current-sense amplifier. This allows for accurate settings for the average maximum current for each phase. Set the VEA gain using RF and RIN for the amount of output voltage positioning required as discussed in the Adaptive Voltage Positioning section (Figures 3a and 3b). Adaptive Voltage Positioning Powering new-generation processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when the output current suddenly increases. Regulating at a lower output voltage under a heavy load allows a larger upward-voltage excursion when the output current suddenly decreases. A larger allowed, voltage-step excursion reduces the required number of output capacitors or allows for the use of higher ESR capacitors. Voltage positioning and the ability to operate with multiple reference voltages may require the output to regulate away from a center value. Define the center value as the voltage where the output drops (∆VOUT/2) at one half the maximum output current (Figure 5). ______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers VOLTAGE-POSITIONING WINDOW VCNTR + ∆VOUT/2 VCNTR VCNTR - ∆VOUT/2 1/2 LOAD NO LOAD FULL LOAD LOAD (A) Figure 5. Defining the Voltage-Positioning Window Set the voltage-positioning window (∆VOUT) using the resistive feedback of the VEA. Use the following equations to calculate the voltage-positioning window for the MAX5038: I × RIN ∆VOUT = OUT 2 × GC × RF GC = 0.05 (8) (9) RS Use the following equation to calculate the voltage-positioning window for the MAX5041: ∆VOUT = IOUT × RIN R + RL × H (2 × GC × RF ) RL GC = 0.05 (10) (11) RS where RIN and RF are the input and feedback resistors of the VEA, GC is the current-loop gain and RS is the current-sense resistor or, if using lossless inductor current sensing, the DC resistance of the inductor. The PLL synchronizes the internal oscillator to the external frequency source when driving CLKIN. Connecting CLKIN to VCC or SGND forces the PWM frequency to default to the internal oscillator frequency of 500kHz or 250kHz, respectively. The PLL uses a conventional architecture consisting of a phase detector and a charge pump capable of providing 20µA of output current. Connect an external series combination capacitor (C25) and resistor (R4) and a parallel capacitor (C26) from PLLCMP to SGND to provide frequency compensation for the PLL (Figure 1). The pole-zero pair compensation provides a zero at fZ = 1 / [R4 x (C25 + C26)] and a pole at fP = 1 / (R4 x C26). Use the following typical values for compensating the PLL: R4 = 7.5kΩ, C25 = 4.7nF, C26 = 470pF. If changing the PLL frequency, expect a finite locking time of approximately 200µs. The MAX5038/MAX5041 require compensation on PLLCMP even when operating from the internal oscillator. The device requires an active PLL in order to generate the proper internal PWM clocks. MOSFET Gate Drivers (DH_, DL_) The high-side (DH_) and low-side (DL_) drivers drive the gates of external N-channel MOSFETs (Figures 1 and 2). The drivers’ high-peak sink and source current capability provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced cross-conduction losses. For modern CPU voltage-regulating module applications where the duty cycle is less than 50%, choose highside MOSFETs (Q1 and Q3) with a moderate RDS(ON) and a very low gate charge. Choose low-side MOSFETs (Q2 and Q4) with very low R DS(ON) and moderate gate charge. The driver block also includes a logic circuit that provides an adaptive non-overlap time to prevent shootthrough currents during transition. The typical non-overlap time is 60ns between the high-side and low-side MOSFETs. BST_ VDD powers the low- and high-side MOSFET drivers. Connect a 0.47µF low-ESR ceramic capacitor between BST_ and LX_. Bypass VCC to PGND with 4.7µF and 0.1µF low-ESR ceramic capacitors. Reduce the PC board area formed by these capacitors, the rectifier diodes between V CC and the boost capacitor, the MAX5038/MAX5041, and the switching MOSFETs. ______________________________________________________________________________________ 17 MAX5038/MAX5041 Phase-Locked Loop: Operation and Compensation MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers Overload Conditions Average current-mode control has the ability to limit the average current sourced by the converter during a fault condition. When a fault condition occurs, the VEA output clamps to +0.9V with respect to the common-mode voltage (VCM = +0.6V) and is compared with the output of the current-sense amplifiers (CA1 and CA2) (see Figures 3a and 3b). The current-sense amplifier’s gain of 18 limits the maximum current in the inductor or sense resistor to ILIMIT = 50mV/RS. Parallel Operation For applications requiring large output current, parallel up to three MAX5038/MAX5041s (six phases) to triple the available output current. The paralleled converters operate at the same switching frequency but different phases keep the capacitor ripple RMS currents to a minimum. Three parallel MAX5038/MAX5041 converters deliver up to 180A of output current. To set the phase shift of the on-board PLL, leave PHASE unconnected for 90° of phase shift (2 paralleled converters), or connect PHASE to SGND for 60° of phase shift (3 converters in parallel). Designate one converter as master and the remaining converters as slaves. Connect the master and slave controllers in a daisy-chain configuration as shown in Figure 6. Connect CLKOUT from the master controller to CLKIN of the first slaved controller, and CLKOUT from the first slaved controller to CLKIN of the second slaved controller. Choose the appropriate phase shift for minimum ripple currents at the input and output capacitors. The master controller senses the output differential voltage through SENSE+ and SENSE- and generates the DIFF voltage. Disable the voltage sensing of the slaved controllers by leaving DIFF unconnected (floating). Figure 7 shows a detailed typical parallel application circuit using two MAX5038s. This circuit provides four phases at an input voltage of +12V and an output voltage range of +1V to +3.3V at 104A. Applications Information Each MAX5038/MAX5041 circuit drives two 180° out-ofphase channels. Parallel two or three MAX5038/ MAX5041 circuits to achieve four- or six-phase operation, respectively. Figure 1 shows the typical application circuit for a two-phase operation. The design criteria for a two-phase converter includes frequency selection, inductor value, input/output capacitance, switching MOSFETs, sense resistors, and the compensation network. Follow the same procedure for the four- and sixphase converter design, except for the input and output capacitance. The input and output capacitance requirements vary depending on the operating duty cycle. 18 The examples discussed in this data sheet pertain to a typical application with the following specifications: VIN = +12V VOUT = +1.8V IOUT(MAX) = 52A fSW = 250kHz Peak-to-Peak Inductor Current (∆IL) = 10A Table 1 shows a list of recommended external components (Figure 1) and Table 2 provides component supplier information. Number of Phases Selecting the number of phases for a voltage regulator depends mainly on the ratio of input-to-output voltage (operating duty cycle). Optimum output-ripple cancellation depends on the right combination of operating duty cycle and the number of phases. Use the following equation as a starting point to choose the number of phases: (12) NPH ≈ K/D where K = 1, 2, or 3 and the duty cycle is D = VOUT/VIN. Choose K to make NPH an integer number. For example, converting V IN = +12V to V OUT = +1.8V yields better ripple cancellation in the six-phase converter than in the four-phase converter. Ensure that the output load justifies the greater number of components for multiphase conversion. Generally limiting the maximum output current to 25A per phase yields the most costeffective solution. The maximum ripple cancellation occurs when NPH = K/D. Single-phase conversion requires greater size and power dissipation for external components such as the switching MOSFETs and the inductor. Multiphase conversion eliminates the heatsink by distributing the power dissipation in the external components. The multiple phases operating at given phase shifts effectively increase the switching frequency seen by the input/output capacitors, thereby reducing the input/output capacitance requirement for the same ripple performance. The lower inductance value improves the large-signal response of the converter during a transient load at the output. Consider all these issues when determining the number of phases necessary for the voltage regulator application. Inductor Selection The switching frequency per phase, peak-to-peak ripple current in each phase, and allowable ripple at the output determine the inductance value. ______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041 CSN1 CSP1 SENSE+ VIN SENSEDH1 VCC LX1 PHASE DL1 VCC CLKIN VIN VIN MAX5038/ MAX5041 DH2 LX2 IN DL2 DIFF EAN CSP2 CSN2 EAOUT PGND SGND CLKOUT CSN1 CSP1 CLKIN VIN DH1 VCC LX1 PHASE DL1 MAX5038/ MAX5041 IN VIN DH2 DIFF * LX2 LOAD * DL2 EAN CSP2 EAOUT CSN2 PGND SGND CLKOUT CSN1 CSP1 CLKIN VIN DH1 VCC LX1 PHASE DL1 MAX5038/ MAX5041 IN VIN DH2 DIFF LX2 DL2 EAN EAOUT *FOR MAX5041 ONLY. CSP2 CSN2 PGND SGND CLKOUT TO OTHER MAX5038/MAX5041s Figure 6. Parallel Configuration of Multiple MAX5038/MAX5041s ______________________________________________________________________________________ 19 MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers VIN = +12V C1, C2 2 x 47µF VCC C31 R3 2.2Ω C32 C39 0.1µF R4 PLLCMP CLKIN IN VIN C3–C7 5 x 22µF SENSE- SENSE+ CSN1 CSP1 DH1 Q1 L1 0.6µH R1 1.35mΩ LX1 DL1 C12 0.47µF Q2 D1 BST1 VCC VCC EN D3 C38 4.7µF C40 0.1µF D4 OVPIN VCC R7 VIN MAX5038 (MASTER) DIFF 4 x 22µF C8–C11 EAN RX DH2 R8 Q3 L2 0.6µH EAOUT R2 1.35mΩ LX2 DL2 Q4 D2 CLP1 CLP2 PGND SGND CLKOUT PHASE PGOOD CSN2 CSP2 R6 C13 0.47µF BST2 R9 R5 C36 C34 C35 PGOOD VCC C33 R18 C26–C30, C37 6 x 10µF LOAD C14, C15, C41, C42 2 x 100µF C62 R12 2.2Ω C63 C47 0.1µF R13 EN C16–C25, C43–C46 14 x 270µF PLLCMP IN VIN C48–C51 5 x 22µF CLKIN SENSE-SENSE+ CSN1 CSP1 DH1 L3 0.6µH Q5 R10 1.35mΩ LX1 DL1 C57 0.47µF Q6 D5 BST1 D7 VCC C65 4.7µF C64 0.1µF D8 MAX5038 (SLAVE) R16 VCC VIN DIFF C52–C55 4 x 22µF EAN RX DH2 R17 L4 0.6µH Q7 EAOUT R11 1.35mΩ LX2 DL2 Q8 D6 CLP1 CLP2 R15 R14 C59 C60 C58 PGND C61 SGND PHASE CSN2 CSP2 C56 0.47µF BST2 VCC Figure 7. Four-Phase Parallel Application Circuit (VIN = +12V, VOUT = +1.1V to +3.3V at 104A) 20 ______________________________________________________________________________________ VOUT = +1.1V TO +3.3V AT 104A R19 Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041 Table 1. Component List DESIGNATION QTY C1, C2 2 47µF,16V X5R input-filter capacitors TDK C5750X5R1C476M DESCRIPTION C3–C11 9 22µF, 16V input-filter capacitors TDK C4532X5R1C226M C12, C13 2 0.47µF, 16V capacitors TDK C1608X5R1A474K C14, C15 2 100µF, 6.3V, output-filter capacitors Murata GRM44-1X5R107K6.3 C16–C24, C33 10 270µF, 2V output-filter capacitors Panasonic EEFUE0D271R C25 1 4700pF, 16V X7R capacitor Vishay-Siliconix VJ0603Y471JXJ C26, C28, C30 3 470pF 16V capacitors Murata GRM1885C1H471JAB01 C27, C29 2 0.01µF 50V X7R capacitors Murata GRM188R71H103KA01 C31 1 4.7µF 16V X5R capacitor Murata GRM40-034X5R475k6.3 C32 3 0.1µF 16V X7R capacitors Murata GRM188R71C104KA01 D1, D2 2 Schottky diodes ON-Semiconductor MBRS340T3 D3, D4 2 Schottky diodes ON-Semiconductor MBR0520LT1 L1, L2 2 0.6µH, 27A inductors Panasonic ETQP1H0R6BFX Q1, Q3 2 Upper-power MOSFETs Vishay-Siliconix Si7860DP Q2, Q4 2 Lower-power MOSFETs Vishay-Siliconix Si7886DP R1 1 2.2Ω ±1% resistor R2, R3 4 Current-sense resistors, use two 2.7mΩ resistors in parallel, Panasonic ERJM1WSF2M7U R4 1 7.5kΩ ±1% resistor R5, R6 2 1kΩ ±1% resistors R7 1 4.99kΩ ±1% resistor R8, R9 2 37.4kΩ ±1% resistors Table 2. Component Suppliers PHONE FAX Murata SUPPLIER 770-436-1300 770-436-3030 www.murata.com ON Semiconductor 602-244-6600 602-244-3345 www.on-semi.com Panasonic 714-373-7939 714-373-7183 www.panasonic.com TDK 847-803-6100 847-390-4405 www.tcs.tdk.com 1-800-551-6933 619-474-8920 www.vishay.com Vishay-Siliconix WEBSITE ______________________________________________________________________________________ 21 MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers Selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficiency. The charge/discharge cycle of the gate and drain capacitances in the switching MOSFETs create switching losses. The situation worsens at higher input voltages, since switching losses are proportional to the square of input voltage. Use 500kHz per phase for VIN = +5V and 250kHz or less per phase for VIN > +12V. Although lower switching frequencies per phase increase the peak-to-peak inductor ripple current (∆IL), the ripple cancellation in the multiphase topology reduces the input and output capacitor RMS ripple current. Use the following equation to determine the minimum inductance value: LMIN = (VINMAX − VOUT ) × VOUT VIN × fSW × ∆IL (13) Choose ∆IL equal to about 40% of the output current per phase. Since ∆IL affects the output-ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full-rated efficiency. Choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. Particular applications may require custom-made inductors. Use high-frequency core material for custom inductors. High ∆IL causes large peak-to-peak flux excursion increasing the core losses at higher frequencies. The high-frequency operation coupled with high ∆IL, reduces the required minimum inductance and even makes the use of planar inductors possible. The advantages of using planar magnetics include lowprofile design, excellent current-sharing between phases due to the tight control of parasitics, and low cost. For example, calculate the minimum inductance at VIN(MAX) = +13.2V, VOUT = +1.8V, ∆IL = 10A, and fSW = 250kHz: LMIN = (13.2 − 1.8) × 1.8 = 0.6µH 13.2 × 250k × 10 (14) The average current-mode control feature of the MAX5038/MAX5041 limits the maximum peak inductor current which prevents the inductor from saturating. Choose an inductor with a saturating current greater than the worst-case peak inductor current. 22 Use the following equation to determine the worst-case inductor current for each phase: IL _ PEAK = ∆I 0.051 + L RSENSE 2 (15) where RSENSE is the sense resistor in each phase. Switching MOSFETs when choosing a MOSFET for voltage regulators, consider the total gate charge, RDS(ON), power dissipation, and package thermal impedance. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average gate-drive current from the MAX5038/ MAX5041 output is proportional to the total capacitance it drives from DH1, DH2, DL1, and DL2. The power dissipated in the MAX5038/MAX5041 is proportional to the input voltage and the average drive current. See the VIN and VCC section to determine the maximum total gate charge allowed from all the driver outputs together. The gate charge and drain capacitance (CV2) loss, the cross-conduction loss in the upper MOSFET due to finite rise/fall time, and the I2R loss due to RMS current in the MOSFET RDS(ON) account for the total losses in the MOSFET. Estimate the power loss (PDMOS_) in the high-side and low-side MOSFETs using following equations: PDMOS − HI = (QG × VDD × fSW ) + (16) ⎛ VIN × IOUT × ( t R + t F ) × fSW ⎞ 2 ⎜ ⎟ + 1.4RDS(ON) × I RMS − HI 4 ⎝ ⎠ where QG, RDS(ON), tR, and tF are the upper-switching MOSFET’s total gate charge, on-resistance at +25°C, rise time, and fall time, respectively. IRMS−HI = (I ) D 2 2 DC + I PK + IDC × IPK × (17) 3 where D = V OUT /V IN , I DC = (I OUT - ∆I L )/2 and I PK = (IOUT + ∆IL)/2 ______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers 2 (18) ⎞ ⎛2×C 2 OSS × VIN × fSW + 1.4R ⎟⎟ ⎜⎜ DS(ON) × I RMS − LO 3 ⎠ ⎝ IRMS−LO = (I ) ( ) 1− D 2 2 DC + I PK + IDC × IPK × 3 (19) For example, from the typical specifications in the Applications Information section with VOUT = +1.8V, the high-side and low-side MOSFET RMS currents are 9.9A and 24.1A, respectively. Ensure that the thermal impedance of the MOSFET package keeps the junction temperature at least 25°C below the absolute maximum rating. Use the following equation to calculate maximum junction temperature: (20) TJ = PDMOS x θJ-A + TA ESRIN = Table 3. Peak-to-Peak Output Ripple Current Calculations NUMBER OF PHASES (N) DUTY CYCLE (D) 2 < 50% 2 > 50% EQUATION FOR ∆IP-P V (1− 2D) ∆I = O L × fSW ∆I = The discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple reflected back to the source dictate the capacitance requirement. Increasing the number of phases increases the effective switching frequency and lowers the peak-to-average current ratio, yielding lower input capacitance requirement. The input ripple is comprised of ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high ripple-current capability at the input. Assume the contributions from the ESR and capacitor discharge are equal to 30% and 70%, respectively. Calculate the input capacitance and ESR required for a specified ripple using the following equation: (VIN − VO )(2D − 1) L × fSW 4 0 to 25% V (1− 4D) ∆I = O L × fSW 4 25% to 50% V (1− 2D)(4D − 1) ∆I = O 2 × D × L × fSW 4 > 50% V (2D − 1)(3 − 4D) ∆I = O D × L × fSW 6 < 17% (∆VESR ) ⎛ IOUT ∆IL ⎞ + ⎜ ⎟ ⎝ N 2 ⎠ IOUT × D(1 − D) CIN = N ∆VQ × fSW (21) (22) where IOUT is the total output current of the multiphase converter and N is the number of phases. For example, at V OUT = +1.8V, the ESR and input capacitance are calculated for the input peak-to-peak ripple of 100mV or less yielding an ESR and capacitance value of 1mΩ and 200µF. Output Capacitors The worst-case peak-to-peak and capacitor RMS ripple current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage during step loads determine the capacitance and the ESR requirements for the output capacitors. In multiphase converter design, the ripple currents from the individual phases cancel each other and lower the ripple current. The degree of ripple cancellation depends on the operating duty cycle and the number of phases. Choose the right equation from Table 3 to calculate the peak-to-peak output ripple for a given duty cycle of two-, four-, and six-phase converters. The maximum ripple cancellation occurs when NPH = K / D. V (1− 6D) ∆I = O L × fSW ______________________________________________________________________________________ 23 MAX5038/MAX5041 Input Capacitors PDMOS − LO = (QG × VDD × fSW ) + MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers The allowable deviation of the output voltage during the fast transient load dictates the output capacitance and ESR. The output capacitors supply the load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closed-loop bandwidth of the converter. The resistive drop across the capacitor ESR and capacitor discharge causes a voltage drop during a step load. Use a combination of SP polymer and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output voltage deviation less than or equal to the adaptive voltage-positioning window (∆VOUT). Assume 50% contribution each from the output capacitance discharge and the ESR drop. Use the following equations to calculate the required ESR and capacitance value: ∆V ESROUT = ESR ISTEP (23) I ×t COUT = STEP RESPONSE ∆VQ (24) where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth. Current Limit The average current-mode control technique of the MAX5038/MAX5041 accurately limits the maximum output current per phase. The MAX5038/MAX5041 sense the voltage across the sense resistor and limit the peak inductor current (IL-PK) accordingly. The ON cycle terminates when the current-sense voltage reaches 45mV (min). Use the following equation to calculate maximum current-sense resistor value: 0.045 IOUT N (25) 2.5 × 10−3 RSENSE (26) RSENSE = PDR = Compensation The main control loop consists of an inner current loop and an outer voltage loop. The MAX5038/MAX5041 use an average current-mode control scheme to regulate the output voltage (Figures 3a and 3b). IPHASE1 and IPHASE2 are the inner average current loops. The VEA output provides the controlling voltage for these current sources. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system. A resistive feedback around the VEA provides the best possible response, since there are no capacitors to charge and discharge during large-signal excursions, RF and RIN determine the VEA gain. Use the following equation to calculate the value for RF: RF = IOUT × RIN N × GC × ∆VOUT (27) 0.05 RS (28) GC = where GC is the current-loop gain and N is number of phases. When designing the current-control loop ensure that the inductor downslope (when it becomes an upslope at the CEA output) does not exceed the ramp slope. This is a necessary condition to avoid sub-harmonic oscillations similar to those in peak current-mode control with insufficient slope compensation. Use the following equation to calculate the resistor RCF: RCF ≤ 2 × fSW × L × 102 VOUT × RSENSE For example, the maximum RCF is 12kΩ for RSENSE = 1.35mΩ. CCF provides a low-frequency pole while RCF provides a midband zero. Place a zero at fZ to obtain a phase bump at the crossover frequency. Place a high-frequency pole (fP) at least a decade away from the crossover frequency to achieve maximum phase margin. where PDR is the power dissipation in sense resistors. Select 5% lower value of RSENSE to compensate for any parasitics associated with the PC board. Also, select a non-inductive resistor with the appropriate wattage rating. 24 (29) ______________________________________________________________________________________ Dual-Phase, Parallelable, Average Current-Mode Controllers CCF = 1 2 × π × fZ × RCF 1 CCFF = 2 × π × fP × RCF (30) (31) Pin Configuration TOP VIEW CSP2 1 28 CLKIN CSN2 2 27 CLKOUT 26 BST2 PHASE 3 PC Board Layout PLLCMP 4 Use the following guidelines to layout the switching voltage regulator. CLP2 5 25 DH2 24 LX2 MAX5038A MAX5041A 23 DL2 1) Place the VIN and VCC bypass capacitors close to the MAX5038/MAX5041. SGND 6 2) Minimize the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal. 3) Keep short the current loop from the lower switching MOSFET, inductor, and output capacitor and return to the source of the lower MOSFET. 4) Place the Schottky diodes close to the lower MOSFETs and on the same side of the PC board. 5) Keep the SGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. SENSE+ 8 21 IN SENSE- 9 20 VCC DIFF 10 19 DL1 EAN 11 18 LX1 EAOUT 12 17 DH1 CSP1 13 16 BST1 CSN1 14 15 EN 6) Run the current-sense lines CS+ and CS- very close to each other to minimize the loop area. Similarly, run the remote voltage sense lines SENSE+ and SENSE- close to each other. Do not cross these critical signal lines through power circuitry. Sense the current right at the pads of current-sense resistors. 7) Avoid long traces between the VCC bypass capacitors, driver output of the MAX5038/MAX5041, MOSFET gates and PGND pin. Minimize the loop formed by the VCC bypass capacitors, bootstrap diode, bootstrap capacitor, MAX5038/MAX5041, and upper MOSFET gate. 8) Place the bank of output capacitors close to the load. 22 PGND CLP1 7 SSOP 9) Distribute the power components evenly across the board for proper heat dissipation. 10) Provide enough copper area at and around the switching MOSFETs, inductor, and sense resistors to aid in thermal dissipation. 11) Use at least 4oz copper to keep the trace inductance and resistance to a minimum. Thin copper PC boards can compromise efficiency since high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance. Chip Information TRANSISTOR COUNT: 5431 PROCESS: BiCMOS ______________________________________________________________________________________ 25 MAX5038/MAX5041 Use the following equations to calculate CCF and CCFF: Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages. 2 SSOP.EPS MAX5038/MAX5041 Dual-Phase, Parallelable, Average Current-Mode Controllers 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C D 0.09 0.20 0.004 0.008 SEE VARIATIONS E 0.205 e 0.212 0.0256 BSC 5.20 MILLIMETERS INCHES D D D D D 5.38 MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.33 7.33 0.317 0.397 0.328 0.407 8.07 10.07 8.33 10.33 N 14L 16L 20L 24L 28L 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.025 0∞ 0.037 8∞ 0.63 0∞ 0.95 8∞ N A C B e L A1 D NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. 21-0056 REV. C 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.