19-3583; Rev 2; 7/05 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers The MAX5060/MAX5061 pulse-width modulation (PWM) DC-DC controllers provide high-output-current capability in a compact package with a minimum number of external components. These devices utilize an average-current-mode control that enables optimal use of low RDS(ON) MOSFETs, eliminating the need for external heatsinks even when delivering high output currents. Differential sensing (MAX5060) enables accurate control of the output voltage, while adaptive voltage positioning provides optimum transient response. An internal regulator enables operation with 4.75V to 5.5V or 7V to 28V input voltage ranges. The high switching frequency, up to 1.5MHz, allows the use of low-output inductor values and input capacitor values. This accommodates the use of PC-board-embedded planar magnetics. The MAX5060 features a clock output with 180° phase delay to control a second out-of-phase converter for lower capacitor ripple currents. The MAX5060 also limits the reverse current if the bus voltage becomes higher than the regulated output voltage. The MAX5060 is specifically designed to limit current sinking when multiple power-supply modules are paralleled. The MAX5060/MAX5061 offer an adjustable 0.6V to 5.5V output voltage. The MAX5060 offers an overvoltage protection, power-good signal, and an output enable function. The MAX5060/MAX5061 operate over the automotive temperature range (-40°C to +125°C). The MAX5060 is available in a 28-pin thin QFN package while the MAX5061 is available in a 16-pin TSSOP package. Applications Servers and Workstations Point-of-Load Telecom DC-DC Regulators Networking Systems Features ♦ 4.75V to 5.5V or 7V to 28V Input Voltage Range ♦ Adjustable Output Voltage from 0.6V to 5.5V ♦ Up to 30A Output Current ♦ Can Parallel Outputs For Higher Output Current ♦ Programmable Adaptive Output Voltage Positioning ♦ True-Differential Remote Output Sensing (MAX5060) ♦ Average-Current-Mode Control • Superior Current Sharing Between Paralleled Modules • Accurate Current Limit Eliminates MOSFET and Inductor Derating ♦ Limits Reverse Current Sinking in Paralleled Modules (MAX5060) ♦ Programmable Switching Frequency from 125kHz to 1.5MHz ♦ Integrated 4A Gate Drivers ♦ Clock Output for 180° Out-of-Phase Operation (MAX5060) ♦ Voltage Signal Proportional to Output Current for Load Monitoring (MAX5060) ♦ Output Overvoltage Crowbar Protection (MAX5060) ♦ Programmable Hiccup Current-Limit Threshold and Response Time ♦ Overtemperature Thermal Shutdown RAID Systems High-End Desktop Computers Selector Guide PART MAX5060 MAX5061 OUTPUT Average-Current-Mode DC-DC Controller for 5V/12V/24V Input Bus with CLKOUT, Load Monitoring, Overvoltage, EN Input, SYNC Input, and PGOOD Output Average-Current-Mode DC-DC Controller for 5V/12V/24V Input with SYNC/ENABLE Input Ordering Information TEMP RANGE PIN-PACKAGE PKG CODE MAX5060ATI -40°C to +125°C 28 TQFN-EP* T2855-3 MAX5060ETI -40°C to +85°C 28 TQFN-EP* T2855-3 MAX5061AUE -40°C to +125°C 16 TSSOP-EP* U16E-3 MAX5061EUE 16 TSSOP-EP* U16E-3 PART -40°C to +85°C *EP = Exposed pad. Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5060/MAX5061 General Description MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers ABSOLUTE MAXIMUM RATINGS IN to SGND.............................................................-0.3V to +30V BST to SGND..........................................................-0.3V to +35V DH to LX .......................................-0.3V to [(VBST - VLX_) + 0.3V] DL to PGND (MAX5060).............................-0.3V to (VDD + 0.3V) DL to PGND (MAX5061).............................-0.3V to (VCC + 0.3V) BST to LX..................................................................-0.3V to +6V VCC to SGND............................................................-0.3V to +6V VCC, VDD to PGND ...................................................-0.3V to +6V SGND to PGND .....................................................-0.3V to +0.3V Current Sink in PGOOD ........................................................6mA All Other Pins to SGND...............................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 21.3mW/°C above +70°C)* ......1702mW 28-Pin TQFN (derate 34.5mW/°C above +70°C)* ......2758mW Operating Temperature Range MAX5060A_ _ and MAX5061A_ _ .................-40°C to +125°C MAX5060E_ _ and MAX5061E_ _ ....................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C *Per JEDEC 51 standard. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 5V, VDD = VCC (MAX5060 only), TA = TJ = TMIN to TMAX, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SYSTEM SPECIFICATIONS 7 28 4.75 5.50 Input Voltage Range VIN Quiescent Supply Current IQ EN = VCC or SGND, not switching 2.7 Efficiency η ILOAD = 20A, VIN = 12V, VOUT = 3.3V 90 Short IN and VCC together for 5V input operation 5.5 V mA % OUTPUT VOLTAGE SENSE+ to SENSE- Accuracy (MAX5060) (Note 2) Soft-Start Time EAN Reference Voltage (MAX5061) No load, VCC = 4.75V to 5.5V, fSW = 500kHz 0.594 0.6 0.606 No load, VIN = 7V to 28V, fSW = 500kHz 0.594 0.6 0.606 tSS VREF V Clock Cycles 1024 No load, VCC = 4.75V to 5.5V, no switching 0.591 0.6 0.606 No load, VIN = 7V to 28V, no switching 0.591 0.6 0.606 4.1 4.3 4.5 V STARTUP/INTERNAL REGULATOR VCC Undervoltage Lockout UVLO VCC rising VCC Undervoltage Lockout Hysteresis 200 VCC Output Voltage VIN = 7V to 28V, ISOURCE = 0 to 60mA 4.85 V mV 5.1 5.30 V 1.1 3 Ω MOSFET DRIVERS Output-Driver Impedance Output-Driver Source/Sink Current Nonoverlap Time 2 RON Low or high output, ISOURCE/SINK = 20mA IDH_, IDL_ tNO CDH/DL = 5nF 4 A 35 ns _______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers (VCC = 5V, VDD = VCC (MAX5060 only), TA = TJ = TMIN to TMAX, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1500 kHz OSCILLATOR Switching Frequency Range Switching Frequency 125 fSW Switching Frequency Accuracy CLKOUT Phase Shift (MAX5060) φCLKOUT RT = 500kΩ 121 125 RT = 120kΩ 495 521 129 547 RT = 39.9kΩ 1515 1620 1725 120kΩ ≤ RT ≤ 500kΩ -5 +5 40kΩ ≤ RT ≤ 120kΩ -8 +8 fSW = 125kHz 180 kHz % degrees CLKOUT Output Low Level (MAX5060) VCLKOUTL ISINK = 2mA CLKOUT Output High Level (MAX5060) VCLKOUTH ISOURCE = 2mA 4.5 V tSYNC RT/SYNC (MAX5060), RT/SYNC/EN (MAX5061) 200 ns SYNC Input Clock High Threshold VSYNCH RT/SYNC (MAX5060), RT/SYNC/EN (MAX5061) 2.0 V SYNC Input Clock Low Threshold VSYNCL RT/SYNC (MAX5060), RT/SYNC/EN (MAX5061) SYNC Input-High Pulse Width SYNC Pullup Current ISYNC_OUT SYNC Power-Off Level VSYNC_OFF 0.4 VRT/SYNC = 0V (MAX5060), VRT/SYNC/EN = 0V (MAX5061) 250 V 0.4 V 750 µA 0.4 V CURRENT LIMIT Average Current-Limit Threshold VCL CSP to CSN 24.0 26.9 28.2 mV Reverse Current-Limit Threshold VCLR CSP to CSN (MAX5060) -3.2 -2.3 -0.1 mV Cycle-by-Cycle Current Limit CSP to CSN 60 mV Cycle-by-Cycle Overload Response Time VCSP to VCSN = 75mV 260 ns Hiccup Divider Ratio LIM to VCM, no switching 0.547 Hiccup Reset Delay LIM Input Impedance LIM to SGND 0.558 0.565 V/V 200 ms 55.9 kΩ CURRENT-SENSE AMPLIFIER CSP to CSN Input Resistance Common-Mode Range Input Offset Voltage RCS VCMR(CS) 4 VIN = 7V to 28V 0 kΩ 5.5 V VOS(CS) 0.1 mV Amplifier Gain AV(CS) 34.5 V/V 3dB Bandwidth f3dB 4 MHz _______________________________________________________________________________________ 3 MAX5060/MAX5061 ELECTRICAL CHARACTERISTICS (continued) MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers ELECTRICAL CHARACTERISTICS (continued) (VCC = 5V, VDD = VCC (MAX5060 only), TA = TJ = TMIN to TMAX, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CURRENT-ERROR AMPLIFIER (Transconductance Amplifier) Transconductance Open-Loop Gain gC AVOL(CE) No load 550 µS 50 dB DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF, MAX5060 only) Common-Mode Voltage Range VCMR(DIFF) DIFF Output Voltage VCM Input Offset Voltage VOS(DIFF) Amplifier Gain AV(DIFF) 3dB Bandwidth f3dB Minimum Output-Current Drive SENSE+ to SENSE- Input Resistance 0 VSENSE+ = VSENSE- = 0V -1 0.994 CDIFF = 20pF IOUT(DIFF) RVS +1.0 0.6 +1 1 1.006 3 50 mV V/V MHz 4 VSENSE- = 0V V V mA 100 kΩ V_IOUT AMPLIFIER (V_IOUT, MAX5060 only) Gain-Bandwidth Product VV_IOUT = 2.0V 4 MHz 3dB Bandwidth VV_IOUT = 2.0V 1.0 MHz Output Sink Current 30 Output Source Current 90 Maximum Load Capacitance µA µA 50 V_IOUT Output to IOUT Transfer Function RSENSE = 1mΩ, 100mV ≤ V_IOUT ≤ 5.5V 132.3 Offset Voltage 135 pF 137.7 1 mV/A mV VOLTAGE-ERROR AMPLIFIER (EAOUT) Open-Loop Gain AVOLEA 70 dB Unity-Gain Bandwidth fGBW 3 MHz EAN Input Bias Current IB(EA) VEAN = 2.0V (MAX5060) Error-Amplifier Output-Clamping Voltage VCLAMP(EA) VEAN = 0.4V, VEAOUT = GND (MAX5061) With respect to VCM (MAX5060), with respect to SGND (MAX5061) -0.2 0.03 +0.2 µA 883 930 976 mV 87.5 90 92.5 %VOUT 0.4 V 1 µA POWER-GOOD AND OVERVOLTAGE PROTECTION (MAX5060 only) PGOOD Trip Level PGOOD Output Low Level PGOOD Output Leakage Current OVI Trip Threshold OVI Input Bias Current 4 VUV VPGLO IPG OVPTH IOVI PGOOD goes low when VOUT is below this threshold ISINK = 4mA PGOOD = VCC With respect to SGND 1.244 1.276 0.2 _______________________________________________________________________________________ 1.308 V µA 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers (VCC = 5V, VDD = VCC (MAX5060 only), TA = TJ = TMIN to TMAX, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.437 2.5 2.562 V 16.5 µA ENABLE INPUTS EN Input High Voltage (MAX5060) VEN EN rising EN Input Hysteresis (MAX5060) EN Pullup Current (MAX5060) 0.28 IEN 13.5 RT/SYNC/EN Input High Voltage Enable (MAX5061) VRT/SYNC/EN_H 1.6 RT/SYNC/EN Input Low Voltage Disable (MAX5061) VRT/SYNC/EN_L 15 V V 0.4 V THERMAL SHUTDOWN Thermal Shutdown Temperature rising Thermal-Shutdown Hysteresis +150 °C 30 °C Note 1: Specifications at TA = +25°C are 100% tested. Specifications over the temperature range are guaranteed by design. Note 2: Does not include an error due to finite error amplifier gain (see the Voltage-Error Amplifier section). _______________________________________________________________________________________ 5 MAX5060/MAX5061 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (TA = +25°C, Figures 1 and 2, unless otherwise noted.) EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE 80 70 60 60 50 50 60 50 40 40 30 30 30 20 20 VOUT = 3.3V fSW = 250kHz 20 VOUT = 0.6V fSW = 250kHz 10 0 4 6 8 10 12 14 16 18 20 0 0 2 4 6 10 12 14 16 18 20 8 OUTPUT CURRENT (A) OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE 80 90 80 70 60 VOUT = 0.6V 50 VOUT = 1V 40 η (%) 70 VOUT = 5V VOUT = 1.8V VOUT = 0.6V 60 VOUT = 1.8V VOUT = 1V 50 VOUT = 3.3V 40 30 30 VOUT = 3.3V 20 10 2 4 6 8 10 12 14 16 18 20 2 4 6 8 SUPPLY CURRENT vs. TEMPERATURE CURRENT-SENSE THRESHOLD vs. OUTPUT VOLTAGE VIN = 12V fSW = 250kHz CDL/CDH = 22nF 62 -15 10 35 TEMPERATURE (°C) 60 85 27.0 1 500 700 900 1100 1300 1500 25.5 25.0 24.5 24.0 VIN = 12V fSW = 250kHz R1 = 1mΩ VOUT = 1.5V 23.5 VIN = 12V fSW = 250kHz 0 300 26.0 CURRENT LIMIT (A) 27.5 26.0 -40 100 MAX5060 toc08 28.0 26.5 60 20 HICCUP CURRENT LIMIT vs. REXT 28.5 (VCSP - VCSN) (mV) 64 VIN = 12V 30 FREQUENCY (kHz) 29.0 MAX5060 toc07 66 VIN = 24V 40 10 12 14 16 18 20 OUTPUT CURRENT (A) 68 EXTERNAL CLOCK NO DRIVER LOAD 0 0 OUTPUT CURRENT (A) 70 10 12 14 16 18 20 VIN = 5V 0 0 8 10 VIN = 5V fSW = 500kHz 10 0 6 50 20 VIN = 12V fSW = 250kHz 4 SUPPLY CURRENT (IQ) vs. FREQUENCY 60 MAX5060 toc05 90 2 OUTPUT CURRENT (A) 100 MAX5060 toc04 100 0 SUPPLY CURRENT (mA) 2 VIN = 24V VOUT = 3.3V fSW = 125kHz 10 0 0 η (%) 70 VIN = 12V 40 10 6 80 MAX5060 toc06 70 90 MAX5060 toc09 VIN = 12V η (%) η (%) 80 VIN = 5V 90 η (%) VIN = 5V 100 MAX5060 toc02 90 EFFICIENCY vs. OUTPUT CURRENT 100 MAX5060 toc01 100 MAX5060 toc03 EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE SUPPLY CURRENT (mA) MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers 23.0 2 3 VOUT (V) 4 5 0 4 8 12 REXT (MΩ) _______________________________________________________________________________________ 16 20 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers VV_IOUT (V) 1.450 RF/RIN = 10 100 2 VIN = 7V 1.5 4 6 MAX5060 toc12 VIN = 5V 4.85 0 0 10 12 14 16 18 20 VIN = 12V VIN = 24V 0.5 8 5.05 4.95 1.0 VIN = 12V fSW = 250kHz VOUT = 1.5V 0 VIN = 24V 5 10 4.75 20 15 0 25 50 75 100 125 OUTPUT CURRENT (A) LOAD CURRENT (A) VCC LOAD CURRENT (mA) DRIVER RISE TIME vs. DRIVER LOAD CAPACITANCE DRIVER FALL TIME vs. DRIVER LOAD CAPACITANCE HIGH-SIDE DRIVER (DH) SINK AND SOURCE CURRENT VIN = 12V fSW = 250kHz 100 80 80 tF (ns) 60 DL 40 VIN = 12V fSW = 250kHz 150 MAX5060 toc15 MAX5060 toc14 1.425 1.400 1.375 5.15 VIN = 12V 2.0 VCC (V) RF/RIN = 20 1.500 1.475 VOUT = 3.3V R1 = 1mΩ MAX5060 2.5 5.25 MAX5060 toc11 RF/RIN = 40 1.350 1.325 1.300 tR (ns) 3.0 MAX5060 toc10 1.600 1.575 1.550 1.525 VCC LOAD REGULATION vs. INPUT VOLTAGE V_IOUT VOLTAGE vs. LOAD CURRENT MAX5060 toc13 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE vs. OUTPUT CURRENT AND ERROR AMPLIFIER GAIN (RF/RIN) CLOAD = 22nF VIN = 12V 60 2A/div DL 40 DH DH 20 20 0 0 1 6 11 16 21 1 CAPACITANCE (nF) 6 11 16 100ns/div 21 CAPACITANCE (nF) LOW-SIDE DRIVER (DL) SINK AND SOURCE CURRENT HIGH-SIDE DRIVER (DH) RISE TIME HIGH-SIDE DRIVER (DH) FALL TIME MAX5060 toc17 MAX5060 toc16 MAX5060 toc18 CLOAD = 22nF VIN = 12V CLOAD = 22nF VIN = 12V CLOAD = 22nF VIN = 12V 2V/div 3A/div 100ns/div 40ns/div 2V/div 40ns/div _______________________________________________________________________________________ 7 MAX5060/MAX5061 Typical Operating Characteristics (continued) (TA = +25°C, Figures 1 and 2, unless otherwise noted.) MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Typical Operating Characteristics (continued) (TA = +25°C, Figures 1 and 2, unless otherwise noted.) LOW-SIDE DRIVER (DL) RISE TIME LOW-SIDE DRIVER (DL) FALL TIME MAX5060 toc19 MAX5060 toc21 CLOAD = 22nF VIN = 12V CLOAD = 22nF VIN = 12V 2V/div 40ns/div VIN = 12V VOUT = 1.5V IOUT = 20A 2V/div 50mV/div 40ns/div INPUT STARTUP RESPONSE 1µs/div LOAD-TRANSIENT RESPONSE ENABLE STARTUP RESPONSE MAX5060 toc22 MAX5060 toc24 MAX5060 toc23 VIN = 12V VOUT = 1.5V IOUT = 20A VPGOOD 5V/div VPGOOD 5V/div VOUT 200mV/div VOUT 2V/div VOUT 2V/div VIN = 12V VOUT = 1.5V IOUT = 20A VIN 5V/div VEN 2V/div 0 2ms/div 2ms/div 100µs/div REVERSE CURRENT SINK vs. TEMPERATURE REVERSE CURRENT SINK AT INPUT TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.0V) REVERSE CURRENT SINK AT INPUT TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V) MAX5060 toc27 MAX5060 toc25 VIN = 12V V0UT = 1.5V R1 = 1mΩ 2.2 IOUT 10A/div VIN = 12V VOUT = 3.3V ISTEP = 5A TO 20A SLEW = 2A/µs MAX5060 toc26 2.4 SINK CURRENT (A) OUTPUT RIPPLE MAX5060 toc20 VEXTERNAL = 3.3V 2.0 5A/div 2A/div VEXTERNAL = 2V 1.8 1.6 1.4 -40 -15 10 35 60 85 200µs/div 200µs/div TEMPERATURE (°C) 8 _______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers REVERSE CURRENT SINK AT ENABLE TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.0V) REVERSE CURRENT SINK AT ENABLE TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V) 2A/div FREQUENCY vs. RT 10,000 5A/div MAX5060 toc30 MAX5060 toc29 fSW (kHz) MAX5060 toc28 VIN = 12V 1000 100 200µs/div 30 200µs/div 110 70 190 150 270 230 350 310 510 430 390 470 RT (kΩ) FREQUENCY vs. TEMPERATURE OUTPUT SHORT-CIRCUIT WAVEFORM VIN = 12V 258 256 MAX5060 toc31 MAX5060 toc32 260 VIN = 12V VOUT = 3.3V CEN = 0.47µF RLIM = OPEN IOUT 10A/div fSW (kHz) 254 252 250 VOUT 2V/div 248 246 244 EN 2V/div 242 240 -40 -15 10 35 60 85 40ms/div TEMPERATURE (°C) SYNC, CLKOUT, AND LX WAVEFORM MAX5060 toc33 SYNC 5V/div CLKOUT 5V/div VIN = 12V fSW = 250kHz LX 10V/div 1µs/div _______________________________________________________________________________________ 9 MAX5060/MAX5061 Typical Operating Characteristics (continued) (TA = +25°C, Figures 1 and 2, unless otherwise noted.) 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers MAX5060/MAX5061 Pin Description PIN 10 NAME FUNCTION MAX5060 MAX5061 1 3 PGND 2, 7 8 N.C. 3 4 DL Low-Side Gate-Driver Output. Synchronous MOSFET gate driver. 4 5 BST Boost Flying-Capacitor Connection. Reservoir capacitor connection for the highside MOSFET driver supply. Connect a 0.47µF ceramic capacitor between BST and LX. 5 6 LX Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for the high-side driver. 6 7 DH High-Side Gate-Driver Output. Drives the gate of the high-side MOSFET. 8, 22, 25 16 SGND Signal Ground. Ground connection for the internal control circuitry. Connect SGND and PGND together at one point near the input bypass capacitor return. 9 — CLKOUT Oscillator Output. Rising edge of CLKOUT is phase-shifted from rising edge of DH by 180°. 10 — PGOOD Power-Good Output. PGOOD is an open-drain output that goes low when the programmed output voltage falls out of regulation. The power-good comparator threshold is 90% of the programmed output voltage. 11 — EN Output Enable. Drive EN high or leave unconnected for normal operation. Drive EN low to shut down the power drivers. EN has an internal 15µA pullup current. Connect a capacitor from EN to SGND to program the hiccup mode duty cycle. 12 — RT/SYNC Switching Frequency Programming and Chip-Enable Input. Connect a resistor from RT/SYNC to SGND to set the internal oscillator frequency. Drive RT/SYNC externally to synchronize the switching frequency with system clock. 13 — V_IOUT Voltage-Source Output Proportional to the Output Load Current. The voltage at V_IOUT is 135 x ILOAD x RS. 14 10 LIM Current-Limit Setting Input. Connect a resistor from LIM to SGND to set the hiccup current-limit threshold. Connect a capacitor from LIM to SGND to ignore short output overcurrent pulses. 15 — OVI Overvoltage Protection Circuit Input. Connect OVI to DIFF. When OVI exceeds +12.7% above the programmed output voltage, DH is latched low and DL is latched high. Toggle EN low to high or recycle the power to reset the latch. 16 11 CLP Current-Error-Amplifier Output. Compensate the current loop by connecting an RC network to ground. Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and VDD (MAX5060)/VCC (MAX5061) bypass capacitor returns together. No Connection. Not internally connected. ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers PIN NAME FUNCTION MAX5060 MAX5061 17 12 EAOUT 18 13 EAN Voltage-Error-Amplifier Inverting Input. Receives a signal from the output of the differential remote-sense amplifier (MAX5060). Connect the center tap of the resistor-divider from the output to SGND (MAX5061). 19 — DIFF Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier whose inputs are SENSE+ and SENSE-. 20 14 CSN Current-Sense Differential Amplifier Negative Input. The differential voltage between CSN and CSP is amplified internally by the current-sense amplifier (gain = 34.5) to measure the inductor current. 21 15 CSP Current-Sense Differential Amplifier Positive Input. The differential voltage between CSP and CSN is amplified internally by the current-sense amplifier (gain = 34.5) to measure the inductor current. 23 — SENSE- Differential Output-Voltage-Sensing Negative Input. SENSE- is used to sense a remote load. Connect SENSE- to VOUT- or PGND at the load. Differential Output-Voltage-Sensing Positive Input. SENSE+ is used to sense a remote load. Connect SENSE+ to VOUT+ at the load. The device regulates the difference between SENSE+ and SENSE- according to the preset reference voltage of 0.6V. Voltage-Error-Amplifier Output. Connect to the external gain-setting feedback resistor. The error-amplifier gain-setting resistors determine the amount of adaptive voltage positioning. 24 — SENSE+ 26 1 IN 27 2 VCC Internal +5V Regulator Output. VCC is derived from the IN voltage. Bypass VCC to SGND with 4.7µF and 0.1µF ceramic capacitors. For MAX5061, connect an additional 0.1µF bypass capacitor from VCC to PGND. 28 — VDD Supply Voltage for Low-Side and High-Side Drivers. Connect a parallel combination of 0.1µF and 1µF ceramic capacitors to PGND and a 1Ω resistor to VCC to filter out the high peak currents of the driver from the internal circuitry. Switching Frequency Programming and Chip-Enable Input. Connect a resistor from RT/SYNC/EN to SGND to set the internal oscillator frequency. Drive RT/SYNC/EN externally to synchronize the switching frequency with system clock. If RT/SYNC/EN is held low for 50µs, the device turns off the output drivers. — 9 RT/SYNC/EN — — EP Supply Voltage Connection. Connect IN to VCC for a +5V system. Exposed Paddle. Connect the exposed paddle to a copper pad (SGND) to improve power dissipation. ______________________________________________________________________________________ 11 MAX5060/MAX5061 Pin Description (continued) 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers MAX5060/MAX5061 Typical Application Circuit VIN = 12V C1, C2 R13 IN RH C3 VIN IN REXT SENSE- SENSE+ CSN CSP DH LIM Q1 RL C3–C7 L1 C4 R1 LX DL EN ON OFF V_IOUT (VOLTAGE α IOUT) C5 C12 Q2 C12 C13 D1 LOAD MAX5060 RIN V_IOUT BST OVI VCC D3 C10 DIFF VDD EAOUT RF CLP C11 R3 EAN RT/ PGND SGND PGOOD SYNC C8 SYNC R5 C6 C7 R11 PGOOD Figure 1. Typical Application Circuit, VIN = 12V (MAX5060) 12 ______________________________________________________________________________________ VOUT = 0.6V TO 5.5V AT 20A 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers VIN = 12V C1, C2 R13 IN C13* RC1 C3 VIN CSN IN VCC CSP RC2 RT/SYNC/EN SYNC OFF C13–C16 L1 RT VOUT = 0.6V TO 5.5V AT 20A R1 LX MAX5061 ON Q1 DH C12 Q2 DL C10 C11 D1 REXT LOAD C4 LIM D3 BST VCC C5 VCC R5 C7* C8 C9 CLP C6 PGND SGND EAN EAOUT RF RH RL * USE C13 = 47pf AND C7 = 4.7µF/6.3V (CERAMIC). Figure 2. Typical Application Circuit, VIN = +12V (MAX5061) ______________________________________________________________________________________ 13 MAX5060/MAX5061 Typical Application Circuit (continued) 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers MAX5060/MAX5061 Block Diagram VCC IS EN 0.5V x VCC 5V LDO REGULATOR IN VCC UVLO POR TEMP SENSOR TO INTERNAL CIRCUITS LIM HICCUP MODE CURRENT LIMIT 126.7kΩ MAX5060 VCM 100kΩ 0.5 x VCLAMP CLP CA CSN Q R Q RT Ct AV = 34.5 CSP S VCM gm = 500µS VDD PWM COMPARATOR CEA AV = 4 BST V_IOUT VCLAMP HIGH VCLAMP LOW SGND RAMP CPWM S Q DH LX 2 x fS (V/s) CLK RT/SYNC OSCILLATOR R Q DL CLKOUT RAMP GENERATOR DIFF +0.6V SENSESENSE+ PGND PGOOD N DIFF AMP 0.1 x VREF EAOUT ERROR AMP EAN 0.12 x VREF OVP LATCH VEA LATCH SOFTSTART OVP COMP VREF = 0.6V VCM (0.6V) CLEAR ON UVLO RESET OR ENABLE LOW OVI Figure 3. Functional Diagram (MAX5060) 14 ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers VCC IS 0.5V x VCC 5V LDO REGULATOR IN VCC UVLO POR TEMP SENSOR TO INTERNAL CIRCUITS LIM HICCUP MODE CURRENT LIMIT 126.7kΩ MAX5061 VCM 100kΩ 0.5 x VCLAMP CLP CA CSN SGND CLK RAMP GENERATOR Q RT gm = 500µS VCLAMP HIGH OSCILLATOR R VCM PWM COMPARATOR CEA RT/SYNC/EN Q Ct AV = 34.5 CSP S RAMP CPWM VCC S Q BST DH LX 2 x fS (V/s) R Q DL PGND EAOUT ERROR AMP EAN VEA SOFTSTART VREF = 0.6V Figure 4. Functional Diagram (MAX5061) ______________________________________________________________________________________ 15 MAX5060/MAX5061 Block Diagram (continued) MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Detailed Description The MAX5060/MAX5061 are high-performance averagecurrent-mode PWM controllers. The average-currentmode control technique offers inherently stable operation, reduces component derating and size by accurately controlling the inductor current. This also improves the current-sharing accuracy when paralleling multiple converters. The devices achieve high efficiency, at high current (up to 30A) with a minimum number of external components. The high- and low-side drivers source and sink up to 4A for lower switching frequencies while driving high-gate-charge MOSFETs. The MAX5060’s CLKOUT output is 180° out-of-phase with respect to the high-side driver. The CLKOUT drives a second MAX5060 or a MAX5061 regulator out-ofphase, reducing the input capacitor ripple current and increasing the load current capacity. The paralleling capability of the MAX5060/MAX5061 improves design flexibility in applications requiring upgrades (higher load). The MAX5060/MAX5061 consist of an inner averagecurrent-loop controlled by an outer-voltage-loop voltageerror amplifier (VEA). The combined action of the inner current loop and outer voltage loop corrects the output voltage errors by adjusting the inductor current. The inductor current is sensed across a current-sense resistor. The differential amplifier (MAX5060) senses the output right at the load for true-differential output voltage sensing. The sensed voltage is compared against internal 0.6V reference at the error-amplifier input. The output voltage can be set from 0.6V to 5.5V (IN ≥ 7V) using a resistor-divider at SENSE+ and SENSE-. IN, VCC, and VDD The MAX5060/MAX5061 accept a 4.75V to 5.5V or 7V to 28V input voltage range. All internal control circuitry operates from an internally regulated nominal voltage of 5V (VCC). For input voltages of 7V or greater, the internal VCC regulator steps the voltage down to 5V. The VCC output voltage is a regulated 5V output capable of sourcing up to 60mA. Bypass the VCC to SGND with 4.7µF and 0.1µF low-ESR ceramic capacitors for high-frequency noise rejection and stable operation. The MAX5060 uses VDD to power the low-side and high-side drivers, while the MAX5061 uses the VCC to power internal circuitry as well as the low- and highside driver supply. In the case of the MAX5061, use 16 one or more 0.1µF low-ESR ceramic capacitors between VCC and PGND to reject the noise spikes due to high-current driver switching. The TQFN-28 and TSSOP-16 are thermally enhanced packages and can dissipate up to 2.7W and 1.7W, respectively. The high-power packages allow the high-frequency, high-current buck converter to operate from a 12V or 24V bus. Calculate power dissipation in the MAX5060/MAX5061 as a product of the input voltage and the total VCC regulator output current (I CC). I CC includes quiescent current (I Q) and gate-drive current (IDD): PD = VIN x ICC ICC = IQ + [fSW x (QG1 + QG2)] where QG1 and QG2 are the total gate charge of the low-side and high-side external MOSFETs at VGATE = 5V, IQ is 3.5mA (typ), and fSW is the switching frequency of the converter. Undervoltage Lockout (UVLO) The MAX5060/MAX5061 include an undervoltage lockout with hysteresis and a power-on-reset circuit for converter turn-on and monotonic rise of the output voltage. The UVLO rising threshold is internally set at 4.35V with a 200mV hysteresis. Hysteresis at UVLO eliminates chattering during startup. Most of the internal circuitry, including the oscillator, turns on when the input voltage reaches 4V. The MAX5060/MAX5061 draw up to 3.5mA of current before the input voltage reaches the UVLO threshold. Soft-Start The MAX5060/MAX5061 has an internal digital soft-start for a monotonic, glitch-free rise of output voltage. Softstart is achieved by the controlled rise of error amplifier dominant input in steps using a 5-bit counter and a 5-bit DAC. The soft-start DAC generates a linear ramp from 0 to 0.7V. This voltage is applied to the error amplifier at a third (noninverting) input. As long as the soft-start voltage is lower than the reference voltage, the system will converge to that lower reference value. Once the softstart DAC output reaches 0.6V, the reference takes over and the DAC output continues to climb to 0.7V assuring that it is out of the way of the reference voltage. ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers The oscillator also generates a 2VP-P voltage-ramp signal for the PWM comparator and a 180° out-of-phase clock signal for CLKOUT (MAX5060) to drive a second DC-DC converter out-of-phase. RT = Synchronization The MAX5060/MAX5061 can be easily synchronized by connecting an external clock to RT/SYNC (MAX5060) or RT/SYNC/EN (MAX5061). If an external clock is present, then the internal oscillator is disabled and the external clock is used to run the MAX5060/MAX5061. If the external clock is removed, the absence of clock for 32µs is detected and the circuit starts switching from the internal oscillator. Pulling RT/SYNC on the MAX5060 or RT/SYNC/EN on the MAX5061 to ground for at least 50µs disables the converter. 6.25 × 1010 fSW for 40kΩ ≤ RT ≤ 120kΩ: RT = Use an open-collector transistor to synchronize the MAX5060/MAX5061 with the external system clock (see Figures 1 and 2). 10 6.40 × 10 fSW RCF CSN CSP CCF CCFF CLP CA RF* SENSE+ SENSE- VIN RIN* DIFF AMP IL CEA VEA CPWM RS VOUT DRIVE VREF + VCM COUT LOAD MAX5060 *RF AND RIN ARE EXTERNAL. Figure 5. MAX5060 Control Loop ______________________________________________________________________________________ 17 MAX5060/MAX5061 Internal Oscillator The internal oscillator generates a clock with the frequency proportional to the inverse of RT. The oscillator frequency is adjustable from 125kHz to 1.5MHz with better than 8% accuracy using a single resistor connected from RT/SYNC to SGND (MAX5060) and from RT/SYNC/EN to SGND (MAX5061). The frequency accuracy avoids the over-design, size, and cost of passive filter components like inductors and capacitors. Use the following equation to calculate the oscillator frequency: for 120kΩ ≤ RT ≤ 500kΩ: MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Control Loop The MAX5060/MAX5061 use an average-current-mode control scheme to regulate the output voltage (Figure 5). The main control loop consists of an inner current loop and an outer voltage loop. The inner loop controls the output current (IPHASE), while the outer loop controls the output voltage. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system. The current loop consists of a current-sense resistor (RSENSE), a current-sense amplifier (CA), a currenterror amplifier (CEA), an oscillator providing the carrier ramp, and a PWM comparator (CPWM) (Figure 6). The precision CA amplifies the sense voltage across RS by a factor of 34.5. The inverting input to the CEA senses the CA output. The CEA output is the difference between the voltage-error-amplifier output (EAOUT) and the amplified voltage from the CA. The RC compensation networks connected to CLP provide external frequency compensation for the CEA. The start of every clock cycle enables the high-side drivers and initiates a PWM ON cycle. Comparator CPWM compares the output voltage from the CEA with a 0 to 2V ramp from the oscillator. The PWM ON cycle terminates when the ramp voltage exceeds the error voltage. The MAX5060 outer voltage control loop consists of the differential amplifier (DIFF AMP), reference voltage, and VEA. The unity-gain differential amplifier provides truedifferential remote sensing of the output voltage. The differential amplifier output connects to the inverting input (EAN) of the VEA. For MAX5061, the DIFF AMP is bypassed and the inverting input is available to the pin for direct feedback. The noninverting input of the VEA is internally connected to an internal precision reference voltage. The MAX5060/MAX5061 reference voltage is set to 0.6V. The VEA controls the inner current loop (Figure 4). Use a resistive feedback network to set the VEA gain as required by the adaptive voltage-positioning circuit (see the Adaptive Voltage Positioning section). VDD PEAK-CURRENT COMPARATOR 60mV CLP AV = 34.5 CSP CA CSN MAX5060 gm = 550µS CEA GMIN BST PWM COMPARATOR S Q LX 2 x fS (V/s) CLK R Q SHDN Figure 6. Phase Circuit 18 DH CPWM RAMP ______________________________________________________________________________________ DL PGND 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Peak-Current Comparator The peak-current comparator provides a path for fast cycle-by-cycle current limit during extreme fault conditions such as an output inductor malfunction (Figure 5). Note the average current-limit threshold of 26.9mV still limits the output current during short-circuit conditions. To prevent inductor saturation, select an output inductor with a saturation current specification greater than the average current limit. Proper inductor selection ensures that only the extreme conditions trip peak-current comparator, such as a broken output inductor. The 60mV threshold for triggering the peak-current limit is twice the full-scale average current-limit voltage threshold. The peak-current comparator has only a 260ns delay. Current-Error Amplifier The MAX5060/MAX5061 has a transconductance current-error amplifier (CEA) with a typical gm of 550µS and 320µA output sink- and source-current capability. The current-error amplifier output CLP, serves as the inverting input to the PWM comparator. CLP is externally accessible to provide frequency compensation for the inner current loops (Figure 5). Compensate (CEA) so the inductor current down slope, which becomes the up slope to the inverting input of the PWM comparator, is less than the slope of the internally generated voltage ramp (see the Compensation section). PWM Comparator and R-S Flip-Flop The PWM comparator (CPWM) sets the duty cycle for each cycle by comparing the output of the current-error amplifier to a 2VP-P ramp. At the start of each clock cycle, an R-S flip-flop resets and the high-side driver (DH) turns on. The comparator sets the flip-flop as soon as the ramp voltage exceeds the CLP voltage, thus terminating the ON cycle (Figure 5). Differential Amplifier (MAX5060) The differential amplifier (DIFF AMP) facilitates outputvoltage remote sensing at the load (Figure 5). It provides true-differential output voltage sensing while rejecting the common-mode voltage errors due to highcurrent ground paths. Sensing the output voltage directly at the load provides accurate load voltage sensing in high-current environments. The VEA provides the difference between the differential amplifier output (DIFF) and the desired output voltage. The differential amplifier has a bandwidth of 3MHz. The difference between SENSE+ and SENSE- is regulated to 0.6V for the MAX5060. Connect SENSE+ to the center of the resistive divider from the output to SENSE-. Connect SENSE- to PGND near the load. Voltage-Error Amplifier The VEA sets the gain of the voltage control loop. The VEA determines the error between the differential amplifier output and the internal reference voltage. The VEA output clamps to 930mV relative to the internally generated common-mode voltage (VCM, 0.6V), thus limiting the maximum output current. The maximum average current-limit threshold is equal to the maximum clamp voltage of the VEA divided by the gain (34.5) of the current-sense amplifier. This results in accurate settings for the average maximum current for each phase. Set the VEA gain using RF and RIN (see Figures 1 and 2) for the amount of output voltage positioning required within the rated current range as discussed in the Adaptive Voltage Positioning section. The finite gain of the VEA introduces an error in the output voltage setting. Use the following equation to calculate the output voltage at no load condition. MAX5060: ⎛ R ⎞ ⎛ R + RL ⎞ VOUT(NL) = ⎜1 + IN ⎟ × ⎜ H × VREF RF ⎠ ⎝ RL ⎟⎠ ⎝ where RH and RL are the feedback resistor network (see the Typical Application Circuits) and VREF = 0.6V. MAX5061: The error amplifier output (EAOUT), which is compared against the output of the current amplifier (CA), may not reduce down to zero due to the saturation voltage of its output stage. This requires the converter to be loaded with a minimum load to prevent it from slipping out of regulation. The minimum load requirement can be eliminated by adding some DC bias voltage between CSP and CSN. See the Typical Application Circuit (Figure 2). Use RC1 and RC2 to generate approximately 3mV DC bias at CSP with respect to CSN. Use the following equation to calculate the values of RC1 and RC2. RC1 = (VCC − VOUT ) × RC2 (0.002) + (0.25 × ∆IL × RSENSE ) ______________________________________________________________________________________ 19 MAX5060/MAX5061 Current-Sense Amplifier The differential current-sense amplifier (CA) provides a DC gain of 34.5. The maximum input offset voltage of the current-sense amplifier is 1mV and the commonmode voltage range is 0 to 5.5V (IN = 7V to 28V). The current-sense amplifier senses the voltage across a current-sense resistor. The maximum common-mode voltage is 3.6V when VIN = 5V. The common-mode voltage range determines the maximum output voltage of the buck converter. where ∆IL = peak-to-peak inductor current. Choose RC2 = 10Ω, V CC = 5.1V, and R SENSE is a currentsense resistor. Note that the current limit of MAX5061 is reduced by 3mV / RSENSE. The no-load output voltage depends on the RH, RF, VREF (0.6V) and the fixed DC bias voltage at CSP CSN. The following equation assumes a 3mV bias voltage at CSP - CSN. V V − 0.1 VOUT(NL) = [( REF + REF ) × RH ] + VREF RL RF VOLTAGE-POSITIONING WINDOW MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers VCNTR + ∆VOUT/2 VCNTR VCNTR ∆VOUT/2 Adaptive Voltage Positioning Powering new-generation processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher than the output voltage during nominally loaded conditions allows a larger downward-voltage excursion when the output current suddenly increases. Regulating at a lower output voltage under a heavy load allows a larger upward-voltage excursion when the output current suddenly decreases. Allowing a larger voltage-step excursion reduces the required number of output capacitors or allows for the use of higher ESR capacitors. Voltage positioning may require the output to regulate away from a center value. Define the center value as the voltage where the output drops (∆VOUT/2) at one half the maximum output current (Figure 7). Set the voltage-positioning window (∆VOUT) using the resistive feedback of the voltage-error amplifier (VEA). Use the following equations to calculate the voltagepositioning window (Figure 5): MAX5060: ∆VOUT = IOUT × RIN RH + RL × GC × RF RL 0.0289 GC = RS MAX5061: I x RH ∆VOUT = OUT Gc x RF RIN and RF are the input and feedback resistors of VEA. GC is the current-loop transconductance and RS is the current-sense resistor. 20 NO LOAD 1/2 LOAD FULL LOAD LOAD (A) Figure 7. Defining the Voltage-Positioning Window MOSFET Gate Drivers (DH_, DL_) The high-side (DH) and low-side (DL) drivers drive the gates of external n-channel MOSFETs (Figures 1 and 2). The drivers’ 4A peak sink- and source-current capability provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced cross-conduction losses. For modern CPU voltage-regulating module applications, where the duty cycle is less than 50%, choose high-side MOSFETs (Q1) with a moderate RDS(ON) and a very low gate charge. Choose low-side MOSFETs (Q2) with very low RDS(ON) and moderate gate charge. Size the high-side and lowside MOSFETs to handle the peak and RMS currents during overload conditions. The driver block also includes a logic circuit that provides an adaptive nonoverlap time to prevent shoot-through currents during transition. The typical nonoverlap time is 35ns between the high-side and low-side MOSFETs. BST The MAX5060 uses VDD to power the low- and high-side MOSFET drivers. The low- and high-side drivers in the MAX5061 are powered from VCC. The high-side driver derives its power through a bootstrap capacitor and VDD supplies power internally to the low-side driver. Connect a 0.47µF low-ESR ceramic capacitor between BST and LX. Connect a Schottky rectifier from BST to VDD on the MAX5060, or to VCC on the MAX5061. Reduce the PC board area formed by the boost capacitor and rectifier. ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers PGOOD Generator (MAX5060) A PGOOD comparator compares the differential amplifier output (DIFF) against 0.90 times the set output voltage for undervoltage monitoring (see Figure 8). Use a 10kΩ pullup resistor from PGOOD to a voltage source less than or equal to VCC. Current Limit The VEA output is clamped to 930mV with respect to the common-mode voltage (VCM). Average current-mode control has the ability to limit the average current sourced by the converter during a fault condition. When a fault condition occurs, the VEA output clamps to 930mV with respect to the common-mode voltage (0.6V) to limit the maximum current sourced by the converter to ILIMIT = 26.9mV/RS. The hiccup current limit overrides the average current limit. The MAX5060/MAX5061 include hiccup currentlimit protection to reduce the power dissipation during a fault condition. The hiccup current-limit circuit derives inductor current information from the output of the current amplifier. This signal is compared against one half of VCLAMP(EA). With no resistor connected from the LIM pin to ground, the hiccup current limit is set at 90% of the full-load average current limit. Use REXT to increase the hiccup current limit from 90% to 100% of the fullload average limit (see Figures 1 and 2). The hiccup current limit can be disabled by connecting LIM to SGND. In this case, the circuit will follow the average current-limit action during overload conditions. An internal clamp (MAX5060) limits the continuous reverse current the buck converter sinks when a higher voltage is applied at the output. The reverse current limit translated at the current-amplifier input is -2.3mV (typ). The maximum reverse current the converter sinks depends on the current-sense resistor. Normally it is about 10% of the full load current. Overvoltage Protection (OVP) (MAX5060) The OVP comparator compares the OVI input to the overvoltage threshold. The overvoltage threshold is typically +12.7% above the internal 0.6V reference voltage. A detected overvoltage event latches the comparator output forcing the power stage into the OVP state. In the OVP state, the high-side MOSFET turns off and the low-side MOSFET latches on. Connect DIFF to OVI for differential output sensing and overvoltage protection. Alternately, use a separate sensing network from VOUT to SGND. Connect OVI to the center tap of a resistor-divider from VOUT to SGND. In this case, the center tap is compared against 1.276V. Add an RC delay to reduce the sensitivity of the overvoltage circuit and avoid nuisance tripping of the converter (Figure 9). Disable the overvoltage function by connecting OVI to SGND. PGOOD DIFF 0.9 x VREF VCM MAX5060 Figure 8. PGOOD Generator RA OVI MAX5060 DIFF RIN EAN RF EAOUT Figure 9. Overvoltage Protection Input Delay ______________________________________________________________________________________ 21 MAX5060/MAX5061 Protection The MAX5060 includes a power-good generator (PGOOD) for undervoltage protection (UVP), and a reverse current-limit protection; the MAX5060/MAX5061 include a hiccup current-limit protection to prevent damage to the powered electronic circuits. Additionally, the MAX5060 includes output overvoltage protection (OVP). MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Parallel Operation To drive multiple converters out-of-phase, use a delay circuit to set 90° of phase shift (4 paralleled converters), or 60° of phase shift (6 converters in parallel). Designate one converter as master and the remaining converters as slaves. Connect the master and slave controllers in a daisy-chain configuration as shown in Figure 11. Choose the appropriate phase shift for minimum ripple currents at the input and output capacitors. The master controller senses the output differential voltage through SENSE+ and SENSE- and generates the DIFF voltage. Disable the voltage sensing of the slaved controllers by leaving DIFF unconnected (floating). Figure 11 shows a typical application circuit using four MAX5060s. This circuit provides two phases at a 12V input voltage and a 0.6V to 5V output voltage range. For applications requiring large output current, parallel two or more MAX5060s (multiphase operation) to increase the available output current. The paralleled converters operate at the same switching frequency but different phases keep the input capacitor ripple RMS currents to a minimum. The MAX5060 provides the clock output (CLKOUT), which is 180° out-of-phase with respect to DH. For the MAX5061, the out-of-phase clock can be easily generated using a simple inverter and driving it from the LX node. Use CLKOUT to drive the second DC-DC converter to double the effective switching frequency and reduce the input capacitor ripple current (see Figure 10). SENSE- SENSE+ CSN CSP VIN VIN IN MAX5060 DIFF DH LX EAN EAOUT DL PGND SGND CLKOUT RT/SYNC RT/SYNC CSN CSP VIN MAX5060 IN DIFF DH VOUT LX EAN EAOUT DL LOAD PGND SGND Figure 10. Parallel Configuration of MAX5060 22 ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers SENSE+ 90° PHASE DELAY CIRCUIT CSN CSN RT/SYNC CSP CSP VIN VIN IN DIFF MAX5060/MAX5061 SENSE- MAX5060 VIN DH IN MAX5060 DIFF LX EAN DH LX EAN EAOUT DL PGND SGND CLKOUT DL EAOUT RT/SYNC PGND SGND CSN RT/SYNC CSP VIN IN MAX5060 DIFF DH LX EAN EAOUT DL PGND SGND CLKOUT VOUT LOAD 90° PHASE DELAY CIRCUIT CSN RT/SYNC CSP VIN IN MAX5060 DIFF DH LX EAN DL EAOUT PGND SGND Figure 11. Parallel Configuration of Multiple MAX5060s ______________________________________________________________________________________ 23 MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Applications Information Inductor Selection The switching frequency, peak inductor current, and allowable ripple at the output determine the value and size of the inductor. Selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficiency. The charge/discharge cycle of the gate and drain capacitances in the switching MOSFETs create switching losses. The situation worsens at higher input voltages, since switching losses are proportional to the square of the input voltage. The MAX5060 can operate up to 1.5MHz, however for VIN > +12V, use lower switching frequencies to limit the switching losses. Use the following equation to determine the minimum inductance value: LMIN = (VINMAX − VOUT ) × VOUT VINMAX × fSW × ∆IL Choose ∆IL equal to approximately 40% of the output current. Since ∆IL affects the output-ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors. Higher values reduce the output ripple, but at the cost of degraded transient response. Lower values have higher output ripple but better transient response. Also, lower inductor values correspond to smaller magnetics. Choose inductors from the standard high-current, surfacemount inductor series available from various manufacturers. Particular applications may require custommade inductors. Use high-frequency core material for custom inductors. High ∆IL causes large peak-to-peak flux excursion, which increases the core losses at higher frequencies. The high-frequency operation coupled with high ∆IL reduces the required minimum inductance and even makes the use of planar inductors possible. The advantages of using planar magnetics include low-profile design, excellent current-sharing between modules due to the tight control of parasitics, and low cost. For example, calculate the minimum inductance at VIN(MAX) = 13.2V, VOUT = 1.8V, ∆IL = 8A, and fSW = 330kHz: LMIN = 24 (13.2 − 1.8) × 1.8 13.2 × 330k × 8 = 0.6µH The average-current-mode control feature of the MAX5060/MAX5061 limits the maximum peak inductor current and prevents the inductor from saturating. Choose an inductor with a saturating current greater than the worst-case peak inductor current. The hiccup current-limit circuit is masked during startup to avoid unintentional hiccup when large output capacitors are used. Use the following equation to determine the worst-case inductor current: LLPEAK = VCL ∆IL + RS 2 where RS is the sense resistor and VCL = 0.0282V. Switching MOSFETs When choosing a MOSFET for voltage regulators, consider the total gate charge, RDS(ON), power dissipation, and package thermal impedance. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average current from the MAX5060/MAX5061 gatedrive output is proportional to the total capacitance it drives at DH and DL. The power dissipated in the MAX5060/MAX5061 is proportional to the input voltage and the average drive current. See the IN, VCC, and V DD section to determine the maximum total gate charge allowed from the combined driver outputs. The gate charge and drain capacitance (CV2) loss, the cross-conduction loss in the upper MOSFET due to finite rise/fall time, and the I2R loss due to RMS current in the MOSFET RDS(ON) account for the total losses in the MOSFET. Estimate the power loss (PDMOS_) caused by the high-side and low-side MOSFETs using the following equations: PDMOS −HI = (QG × VDD × fSW ) + ⎛ VIN × IOUT × (tR + tF ) × fSW ⎞ 2 ⎜ ⎟ + 1.4RDS(ON) × I RMS −HI 4 ⎝ ⎠ ( ) where QG, RDS(ON), tR, and tF are the upper-switching MOSFET’s total gate charge, on-resistance at +25°C, rise time, and fall time, respectively. ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers (I DC + I PK + I 2 2 ) DC × IPK × D 3 ESRIN = where D = VOUT/VIN, IDC = (IOUT - ∆IL/2) and IPK = (IOUT + ∆IL/2). PDMOS −LO = (QG × VDD × fSW ) + 2 ⎛2 × C ⎞ 2 OSS × VIN × fSW + 1.4R ⎜ ⎟ DS(ON) × I RMS −LO 3 ⎠ ⎝ ( IRMS −LO = (I DC + I PK + I 2 2 ) DC × IPK × ) (1 − D) 3 where COSS is the MOSFET drain-to-source capacitance. For example, from the typical specifications in the Applications Information section with VOUT = 1.8V, the high-side and low-side MOSFET RMS currents are 7.8A and 18.5A, respectively for 20A. Ensure that the thermal impedance of the MOSFET package keeps the junction temperature at least +25°C below the absolute maximum rating. Use the following equation to calculate maximum junction temperature: TJ = (PDMOS x θJA) + TA where θJA and TA are the junction-to-ambient thermal impedance and ambient temperature, respectively. Input Capacitors The discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple reflected back to the source dictate the capacitance requirement. Increasing switching frequency or paralleling multiple outof-phase converters lowers the peak-to-average current ratio, yielding a lower input capacitance requirement for the same load current. The input ripple is comprised of ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high-ripple-current capability at the input. Assume the contributions from the ESR and capacitor discharge are equal to 30% and 70%, respectively. Calculate the input capacitance and ESR required for a specified ripple using the following equation: CIN = (∆VESR ) ∆IL ⎞ ⎛ ⎜ IOUT + ⎟ ⎝ 2 ⎠ IOUT × D(1− D) ∆VQ × fSW where IOUT is the output current of the converter. For example, at VOUT = 1.8V, the ESR and input capacitance are calculated for the input peak-to-peak ripple of 100mV or less yielding an ESR and capacitance value of 1.25mΩ and 110µF. Output Capacitors The worst-case peak-to-peak and capacitor RMS ripple current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage during step loads determine the capacitance and the ESR requirements for the output capacitors. In buck converter design, the output-current waveform is continuous and this reduces peak-to-peak ripple current in the output capacitor equal to the inductor ripple current. Calculate the capacitance, the ESR of the output capacitor, and the RMS ripple current rating of the output capacitor based on the following equations. ∆VOESR ∆IL ∆IL COUT = 8 × ∆VOQ × fSW ESROUT = where ∆VOESR and ∆VOQ are the output-ripple contributions due to ESR and the discharge of output capacitor, respectively. In the dynamic load environment, the allowable deviation of output voltage during the fast transient load dictates the output capacitance and ESR. The output capacitors supply the load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closed-loop bandwidth of the converter. The resistive drop across the capacitor ESR and capacitor discharge causes a voltage drop during a step load. Use a combination of SP polymer and ceramic capacitors for better transient load and ripple/noise performance. ______________________________________________________________________________________ 25 MAX5060/MAX5061 IRMS−HI = MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Keep the maximum output voltage deviation less than or equal to the adaptive voltage-positioning window (∆VOUT). Assume 50% contribution each from the output capacitance discharge and the ESR drop. Use the following equations to calculate the required ESR and capacitance value: ∆VESR ISTEP ISTEP × tRESPONSE COUT = ∆VQ ESROUT = 100% of the average current-limit value. The average current-limit architecture accurately limits the average output current to its current-limit threshold. If the hiccup current limit is programmed to be equal or above the average current-limit value, the output current will not reach the point where the hiccup current limit can trigger. Program the hiccup current limit at least 5% below the average current limit to ensure that the hiccup current-limit circuit triggers during overload. See the Hiccup Current Limit vs. R EXT graph in the Typical Operating Characteristics. Reverse Current Limit (MAX5060) where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth. The MAX5060 limits the reverse current in case VBUS is higher than the preset output voltage. Calculate the maximum reverse current based on VCLR, the reversecurrent-limit threshold and the current-sense resistor. Current Limit In addition to the average current limit, the MAX5060/MAX5061 also have hiccup current limit. The hiccup current limit is set to 10% below the average current limit to ensure that the circuit goes in hiccup mode during continuous output short circuit. Connecting a resistor from LIM to ground increases the hiccup current limit, while shorting LIM to ground disables the hiccup current-limit circuit. Average Current Limit The average-current-mode control technique of the MAX5060/MAX5061 accurately limits the maximum output current. The MAX5060/MAX5061 sense the voltage across the sense resistor and limit the peak inductor current (IL-PK) accordingly. The ON cycle terminates when the current-sense voltage reaches 25.5mV (min). Use the following equation to calculate the maximum current-sense resistor value: RS = 0.0255 IOUT PDR = 0.75 × 10 −3 RS IREVERSE = VCLR RS where IREVERSE is the total reverse current sink into the converter and VCLR = 2.3mV (typ). Compensation The main control loop consists of an inner current loop and an outer voltage loop. The MAX5060/MAX5061 use an average current-mode control scheme to regulate the output voltage (Figure 5). IPHASE is the inner average current loop. The VEA output provides the controlling voltage for this current source. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system. A resistive feedback network around the VEA provides the best possible response, since there are no capacitors to charge and discharge during large-signal excursions. RF and RIN determine the VEA gain. Use the following equation to calculate the value of RF: IOUT × RIN GC × ∆VOUT 0.0289 GC = RS RF = where PDR is the power dissipation in the sense resistors. Select a 5% lower value of RS to compensate for any parasitics associated with the PC board. Also, select a non-inductive resistor with the appropriate power rating. where GC is the current-loop transconductance and RS is the value of the sense resistor. Hiccup Current Limit The hiccup current-limit value is always 10% lower than the average current-limit threshold, when LIM is left unconnected. Connect a resistor from LIM to SGND to increase the hiccup current-limit value from 90% to When designing the current-control loop ensure that the inductor downslope (when it becomes an upslope at the CEA output) does not exceed the ramp slope. This is a necessary condition to avoid sub-harmonic oscillations similar to those in peak current-mode control with insufficient slope compensation. 26 ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers RCF ≤ fSW × L × 102 VOUT × RS CCF provides a low-frequency pole while RCF provides a midband zero. Place a zero (fZ) to obtain a phase bump at the crossover frequency. Place a high-frequency pole (f P ) at least a decade away from the crossover frequency to reduce the influence of the switching noise and achieve maximum phase margin. Use the following equations to calculate CCF and CCFF: 1 2 × π × fZ × RCF 1 CCFF = 2 × π × fP × RCF CCF = Power Dissipation The TQFN-28 and TSSOP-16 are thermally enhanced packages and can dissipate about 2.7W and 1.7W, respectively. The high-power packages make the highfrequency, high-current buck converter possible to operate from a 12V or 24V bus. Calculate power dissipation in the MAX5060/MAX5061 as a product of the input voltage and the total VCC regulator output current (ICC). ICC includes quiescent current (IQ) and gatedrive current (IDD): PD = VIN x ICC ICC = IQ + [fSW x (QG1 + QG2)] where QG1 and QG2 are the total gate charge of the low-side and high-side external MOSFETs at VGATE = 5V, I Q is estimated from the Supply Current (I Q ) vs. Frequency graph in the Typical Operating Characteristics, and fSW is the switching frequency of the converter. Use the following equation to calculate the maximum power dissipation (PDMAX) in the chip at a given ambient temperature (TA) : MAX5060: PDMAX = 34.5 x (150 - TA)..............mW PC Board Layout Use the following guidelines to layout the switching voltage regulator. 1) Place the IN, V CC , and V DD bypass capacitors close to the MAX5060/MAX5061. 2) Minimize the area and length of the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal. 3) Keep short the current loop formed by the lower switching MOSFET, inductor, and output capacitor. 4) Place the Schottky diodes close to the lower MOSFETs and on the same side of the PC board. 5) Keep the SGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 6) Run the current-sense lines CSP and CSN very close to each other to minimize the loop area. Similarly, run the remote voltage sense lines SENSE+ and SENSE- close to each other. Do not cross these critical signal lines through power circuitry. Sense the current right at the pads of the current-sense resistors. 7) Avoid long traces between the VDD (MAX5060)/VCC (MAX5061) bypass capacitors, driver output of the MAX5060/MAX5061, MOSFET gates, and PGND. Minimize the loop formed by the V CC bypass capacitors, bootstrap diode, bootstrap capacitor, MAX5060/MAX5061, and upper MOSFET gate. 8) Place the bank of output capacitors close to the load. 9) Distribute the power components evenly across the board for proper heat dissipation. 10) Provide enough copper area at and around the switching MOSFETs, inductor, and sense resistors to aid in thermal dissipation. 11) Use 4oz copper to keep the trace inductance and resistance to a minimum. Thin copper PC boards can compromise efficiency since high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance. MAX5061: PDMAX = 21.3 x (150 - TA)..............mW ______________________________________________________________________________________ 27 MAX5060/MAX5061 Use the following equation to calculate the resistor RCF: 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers MAX5060/MAX5061 Pin Configurations SGND CSP CSN DIFF EAN EAOUT CLP OVI TOP VIEW 21 20 19 18 17 16 15 22 14 LIM SENSE- 23 13 V_IOUT SENSE+ 24 12 RT/SYNC SGND 25 11 EN IN 26 10 PGOOD VCC 27 9 CLKOUT EXPOSED PAD 28 1 2 3 4 5 6 7 N.C. DL BST LX DH N.C. 8 PGND VDD MAX5060 SGND IN 1 16 SGND VCC 2 15 CSP PGND 3 14 CSN DL 4 MAX5061 11 CLP LX 6 10 LIM DH 7 N.C. 8 13 EAN 12 EAOUT BST 5 EXPOSED PAD 9 RT/SYNC/EN TSSOP THIN QFN Chip Information TRANSISTOR COUNT: 5654 PROCESS: BiCMOS 28 ______________________________________________________________________________________ 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers QFN THIN.EPS D2 D MARKING b CL 0.10 M C A B D2/2 D/2 k L AAAAA E/2 E2/2 CL (NE-1) X e E DETAIL A PIN # 1 I.D. e/2 E2 PIN # 1 I.D. 0.35x45° e (ND-1) X e DETAIL B e L1 L CL CL L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 21-0140 I 1 2 ______________________________________________________________________________________ 29 MAX5060/MAX5061 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX5060/MAX5061 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) COMMON DIMENSIONS EXPOSED PAD VARIATIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0.02 0.05 0 0.02 0.05 0 0 0.02 0.05 e 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.80 BSC. k L 0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 N ND NE JEDEC - 16 4 4 WHHB - 20 5 5 WHHC - 28 7 7 WHHD-1 - 32 8 8 WHHD-2 0.30 0.40 0.50 40 10 10 ----- NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. PKG. CODES E2 exceptions MIN. NOM. MAX. ±0.15 T1655-2 3.00 T1655-3 3.00 T1655N-1 3.00 T2055-3 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. L D2 MIN. NOM. MAX. 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20 3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30 3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 .20 .20 3.20 3.20 3.40 ** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** ** DOWN BONDS ALLOWED YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05. -DRAWING NOT TO SCALE- 30 PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm 21-0140 ______________________________________________________________________________________ I 2 2 0.6V to 5.5V Output, Parallelable, Average-Current-Mode DC-DC Controllers TSSOP 4.4mm BODY.EPS XX XX PACKAGE OUTLINE, TSSOP, 4.40 MM BODY, EXPOSED PAD 21-0108 E 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX5060/MAX5061 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)