19-3035; Rev 1; 11/03 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Applications Features ♦ +4.75V to +5.5V or +8V to +28V Input Voltage Range ♦ Adjustable VOUT +0.6V to +3.3V (MAX5065) +0.8V to +3.3V (MAX5067) ♦ Up to 60A Output Current ♦ Internal Voltage Regulator for a +12V or +24V Power Bus ♦ Programmable Adaptive Output Voltage Positioning ♦ True Differential Remote Output Sensing ♦ Out-of-Phase Controllers Reduce Input Capacitance Requirement and Distribute Power Dissipation ♦ Average-Current-Mode Control Superior Current Sharing Between Individual Phases and Paralleled Modules Accurate Current Limit Eliminates MOSFET and Inductor Derating ♦ Limits Reverse-Current Sinking in Paralleled Modules ♦ Integrated 4A Gate Drivers ♦ Selectable Fixed Frequency 250kHz or 500kHz Per Phase (Up to 1MHz for Two Phases) ♦ External Frequency Synchronization from 125kHz to 600kHz ♦ Internal PLL with Clock Output for Paralleling Multiple DC-DC Converters ♦ Thermal Protection ♦ 28-Pin SSOP Package (MAX5065) ♦ 44-Pin Thin QFN Package (MAX5067) Servers and Workstations Point-of-Load High-Current/High-Density Telecom DC-DC Regulators Ordering Information TEMP RANGE PIN-PACKAGE Networking Systems MAX5065EAI PART -40°C to +85°C 28 SSOP Large-Memory Arrays MAX5067ETH -40°C to +85°C 44 Thin QFN RAID Systems High-End Desktop Computers Selector Guide and Pin Configurations appear at end of data sheet. ________________________________________________________________Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5065/MAX5067 General Description The MAX5065/MAX5067 dual-phase, PWM controllers provide high-output-current capability in a compact package with a minimum number of external components. The MAX5065/MAX5067 utilize a dual-phase, average-current-mode control that enables optimal use of low RDS(ON) MOSFETs, eliminating the need for external heatsinks even when delivering high output currents. Differential sensing enables accurate control of the output voltage, while adaptive voltage positioning provides optimum transient response. An internal regulator enables operation with input voltage ranges of +4.75V to +5.5V or +8V to +28V. The high switching frequency, up to 500kHz per phase, and dual-phase operation allow the use of low-output inductor values and input capacitor values. This accommodates the use of PC boardembedded planar magnetics achieving superior reliability, current sharing, thermal management, compact size, and low system cost. The MAX5065/MAX5067 also feature a clock input (CLKIN) for synchronization to an external clock, and a clock output (CLKOUT) with programmable phase delay (relative to CLKIN) for paralleling multiple phases. The MAX5065/MAX5067 also limit the reverse current if the bus voltage becomes higher than the regulated output voltage. These devices are specifically designed to limit current sinking when multiple power-supply modules are paralleled. The MAX5065 offers an adjustable +0.6V to +3.3V output voltage. The MAX5067 output voltage is adjustable from +0.8V to +3.3V and features an overvoltage protection and a power-good output signal. The MAX5065/MAX5067 operate over the extended temperature range (-40°C to +85°C). The MAX5065 is available in a 28-pin SSOP package. The MAX5067 is available in a 44-pin thin QFN package. Refer to the MAX5037A data sheet for a VRM 9.0/VRM 9.1-compatible, VID-controlled output voltage controller in a 44-pin QFN package. MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.5mW/°C above +70°C) ............762mW 44-Pin Thin QFN (derate 27.0mW/°C above+70°C) ...2162mW Operating Temperature Range ...........................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C IN to SGND.............................................................-0.3V to +30V BST_ to SGND ........................................................-0.3V to +35V DH_ to LX_ .................................-0.3V to [(VBST_ - VLX_) + 0.3V] DL_ to PGND ..............................................-0.3V to (VCC + 0.3V) BST_ to LX_ ..............................................................-0.3V to +6V VCC to SGND............................................................-0.3V to +6V VCC, VDD to PGND ...................................................-0.3V to +6V SGND to PGND .....................................................-0.3V to +0.3V All Other Pins to SGND...............................-0.3V to (VCC + 0.3V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SYSTEM SPECIFICATIONS 8 28 4.75 5.50 Input Voltage Range VIN Quiescent Supply Current IQ EN = VCC or SGND 4 Efficiency η ILOAD = 52A (26A per phase) 90 Short IN and VCC together for +5V input operation 10 V mA % OUTPUT VOLTAGE No load MAX5065 No load, VCC = +4.75V to +5.5V or VIN = +8V to +28V SENSE+ to SENSE- Accuracy (Note 4) No load MAX5067 No load, VCC = +4.75V to +5.5V or VIN = +8V to +28V 0.5952 0.6 0.6048 0.594 0.6 0.6064 0.7936 0.8 0.8064 0.792 0.8 0.808 4.0 4.15 4.5 V STARTUP/INTERNAL REGULATOR VCC Undervoltage Lockout UVLO VCC rising VCC Undervoltage Lockout Hysteresis 200 VCC Output Accuracy VIN = +8V to +28V, ISOURCE = 0 to 80mA 4.85 V mV 5.1 5.30 V 1 3 Ω MOSFET DRIVERS Output Driver Impedance RON Output Driver Source/Sink Current IDH_, IDL_ Nonoverlap Time tNO Low or high output CDH_/DL_ = 5nF 4 A 60 ns OSCILLATOR AND PLL Switching Frequency fSW PLL Lock Range fPLL PLL Locking Time tPLL 2 CLKIN = SGND 238 250 262 CLKIN = VCC 475 500 525 125 600 200 _______________________________________________________________________________________ kHz kHz µs Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers (VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER CLKOUT Phase Shift (At fSW = 125kHz) SYMBOL φCLKOUT MIN TYP MAX PHASE = VCC CONDITIONS 115 120 125 PHASE = unconnected 85 90 95 PHASE = SGND 55 60 65 ICLKIN 3 5 7 CLKIN High Threshold VCLKINH 2.4 CLKIN Low Threshold VCLKINL CLKIN Input Pulldown Current UNITS degrees µA V 0.8 V CLKIN High Pulse Width tCLKIN 200 ns PHASE High Threshold VPHASEH 4 V PHASE Low Threshold VPHASEL PHASE Input Bias Current IPHASEBIAS -50 CLKOUT Output Low Level VCLKOUTL CLKOUT Output High Level VCLKOUTH ISOURCE = 2mA (Note 2) ISINK = 2mA (Note 2) 1 V +50 µA 100 mV 4.5 V CURRENT LIMIT Average Current-Limit Threshold VCL CSP_ to CSN_ 45 Reverse Current-Limit Threshold VCLR CSP_ to CSN_ -3.9 Cycle-by-Cycle Current Limit VCLPK CSP_ to CSN_ (Note 3) Cycle-by-Cycle Overload Response Time tR 90 VCSP_ to VCSN_ = +150mV 48 112 51 mV -0.2 mV 130 mV 260 ns CURRENT-SENSE AMPLIFIER CSP_ to CSN_ Input Resistance Common-Mode Range Input Offset Voltage RCS_ 4 VCMR(CS) -0.3 VOS(CS) -1 kΩ +3.6 +1 V mV Amplifier Gain AV(CS) 18 V/V 3dB Bandwidth f3dB 4 MHz CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER) Transconductance gmca Open-Loop Gain AVOL(CE) No load 550 µS 50 dB DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF) Common-Mode Voltage Range VCMR(DIFF) DIFF Output Voltage VCM Input Offset Voltage -0.3 VSENSE+ = VSENSE- = 0 VOS(DIFF) -1 Amplifier Gain AV(DIFF) 0.997 3dB Bandwidth f3dB Minimum Output Current Drive SENSE+ to SENSE- Input Resistance +1.0 0.6 CDIFF = 20pF 1 3 IOUT(DIFF) 1.0 RVS_ 50 V V +1 mV 1.003 V/V MHz mA 100 kΩ _______________________________________________________________________________________ 3 MAX5065/MAX5067 ELECTRICAL CHARACTERISTICS (continued) MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers ELECTRICAL CHARACTERISTICS (continued) (VCC = +5V, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical specifications are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VOLTAGE-ERROR AMPLIFIER (EAOUT) Open-Loop Gain AVOL(EA) Unity-Gain Bandwidth fUGEA EAN Input Bias Current IB(EA) Error-Amplifier Output Clamping Voltage 70 dB 3 VEAN = +2.0V VCLAMP(EA) With respect to VCM MHz -100 +100 nA 810 918 mV POWER-GOOD, PHASE FAILURE DETECTION, OVERVOLTAGE PROTECTION, AND THERMAL SHUTDOWN VOV PGOOD goes low when VOUT is outside this window VUV PGOOD goes low when VOUT is outside this window +6 +8 +10 %VOUT PGOOD Trip Level (MAX5067) PGOOD Output Low Level (MAX5067) VPGLO IPG PGOOD = VCC Phase Failure Trip Threshold (MAX5067) VPH PGOOD goes low when CLP_ is higher than VPH OVPTH OVPIN Input Resistance (MAX5067) ROVPIN -10 ISINK = 4mA PGOOD Output Leakage Current (MAX5067) OVPIN Trip Threshold (MAX5067) -12.5 With respect to SGND -8.5 0.2 V 1 µA 2 V 0.792 0.8 0.808 V 190 280 370 kΩ THERMAL SHUTDOWN Thermal Shutdown TSHDN Thermal-Shutdown Hysteresis 150 °C 8 °C EN INPUT EN Input Low Voltage VENL EN Input High Voltage VENH 3 IEN 4.5 EN Pullup Current Note 1: Note 2: Note 3: Note 4: 4 1 V V 5 Specifications from -40°C to 0°C are guaranteed by characterization but not production tested. Guaranteed by design. Not production tested. See Peak-Current Comparator section. Does not include an error due to finite error amplifier gain. See the Voltage-Error Amplifier section. _______________________________________________________________________________________ 5.5 µA Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers f = 500kHz 60 VIN = +5V VOUT = +1.8V 60 VIN = +5V 50 40 30 30 20 VOUT = +1.8V fSW = 250kHz VOUT = 1V fSW = 250kHz 10 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A) OUTPUT CURRENT (A) EFFICIENCY vs. OUTPUT CURRENT EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE EFFICIENCY vs. OUTPUT CURRENT AND OUTPUT VOLTAGE 90 60 60 50 40 30 VOUT = +1.5V 80 VOUT = +1.8V 30 30 VOUT = +1V 20 VIN = +12V fSW = 250kHz VIN = +12V fSW = 500kHz 10 0 0 0 50 40 10 VOUT = +1.8V 60 40 20 VIN = +24V VOUT = +1.8V fSW = 125kHz VOUT = +1.5V 70 VOUT = +1V 50 90 η (%) 80 100 MAX5065/67 toc05 MAX5065/67 toc04 100 MAX5065/67 toc06 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A) 70 0 4 8 12 16 20 24 28 32 36 40 44 48 52 0 4 8 12 16 20 24 28 32 36 40 44 48 52 0 4 8 12 16 20 24 28 32 36 40 44 48 52 IOUT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A) SUPPLY CURRENT vs. FREQUENCY AND INPUT VOLTAGE SUPPLY CURRENT vs. TEMPERATURE AND FREQUENCY SUPPLY CURRENT vs. LOAD CAPACITANCE PER DRIVER VIN = +24V 100 90 80 100 250kHz 90 80 70 70 9.0 8.5 VIN = +12V 8.0 7.5 60 ICC (mA) ICC (mA) 10.0 9.5 125kHz 50 EXTERNALCLOCK NO DRIVER LOAD 100 150 200 250 300 350 400 450 500 550 600 FREQUENCY (kHz) 10 0 50 30 30 VIN = +5V 60 40 40 20 MAX5065/67 toc09 11.5 11.0 MAX5065/67 toc07 12.0 7.0 6.5 6.0 VIN = +12V 40 70 10.5 70 0 4 8 12 16 20 24 28 32 36 40 44 48 52 η (%) η (%) 50 0 80 ICC (mA) 60 10 90 10 VIN = +5V 20 100 20 80 MAX5065/67 toc08 40 90 η (%) η (%) f = 250kHz 70 50 VIN = +12V 70 80 η (%) 90 80 100 MAX5065/67 toc02 90 100 MAX5065/67 toc01 100 EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE EFFICIENCY vs. OUTPUT CURRENT AND INPUT VOLTAGE MAX5065/67 toc03 EFFICIENCY vs. OUTPUT CURRENT AND INTERNAL OSCILLATOR FREQUENCY 20 VIN = +12V CDL_ = 22nF CDH_ = 8.2nF -40 -15 VIN = +12V fSW = 250kHz 10 0 10 35 TEMPERATURE (°C) 60 85 1 3 5 7 9 11 13 15 CDRIVER (nF) _______________________________________________________________________________________ 5 MAX5065/MAX5067 Typical Operating Characteristics (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C, unless otherwise noted.) OVERVOLTAGE THRESHOLD (PGOOD) vs. INPUT VOLTAGE 53 10 MAX5065/67 toc11 54 VOUT = +3.3V 51 50 49 PHASE 2 48 PHASE 1 VOUT = +3.3V VUV (V) 52 VOV (V) (VCSP_ - VCSN_) (mV) 10 MAX5065/67 toc10 55 UNDERVOLTAGE THRESHOLD (PGOOD) vs. INPUT VOLTAGE MAX5065/67 toc12 CURRENT-SENSE THRESHOLD vs. OUTPUT VOLTAGE 1 VOUT = +0.8V 1 VOUT = +0.8V 47 46 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 4.7 1.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 VIN (V) OUTPUT VOLTAGE vs. OUTPUT CURRENT AND ERROR AMP GAIN (RF/RIN) DIFFERENTIAL AMPLIFIER BANDWIDTH DIFF OUTPUT ERROR vs. SENSE+ TO SENSE- VOLTAGE PHASE 2.5 GAIN (V/V) 1.75 1.70 GAIN 0 1.50 0.01 0 4 8 12 16 20 24 28 32 36 40 44 48 52 VCC LOAD REGULATION vs. INPUT VOLTAGE 0.1 1 0.125 0.100 0.075 -180 0.050 -225 0.025 -270 0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 10 ∆VSENSE (V) VIN = +12V 5.20 ICC = 0 5.15 VCC LINE REGULATION 5.25 MAX5065/67 toc17 VIN = +24V VCC LINE REGULATION 5.25 MAX5065/67 toc16 5.20 5.10 -45 5.20 5.15 5.10 4.95 4.90 4.85 DC LOAD 4.80 5.10 ICC = 40mA 5.05 VCC (V) VIN = +8V VCC (V) 5.05 5.00 5.00 15 30 45 60 75 90 105 120 135 150 ICC (mA) 5.05 5.00 4.95 4.95 4.90 4.90 4.85 4.85 4.80 4.80 4.75 0 VIN = +12V NO DRIVER FREQUENCY (MHz) ILOAD (A) 5.15 0.150 -135 0.5 1.55 0 -90 1.5 1.0 RF/RIN = 7.5 0.175 2.0 RF/RIN = 10 1.60 45 MAX5065/67 toc18 1.65 0.200 ERROR (%) RF/RIN = 20 3.0 90 PHASE (deg) 1.80 MAX5065/67 toc13 RF/RIN = 40 MAX5065/67 toc14 3.5 ICC = 80mA 4.75 8 5.5 MAX5065/67 toc15 VIN (V) 1.85 6 4.8 VOUT (V) 1.90 VOUT (V) 0.1 0.1 45 VCC (V) MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers 10 12 14 16 18 20 22 24 26 28 8 9 10 VIN (V) _______________________________________________________________________________________ 11 VIN (V) 12 13 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers DRIVER RISE TIME vs. DRIVER LOAD CAPACITANCE 100 90 100 90 80 70 DL_ 60 50 tR (ns) tR (ns) 80 MAX5065/67 toc21 MAX5065/67 toc20 120 110 MAX5065/67 toc19 120 110 HIGH-SIDE DRIVER (DH_) SINK AND SOURCE CURRENT DRIVER FALL TIME vs. DRIVER LOAD CAPACITANCE DH_ 40 30 20 1 6 11 16 21 26 31 DL_ 36 DH_ 1.6A/div DH_ 50 40 30 20 10 0 VIN = +12V fSW = 250kHz 10 0 70 60 VIN = +12V CDH_ = 22nF VIN = +12V fSW = 250kHz 1 CDRIVER (nF) 6 11 16 21 26 100ns/div 36 31 CDRIVER (nF) PLL LOCKING TIME 250kHz TO 350kHz AND 350kHz TO 250kHz MAX5065/67 toc23 LOW-SIDE DRIVER (DL_) SINK AND SOURCE CURRENT MAX5065/67 toc22 CLKOUT 5V/div 350kHz DL_ 1.6A/div PLLCMP 200mV/div 250kHz 0 VIN = +12V CDL_ = 22nF VIN = +12V NO LOAD 100ns/div 100µs/div PLL LOCKING TIME 250kHz TO 500kHz AND 500kHz TO 250kHz MAX5065/67 toc24 PLL LOCKING TIME 250kHz TO 150kHz AND 150kHz TO 250kHz MAX5065/67 toc25 CLKOUT 5V/div CLKOUT 5V/div 250kHz PLLCMP 200mV/div 500kHz PLLCMP 200mV/div 150kHz 0 250kHz VIN = +12V NO LOAD 0 100µs/div VIN = +12V NO LOAD 100µs/div _______________________________________________________________________________________ 7 MAX5065/MAX5067 Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C, unless otherwise noted.) MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C, unless otherwise noted.) HIGH-SIDE DRIVER (DH_) FALL TIME HIGH-SIDE DRIVER (DH_) RISE TIME MAX5065/67 toc27 MAX5065/67 toc26 DH_ 2V/div DH_ 2V/div VIN = +12V CDH_ = 22nF VIN = +12V CDH_ = 22nF 40ns/div 40ns/div LOW-SIDE DRIVER (DL_) RISE TIME LOW-SIDE DRIVER (DL_) FALL TIME MAX5065/67 toc28 MAX5065/67 toc29 DL_ 2V/div VIN = +12V CDL_ = 22nF DL_ 2V/div VIN = +12V CDL_ = 22nF 40ns/div 40ns/div OUTPUT RIPPLE INPUT STARTUP RESPONSE MAX5065/67 toc30 MAX5065/67 toc31 VPGOOD 1V/div VOUT 1V/div VOUT (AC-COUPLED) 10mV/div VIN 5V/div VIN = +12V VOUT = +1.75V IOUT = 52A VIN = +12V VOUT = +1.75V IOUT = 52A 500ns/div 8 2ms/div _______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers ENABLE STARTUP RESPONSE REVERSE CURRENT SINK vs. TEMPERATURE LOAD-TRANSIENT RESPONSE MAX5065/67 toc33 2.8 VPGOOD 1V/div VIN = +12V VOUT = +1.75V IOUT = 52A 2.7 VEXTERNAL = +3.3V IREVERSE (A) VOUT 1V/div MAX5065/67 toc34 MAX5065/67 toc32 VOUT 50mV/div VEN 2V/div 2.6 2.5 VEXTERNAL = +2V VIN = +12V VOUT = +1.75V ISTEP = 8A TO 52A tRISE = 1µs 2.4 VIN = +12V VOUT = 1.5V R1 = R2 = 1.5mΩ 2.3 1ms/div -40 40µs/div -15 10 35 60 85 TEMPERATURE (°C) REVERSE CURRENT SINK AT INPUT TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.5V) REVERSE CURRENT SINK AT INPUT TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V) MAX5065/67 toc36 MAX5065/67 toc35 REVERSE CURRENT 10A/div REVERSE CURRENT 5A/div 0A 0A R1 = R2 = 1.5mΩ R1 = R2 = 1.5mΩ 200µs/div 200µs/div REVERSE CURRENT SINK AT ENABLE TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.5V) REVERSE CURRENT SINK AT ENABLE TURN-ON (VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V) MAX5065/67 toc37 R1 = R2 = 1.5mΩ MAX5065/67 toc38 REVERSE CURRENT 5A/div REVERSE CURRENT 10A/div 0A 0A R1 = R2 = 1.5mΩ 200µs/div 200µs/div _______________________________________________________________________________________ 9 MAX5065/MAX5067 Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C, unless otherwise noted.) MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Pin Description PIN NAME FUNCTION MAX5065 MAX5067 1, 13 39, 16 CSP2, CSP1 Current-Sense Differential Amplifier Positive Inputs. Sense the inductor current. The differential voltage between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18. 2, 14 40, 17 CSN2, CSN1 Current-Sense Differential Amplifier Negative Inputs. Together with CSP_, sense the inductor current. 3 41 PHASE Phase-Shift Setting Input. Connect PHASE to VCC for 120°, leave PHASE unconnected for 90°, or connect PHASE to SGND for 60° of phase shift between the rising edge of CLKOUT and CLKIN/DH1. 4 42 PLLCMP External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see the Phase-Locked Loop section). 5, 7 43, 7 CLP2, CLP1 Current-Error Amplifier Outputs. Compensate the current loop by connecting an RC network to ground. 6 5, 20, 35 SGND Signal Ground. Ground connection for the internal control circuitry. 8 10 SENSE+ Differential Output-Voltage-Sensing Positive Input. Used to sense a remote load. The MAX5065 and MAX5067 regulate the difference between SENSE+ and SENSE- according to the factory preset reference voltage of +0.6V and +0.8V, respectively. 9 11 SENSE- Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to VOUT- or PGND at the load. 10 12 DIFF Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier. 11 13 EAN Voltage-Error Amplifier Inverting Input. Receives a signal from the output of the differential remote-sense amplifier. Referenced to SGND. 12 14 EAOUT Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error amplifier gain-setting resistors determine the amount of adaptive voltage positioning. 15 19 EN 16, 26 22, 34 BST1, BST2 Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply. Connect a 0.47µF ceramic capacitor between BST_ and LX_. 17, 25 23, 32 DH1, DH2 High-Side Gate-Driver Outputs. Drive the gate of the high-side MOSFET. 18, 24 24, 31 LX1, LX2 19, 23 25, 30 DL1, DL2 Low-Side Gate-Driver Outputs. Synchronous MOSFET gate drivers for the two phases. 20 27 VCC 21 28 IN 22 29 PGND 10 Output Enable. A logic-low shuts down the power drivers. EN has an internal 5µA pullup current. Inductor Connection. Source connection for the high-side MOSFETs. Also serve as the return terminal for the high-side driver. Internal +5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7µF and 0.1µF ceramic capacitors in parallel. Supply Voltage Connection. Connect IN to VCC for a +5V system. Connect the unregulated power source to IN through an RC lowpass filter comprised of a 2.2Ω resistor and a 0.1µF ceramic capacitor. Power Ground. Connect the VCC bypass capacitors, input capacitors, output capacitors, and low-side synchronous MOSFET source to PGND. ______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065 MAX5067 27 36 NAME CLKOUT FUNCTION Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount determined by the PHASE input. Use CLKOUT to parallel additional MAX5065/MAX5067s. 28 38 CLKIN CMOS Logic Clock Input. Drive CLKIN with a frequency range between 125kHz and 600kHz or connect to VCC or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or connect to VCC to set the internal oscillator to 500kHz. CLKIN has an internal 5µA pulldown current. — 6 OVPIN Overvoltage Protection Circuit Input. Connect OVPIN to the center of the resistive-divider between VOUT and GND. When OVPIN exceeds +0.8V with respect to SGND, OVPOUT latches DH_ low and DL_ high. Toggle EN low to high or recycle the power to reset the latch. — 8 OVPOUT Overvoltage Protection Output. Use the OVPOUT active-high, push-pull output to trigger a safety device such as an SCR. Power-Good Output. The open-drain, active-low PGOOD output goes low when the output voltage falls out of regulation or a phase failure is detected. The power-good windowcomparator thresholds are +8% and -10% of the output voltage. Forcing EN low also forces PGOOD low. — 9 PGOOD — 1, 2, 3, 4, 15, 18, 21, 33, 37, 44 N.C. No Connection. Not internally connected. — 26 VDD Supply Voltage for Low-Side and High-Side Drivers. VCC powers VDD. Connect a parallel combination of 0.1µF and 1µF ceramic capacitors to PGND and a 1Ω resistor to VCC to filter out the high peak currents of the driver from the internal circuitry. Detailed Description The MAX5065/MAX5067 average-current-mode PWM controllers drive two out-of-phase buck converter channels. Average-current-mode control improves current sharing between the channels while minimizing component derating and size. Parallel multiple MAX5065/ MAX5067 regulators to increase the output current capacity. For maximum ripple rejection at the input, set the phase shift between phases to 90° for two paralleled converters, or 60° for three paralleled converters. Paralleling the MAX5065/MAX5067s improves design flexibility in applications requiring upgrades (higher load). Dual-phase converters with an out-of-phase locking arrangement reduce the input and output capacitor ripple current, effectively multiplying the switching frequency by the number of phases. Each phase of the MAX5065/MAX5067 consists of an inner average current loop controlled by a common outer-loop voltageerror amplifier (VEA). The combined action of the two inner current loops and the outer voltage loop corrects the output voltage errors and forces the phase currents to be equal. Program the output voltage from +0.6V to +3.3V (MAX5065) and +0.8V to +3.3V (MAX5067) using a resistive-divider at SENSE+ and SENSE-. VIN, VCC, VDD The MAX5065/MAX5067 accept a wide input voltage range of +4.75V to +5.5V or +8V to +28V. All internal control circuitry operates from an internally regulated nominal voltage of +5V (VCC). For input voltages of +8V or greater, the internal VCC regulator steps the voltage down to +5V. The VCC output voltage regulates to +5V while sourcing up to 80mA. Bypass VCC to SGND with 4.7µF and 0.1µF low-ESR ceramic capacitors for highfrequency noise rejection and stable operation (Figures 1, 2, and 3). Calculate power dissipation in the MAX5065/MAX5067 as a product of the input voltage and the total VCC regulator output current (ICC). ICC includes quiescent current (IQ) and gate-drive current (IDD): (1) PD = VIN x ICC ICC = IQ + fSW x (QG1 + QG2 + QG3 + QG4) ______________________________________________________________________________________ (2) 11 MAX5065/MAX5067 Pin Description (continued) PIN Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067 Functional Diagrams EN IN +5V LDO REGULATOR UVLO POR TEMP SENSOR TO INTERNAL CIRCUITS VCC TO INTERNAL CIRCUITS CSP1 CSN1 CSP1 DRV_VCC SHDN CSN1 CLP1 DH1 CLP1 CLK SGND BST1 LX1 PHASE 1 DL1 MAX5065 GMIN PGND PHASELOCKED LOOP CLKIN RAMP1 PHASE CLKOUT PLLCMP RAMP GENERATOR DIFF SENSE- 0.6V DIFF AMP PGND SENSE+ EAOUT EAN ERROR AMP DRV_VCC SHDN CLK VREF = 0.6V + VCM PGND RAMP2 GMIN CLP2 CSN2 CSP2 12 PHASE 2 DH2 LX2 CLP2 CSN2 CSP2 ______________________________________________________________________________________ DL2 BST2 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers EN IN +5V LDO REGULATOR UVLO POR TEMP SENSOR VCC TO INTERNAL CIRCUITS VDD CSP1 CSP1 CSN1 DRV_VCC SHDN BST1 CSN1 CLP1 DH1 CLP1 CLK SGND LX1 PHASE 1 DL1 MAX5067 GMIN PGND PHASELOCKED LOOP CLKIN RAMP1 PHASE RAMP GENERATOR CLKOUT CLP1 PLLCMP DIFF DIFF CLP2 SENSE- +0.6V PGOOD POWERGOOD GENERATOR N PGND VREF DIFF AMP SENSE+ EAOUT 0.8V EAN OVPOUT OVP COMP ERROR AMP DRV_VCC SHDN CLK VREF = 0.8V + VCM PGND RAMP2 OVPIN CLP2 CSN2 CSP2 GMIN PHASE 2 DH2 LX2 CLP2 DL2 CSN2 BST2 CSP2 ______________________________________________________________________________________ 13 MAX5065/MAX5067 Functional Diagrams (continued) 14 RB RA RX C43 VCC C44 VIN Rf RIN C36 R12 EN C32 Figure 1. Typical Application Circuit, VIN = +5V ______________________________________________________________________________________ C33 R5 R6 C35 CLP2 PLLCMP CLKIN R4 C31 CLP1 EAOUT EAN DIFF OVPIN OVPOUT VCC VCC IN C42 C34 PGND SGND PHASE PGOOD CSN2 CSP2 VCC BST2 DL2 LX2 DH2 VDD VCC BST1 DL1 LX1 SENSE- SENSE+ CSN1 CSP1 DH1 C1, C2 MAX5067 IN R13 VIN = +5V Q4 Q3 VIN C39 R3 Q2 Q1 VIN D2 C13 C8 C11 C40 D1 L2 C41 L1 R11 D4 D3 C12 PGOOD C3–C7 R2 IN R1 C38 C14 C15 C16 C25 C26, C30, C37 LOAD RL RH VOUT = +0.8V TO +3.3V AT 52A MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers C44 RX VCC C43 Rf RIN C36 R12 C33 R5 R6 C35 CLP2 PLLCMP CLKIN R4 C31 CLP1 EAOUT EAN DIFF OVPIN OVPOUT EN C32 NOTE: SEE TABLE 1 FOR COMPONENT VALUES. RB RA VIN VCC C42 C34 VCC BST2 DL2 LX2 DH2 VDD VCC BST1 DL1 LX1 SENSE- SENSE+ CSN1 CSP1 DH1 PGND SGND PHASE PGOOD CSN2 CSP2 MAX5067 IN R13 C1, C2 VIN = +8V TO +28V Q4 Q3 VIN C39 R3 Q2 Q1 VIN D2 C13 C8– C11 C40 C41 D1 C12 PGOOD C3–C7 R11 L2 C38 L1 D4 D3 R2 R1 C14, C15 C16– C25 C26– C30, C37 LOAD RL RH VOUT = +1.8V AT 52A MAX5065/MAX5067 VCC Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Figure 2. Typical VRM Application Circuit, VIN = +8V to +28V ______________________________________________________________________________________ 15 MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers SENSESENSE+ 3 CSN1 PHASE CSP1 9 8 14 13 VIN 15 EN R1 VIN = +12V C3–C7 21 IN C1, C2 C39 DH1 LX1 VCC 28 DL1 17 Q1 L1 18 19 C12 Q2 CLKIN R2 D1 MAX5065 BST1 16 4 PLLCMP R4 C25 D3 +1.8V AT 60A VOUT VCC 20 C34 C32 C31 RH C26 R7 VCC 10 11 R8 RX 12 DIFF D4 VIN C8–C11 EAN EAOUT R6 7 CLP1 C16–C24, LOAD C33 RL DH2 25 Q1 L2 LX2 24 C29 C14, C15 DL2 23 R3 C13 Q2 D2 C30 5 C28 C27 BST2 26 CLP2 R5 1 6 22 SGND PGND CSP2 CSN2 2 Figure 3. MAX5065 Typical Application Circuit 16 ______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Undervoltage Lockout (UVLO)/Soft-Start The MAX5065/MAX5067 include an undervoltage lockout with hysteresis and a power-on reset circuit for converter turn-on and monotonic rise of the output voltage. The UVLO threshold is internally set between +4.0V and +4.5V with a 200mV hysteresis. Hysteresis at UVLO eliminates “chattering” during startup. Most of the internal circuitry, including the oscillator, turns on when the input voltage reaches +4V. The MAX5065/MAX5067 draw up to 4mA of current before the input voltage reaches the UVLO threshold. The compensation network at the current-error amplifiers (CLP1 and CLP2) provides an inherent soft-start of the output voltage. It includes a parallel combination of capacitors (C34, C36) and resistors (R5, R6) in series with other capacitors (C33, C35) (see Figures 1 and 2). The voltage at CLP_ limits the maximum current available to charge output capacitors. The capacitor on CLP_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus the output voltage. Internal Oscillator The internal oscillator generates the 180° out-of-phase clock signals required by the pulse-width modulation (PWM) circuits. The oscillator also generates the 2VP-P voltage ramp signals necessary for the PWM comparators. Connect CLKIN to SGND to set the internal oscillator frequency to 250kHz or connect CLKIN to VCC to set the internal oscillator to 500kHz. CLKIN is a CMOS logic clock input for the phaselocked loop (PLL). When driven externally, the internal oscillator locks to the signal at CLKIN. A rising edge at CLKIN starts the ON cycle of the PWM. Ensure that the external clock pulse width is at least 200ns. CLKOUT provides a phase-shifted output with respect to the rising edge of the signal at CLKIN. PHASE sets the amount of phase shift at CLKOUT. Connect PHASE to VCC for 120° of phase shift, leave PHASE unconnected for 90° of phase shift, or connect PHASE to SGND for 60° of phase shift with respect to CLKIN. The MAX5065/MAX5067 require compensation on PLLCMP even when operating from the internal oscillator. The device requires an active PLL to generate the proper clock signal required for PWM operation. Control Loop The MAX5065/MAX5067 use an average-current-mode control scheme to regulate the output voltage (Figure 4). The main control loop consists of an inner current loop and an outer voltage loop. The inner loop controls the output currents (IPHASE1 and IPHASE2) while the outer loop controls the output voltage. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a singlepole system. The current loop consists of a current-sense resistor (RS), a current-sense amplifier (CA_), a current-error amplifier (CEA_), an oscillator providing the carrier ramp, and a PWM comparator (CPWM_). The precision CA_ amplifies the sense voltage across RS by a factor of 18. The inverting input to the CEA_ senses the CA_ output. The CEA_ output is the difference between the voltage-error amplifier output (EAOUT) and the gainedup voltage from the CA_. The RC compensation network connected to CLP1 and CLP2 provides external frequency compensation for the respective CEA_. The start of every clock cycle enables the high-side drivers and initiates a PWM ON cycle. Comparator CPWM_ compares the output voltage from the CEA_ with a 0 to +2V ramp from the oscillator. The PWM ON cycle terminates when the ramp voltage exceeds the error voltage. The outer voltage control loop consists of the differential amplifier (DIFF AMP), reference voltage, and VEA. The unity-gain differential amplifier provides true differential remote sensing of the output voltage. The differential amplifier output connects to the inverting input (EAN) of the VEA. The noninverting input of the VEA is internally connected to an internal precision reference voltage. The MAX5067 reference voltage is set to +0.8V and the MAX5065 reference is set to +0.6V. The VEA controls the two inner current loops (Figure 4). Use a resistive feedback network to set the VEA gain as required by the adaptive voltage-positioning circuit (see the Adaptive Voltage Positioning section). Current-Sense Amplifier The differential current-sense amplifier (CA_) provides a DC gain of 18. The maximum input offset voltage of the current-sense amplifier is 1mV and the common-mode voltage range is -0.3V to +3.6V. The current-sense amplifier senses the voltage across a current-sense resistor. Peak-Current Comparator The peak-current comparator provides a path for fast cycle-by-cycle current limit during extreme fault conditions such as an output inductor malfunction (Figure 5). Note that the average current-limit threshold of 48mV still limits the output current during short-circuit conditions. To prevent inductor saturation, select an output ______________________________________________________________________________________ 17 MAX5065/MAX5067 where, Q G1, Q G2, Q G3, and Q G4 are the total gate charge of the low-side and high-side external MOSFETs, IQ is 4mA (typ), and fSW is the switching frequency of each individual phase. For applications utilizing a +5V input voltage, disable the VCC regulator by connecting IN and VCC together. up slope to the inverting input of the PWM comparator, is less than the slope of the internally generated voltage ramp (see the Compensation section). inductor with a saturation current specification greater than the average current limit (48mV). Proper inductor selection ensures that only extreme conditions trip the peak-current comparator, such as a cracked output inductor. The 112mV voltage threshold for triggering the peak-current limit is twice the full-scale average current-limit voltage threshold. The peak-current comparator has a delay of only 260ns. PWM Comparator and R-S Flip-Flop The PWM comparator (CPWM) sets the duty cycle for each cycle by comparing the output of the current-error amplifier to a 2VP-P ramp. At the start of each clock cycle, an R-S flip-flop resets and the high-side driver (DH_) turns on. The comparator sets the flip-flop as soon as the ramp voltage exceeds the CLP_ voltage, thus terminating the ON cycle (Figure 5). Current-Error Amplifier Each phase of the MAX5065/MAX5067 has a dedicated transconductance current-error amplifier (CEA_) with a typical gm of 550µS and 320µA output sink and source current capability. The current-error amplifier outputs, CLP1 and CLP2, serve as the inverting input to the PWM comparator. CLP1 and CLP2 are externally accessible to provide frequency compensation for the inner current loops (Figure 4). Compensate CEA_ so the inductor current down slope, which becomes the Differential Amplifier The differential amplifier (DIFF AMP) facilitates output voltage remote sensing at the load (Figure 4). It provides true differential output voltage sensing while rejecting the common-mode voltage errors due to highcurrent ground paths. Sensing the output voltage CCF MAX5065/ MAX5067 CLP1 CSP1 CSN1 RCF CCFF CA1 RF* VIN IPHASE1 CEA1 SENSE+ CPWM1 DIFF AMP DRIVE 1 RS RIN* VEA SENSE- VOUT VIN COUT CEA2 VREF CPWM2 DRIVE 2 IPHASE2 RS CLP2 CSP2 CA2 CSN2 MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers CCF RCF *RF AND RIN ARE EXTERNAL. CCCF Figure 4. MAX5065/MAX5067 Control Loop 18 ______________________________________________________________________________________ LOAD Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Voltage-Error Amplifier The VEA sets the gain of the voltage control loop and determines the error between the differential amplifier output and the internal reference voltage (VREF). The VEA output clamps to +0.9V relative to V CM (+0.6V), thus limiting the average maximum current from individual phases. The maximum average currentlimit threshold for each phase is equal to the maximum clamp voltage of the VEA divided by the gain (18) of the current-sense amplifier. This results in accurate settings for the average maximum current for each phase. Set the VEA gain using RF and RIN for the amount of output voltage positioning required within the rated current range as discussed in the Adaptive Voltage Positioning section (Figure 4). R R +R L ×V VOUT(NL) = 1 + IN × H REF RF RL (3) where RH and RL are the feedback resistor network (Figures 1, 2). V REF = 0.6V (MAX5065) or 0.8V (MAX5067). Some applications require VOUT equal to VOUT(NOM) at no load. To ensure that the output voltage does not exceed the nominal output voltage (VOUT(NOM)), add a resistor RX from VCC to EAN. Use the following equations to calculate the value of RX. For MAX5065: RX = [VCC − 1.2] × RF 0.6V RX = [VCC − 1.4] × RF 0.8V (4) For MAX5067: (5) Adaptive Voltage Positioning Powering new-generation processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when the output current suddenly increases. Regulating at a lower output voltage under a heavy load allows a larger upward-voltage excursion when the output current suddenly decreases. A larger allowed, voltage-step excursion reduces the required number of output capacitors DRV_VCC PEAK-CURRENT COMPARATOR 112mV CLP_ CSP_ AV = 18 Gm = 500µS CSN_ BST_ PWM COMPARATOR GMIN S Q DH_ RAMP LX_ 2 x fs (V/s) CLK R Q DL_ PGND SHDN Figure 5. Phase Circuit (Phase 1/Phase 2) ______________________________________________________________________________________ 19 MAX5065/MAX5067 directly at the load provides accurate load voltage sensing in high-current environments. The VEA provides the difference between the differential amplifier output (DIFF) and the desired output voltage. The differential amplifier has a bandwidth of 3MHz. The difference between SENSE+ and SENSE- regulates to +0.6V for the MAX5065 and regulates to +0.8V for the MAX5067. Connect SENSE+ to the center of the resistive-divider from the output to SENSE-. VOLTAGE-POSITIONING WINDOW MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers VCNTR + ∆VOUT/2 VCNTR VCNTR - ∆VOUT/2 1/2 LOAD NO LOAD FULL LOAD compensation provides a zero defined by 1 / [R4 x (C31 + C32)] and a pole defined by 1 / (R4 x C32). Use the following typical values for compensating the PLL: R4 = 7.5kΩ, C31 = 4.7nF, C32 = 470pF. If changing the PLL frequency, expect a finite locking time of approximately 200µs. The MAX5065/MAX5067 require compensation on PLLCMP even when operating from the internal oscillator. The device requires an active PLL in order to generate the proper internal PWM clocks. MOSFET Gate Drivers (DH_, DL_) LOAD (A) Figure 6. Defining the Voltage-Positioning Window or allows for the use of higher ESR capacitors. Voltage positioning may require the output to regulate away from a center value. Define the center value as the voltage where the output drops (∆VOUT/2) at one half the maximum output current (Figure 6). Set the voltage-positioning window (∆VOUT) using the resistive feedback of the VEA. Use the following equations to calculate the voltage-positioning window for the MAX5065/MAX5067: (6) I × RIN RH + RL ∆VOUT = OUT × RL 2 × GC × RF The high-side (DH_) and low-side (DL_) drivers drive the gates of external N-channel MOSFETs (Figures 1, 2, and 3). The drivers’ high-peak sink and source current capability provides ample drive for the fast rise and fall times of the switching MOSFETs. Faster rise and fall times result in reduced cross-conduction losses. For modern CPU voltage-regulating module applications where the duty cycle is less than 50%, choose highside MOSFETs (Q1 and Q3) with a moderate RDS(ON) and a very low gate charge. Choose low-side MOSFETs (Q2 and Q4) with very low R DS(ON) and moderate gate charge. The driver block also includes a logic circuit that provides an adaptive nonoverlap time to prevent shoot-through currents during transition. The typical nonoverlap time is 60ns between the high-side and low-side MOSFETs. BST_ (7) GC = 0.05 RS where RIN and RF are the input and feedback resistors of the VEA, GC is the current-loop transconductance, and RS is the current-sense resistor. Phase-Locked Loop: Operation and Compensation The PLL synchronizes the internal oscillator to the external frequency source when driving CLKIN. Connecting CLKIN to VCC or SGND forces the PWM frequency to default to the internal oscillator frequency of 500kHz or 250kHz, respectively. The PLL uses a conventional architecture consisting of a phase detector and a charge pump capable of providing 20µA of output current. Connect an external series combination capacitor (C31) and resistor (R4) and a parallel capacitor (C32) from PLLCMP to SGND to provide frequency compensation for the PLL (Figure 1). The pole-zero pair 20 The MAX5067 uses VDD to power the low- and highside MOSFET drivers. The high-side drivers derive their power through a bootstrap capacitor and VDD supplies power internally to the low-side drivers. Connect a 0.47µF low-ESR ceramic capacitor between BST_ and LX_. Bypass VCC to SGND with 4.7µF and 0.1µF lowESR ceramic capacitors in parallel. Reduce the PC board area formed by these capacitors, the rectifier diodes between V CC and the boost capacitor, the MAX5065/MAX5067, and the switching MOSFETs. Overload Conditions Average-current-mode control has the ability to limit the average current sourced by the converter during a fault condition. When a fault condition occurs, the VEA output clamps to +0.9V with respect to the common-mode voltage (VCM = +0.6V) and is compared with the output of the current-sense amplifiers (CA1 and CA2) (see Figure 4). The current-sense amplifier’s gain of 18 limits the maximum current in the inductor or sense resistor to ILIMIT = 50mV/RS. ______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Power-Good Generator (MAX5067) The PGOOD output is high if all of the following conditions are met (Figure 8): 1) The output is within 90% to 108% of the programmed output voltage. Overvoltage Protection (MAX5067) The OVP comparator compares the OVPIN input to the overvoltage threshold (Figure 7). The overvoltage threshold is typically +0.8V. A detected overvoltage event latches the comparator output forcing the power stage into the OVP state. In the OVP state, the highside MOSFETs turn off and the low-side MOSFETs latch on. Use the OVPOUT high-current output driver to turn on an external crowbar SCR. When the crowbar SCR turns on, a fuse must blow or the source current for the MAX5067 regulator must be limited to prevent further damage to the external circuitry. Connect the SCR close to the input source and after the fuse. Use an SCR large enough to handle the peak I2t energy due to the input and output capacitors discharging and the current sourced by the power-source output. Connect DIFF to OVPIN for differential output sensing and overvoltage protection. Add an RC delay to reduce the sensitivity of the overvoltage circuit and avoid nuisance tripping of the converter (Figures 1, 2). Connect a resistor-divider from the load to SGND to set the OVP output voltage. R VOVP = 1+ A × 0.8V RB (8) 2) Both phases are providing current. 3) EN is high. A window comparator compares the differential amplifier output (DIFF) against 1.08 times the set output voltage for overvoltage and 0.90 times the set output voltage for undervoltage monitoring. The phase-failure comparator detects a phase failure by comparing the current-erroramplifier output (CLP_) with a 2.0V reference. Use a 10kΩ pullup resistor from PGOOD to a voltage source less than or equal to VCC. An output voltage outside the comparator window or a phase-failure condition forces the open-drain output low. The open-drain MOSFET sinks 4mA of current while maintaining less than 0.2V at the PGOOD output. DIFF 8% OF VREF PGOOD VREF RA 10% OF VREF VOUT OVPIN RB CLP1 MAX5067 DIFF +2.0V RIN EAN RF EAOUT CLP2 PHASE-FAILURE DETECTION Figure 7. OVP Input Delay Figure 8. Power-Good Generator (MAX5067) ______________________________________________________________________________________ 21 MAX5065/MAX5067 Protection The MAX5067 includes output overvoltage protection (OVP), undervoltage protection (UVP), phase failure, and overload protection to prevent damage to the powered electronic circuits. MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers CSN1 CSP1 SENSE+ VIN SENSEDH1 VCC LX1 PHASE DL1 VCC CLKIN VIN VIN MAX5065/ MAX5067 DH2 LX2 IN DL2 DIFF EAN CSP2 CSN2 EAOUT PGND SGND CLKOUT CSN1 CSP1 CLKIN VIN DH1 VCC LX1 PHASE DL1 MAX5065/ MAX5067 IN VIN DH2 DIFF LX2 LOAD DL2 VOUT = +0.6V (MAX5065) VOUT = +0.8V (MAX5067) EAN CSP2 EAOUT CSN2 PGND SGND CLKOUT CSN1 CSP1 CLKIN VIN DH1 VCC LX1 PHASE DL1 MAX5065/ MAX5067 IN VIN DH2 DIFF LX2 DL2 EAN EAOUT CSP2 CSN2 PGND SGND CLKOUT TO OTHER MAX5065/MAX5067s Figure 9. Parallel Configuration of Multiple MAX5065/MAX5067s 22 ______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067 VIN = +12V VIN C1, C2 2 x 47µF VCC C31 R13 2.2Ω C32 C43 R12 C42 0.1µF R4 VIN C3–C7 5 x 22µF OVPOUT PLLCMP CLKIN IN SENSE- SENSE+ CSN1 CSP1 Q1 DH1 L1 0.6µH R1 1.35mΩ LX1 DL1 C12 0.47µF Q2 D1 D3 BST1 VCC VCC R3 C41 0.1µF C38 4.7µF C39 1µF C40 1µF D4 EN VDD OVPIN R7 VIN MAX5067 (MASTER) DIFF 4 x 22µF C8–C11 EAN DH2 R8 Q3 L2 0.6µH EAOUT R2 1.35mΩ LX2 DL2 C13 0.47µF Q4 D2 CLP1 CLP2 PGND SGND CLKOUT PHASE PGOOD CSN2 CSP2 BST2 R11 R5 R6 C36 C34 PGOOD VCC C33 C35 C16–C25, C57–C60 2 x 270µF C71 R17 VIN C61 0.1µF EN PLLCMP IN C26–C30, C37 6 x 10µF LOAD C14, C15, C44, C45 2 x 100µF R24 2.2Ω C70 RA RL RB VOUT = +0.8V TO +3.3V AT 104A C46–C50 5 x 22µF CLKIN RH SENSE- SENSE+ CSN1 CSP1 L3 0.6µH Q5 DH1 R14 1.35mΩ LX1 DL1 C55 0.47µF Q6 D5 D7 BST1 VCC R16 OVPOUT VDD OVPIN MAX5067 (SLAVE) C65 4.7µF C64 0.1µF C62 1µF C63 0.1µF D8 R20 VIN DIFF C51–C54 4 x 22µF EAN DH2 R21 L4 0.6µH Q7 EAOUT R15 1.35mΩ LX2 DL2 C56 0.47µF Q8 D6 CLP1 CLP2 R19 R18 C66 PGND C69 C67 SGND PHASE PGOOD CSN2 CSP2 BST2 VCC C68 Figure 10. Four-Phase Parallel Application Circuit (VIN = +12V, VOUT = +0.8V to +3.3V at 104A) ______________________________________________________________________________________ 23 MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Phase-Failure Detector (MAX5067) Output current contributions from the two phases are within ±10% of each other. Proper current sharing reduces the necessity to overcompensate the external components. However, an undetected failure of one phase driver causes the other phase driver to run continuously as it tries to provide the entire current requirement to the load. Eventually, the stressed operational phase driver fails. During normal operating conditions, the voltage level on CLP_ is within the peak-to-peak voltage levels of the PWM ramp. If one of the phases fails, the control loop raises the CLP_ voltage above its operating range. To determine a phase failure, the phase-failure detection circuit (Figure 8) monitors the output of the current amplifiers (CLP1 and CLP2) and compares them to a 2.0V reference. If the voltage levels on CLP1 or CLP2 are above the reference level for more than 1250 clock cycles, the phase failure circuit forces PGOOD low. Parallel Operation For applications requiring large output current, parallel up to three MAX5065/MAX5067s (six phases) to triple the available output current (see Figures 9 and 10). The paralleled converters operate at the same switching frequency but different phases keep the capacitor ripple RMS currents to a minimum. Three parallel MAX5065/ MAX5067 converters deliver up to 180A of output current. To set the phase shift of the on-board PLL, leave PHASE unconnected for 90° of phase shift (2 paralleled converters), or connect PHASE to SGND for 60° of phase shift (3 converters in parallel). Designate one converter as master and the remaining converters as slaves. Connect the master and slave controllers in a daisychain configuration as shown in Figure 9. Connect CLKOUT from the master controller to CLKIN of the first slaved controller, and CLKOUT from the first slaved controller to CLKIN of the second slaved controller. Choose the appropriate phase shift for minimum ripple currents at the input and output capacitors. The master controller senses the output differential voltage through SENSE+ and SENSE- and generates the DIFF voltage. Disable the voltage sensing of the slaved controllers by leaving DIFF unconnected (floating). Figure 10 shows a detailed typical parallel application circuit using two MAX5067s. This circuit provides four phases at an input voltage of +12V and an output voltage range of +0.6V to +3.3V (MAX5065) and +0.8V to +3.3V (MAX5067) at 104A. Applications Information Each MAX5065/MAX5067 circuit drives two 180° out-ofphase channels. Parallel two or three MAX5065/ MAX5067 circuits to achieve four- or six-phase opera24 tion, respectively. Figure 1 shows the typical application circuit for a two-phase operation. The design criteria for a two-phase converter includes frequency selection, inductor value, input/output capacitance, switching MOSFETs, sense resistors, and the compensation network. Follow the same procedure for the four- and sixphase converter design, except for the input and output capacitance. The input and output capacitance requirements vary depending on the operating duty cycle. The examples discussed in this data sheet pertain to a typical application with the following specifications: VIN = +12V VOUT = +1.8V IOUT(MAX) = 52A fSW = 250kHz Peak-to-Peak Inductor Current (∆IL) = 10A Table 1 shows a list of recommended external components (Figure 1) and Table 2 provides component supplier information. Number of Phases Selecting the number of phases for a voltage regulator depends mainly on the ratio of input-to-output voltage (operating duty cycle). Optimum output-ripple cancellation depends on the right combination of operating duty cycle and the number of phases. Use the following equation as a starting point to choose the number of phases: NPH ≈ K/D (9) where K = 1, 2, or 3 and the duty cycle is D = VOUT/VIN. Choose K to make NPH an integer number. For example, converting V IN = +12V to V OUT = +1.8V yields better ripple cancellation in the six-phase converter than in the four-phase converter. Ensure that the output load justifies the greater number of components for multiphase conversion. Generally limiting the maximum output current to 25A per phase yields the most costeffective solution. The maximum ripple cancellation occurs when NPH = K/D. Single-phase conversion requires greater size and power dissipation for external components such as the switching MOSFETs and the inductor. Multiphase conversion eliminates the heatsink by distributing the power dissipation in the external components. The multiple phases operating at given phase shifts effectively increase the switching frequency seen by the input/output capacitors, thereby reducing the input/output capacitance requirement for the same ripple performance. The lower inductance value improves the large-signal response of the converter during a transient load at the output. Consider ______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers MAX5065/MAX5067 Table 1. Component List DESIGNATION QTY DESCRIPTION C1, C2 2 47µF,16V X5R input-filter capacitors TDK C5750X5R1C476M C3–C11 9 22µF, 16V input-filter capacitors TDK C4532X5R1C226M C12, C13 2 0.47µF, 16V capacitors TDK C1608X5R1A474K C14, C15 2 100µF, 6.3V, output-filter capacitors Murata GRM44-1X5R107K6.3 C16–C25 10 270µF, 2V output-filter capacitors Panasonic EEFUE0D271R C26–C30, C37 6 10µF, 6.3V output-filter capacitors TDK C2012X5R05106M C31 1 4700pF, 16V X7R capacitor Vishay-Siliconix VJ0603Y471JXJ C32, C34, C36 3 470pF, 16V capacitors Murata GRM1885C1H471JAB01 C33, C35, C43 3 0.01µF, 50V X7R capacitors Murata GRM188R71H103KA01 C38 1 4.7µF, 16V X5R capacitor Murata GRM40-034X5R475k6.3 C39 1 0.1µF, 10V Y5V capacitor Murata GRM188F51A105 C40, C41, C42 3 0.1µF, 16V X7R capacitors Murata GRM188R71C104KA01 C44 1 100pF—OVPIN capacitor D1, D2 2 Schottky diodes ON-Semiconductor MBRS340T3 D3, D4 2 Schottky diodes ON-Semiconductor MBR0520LT1 L1, L2 2 0.6µH, 27A inductors Panasonic ETQP1H0R6BFX Q1, Q3 2 Upper-power MOSFETs Vishay-Siliconix Si7860DP Q2, Q4 2 Lower-power MOSFETs Vishay-Siliconix Si7886DP R1, R2 4 Current-sense resistors, use two 2.7mΩ resistors in parallel, Panasonic ERJM1WSF2M7U R3, R13 2 2.2Ω ±1% resistors R4 2 7.5kΩ ±1% resistor R5, R6 2 1kΩ ±1% resistors RIN 1 4.99kΩ ±1% resistor Rf 1 37.4kΩ ±1% resistor R11 1 10kΩ ±1% resistor R12 1 10kΩ ±1% resistor RA 1 See the Overvoltage Protection (MAX5067) section RB 1 See the Overvoltage Protection (MAX5067) section RH 1 See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections RL 1 See the Adaptive Voltage Positioning and Voltage-Error Amplifier sections RX 1 Open circuit Table 2. Component Suppliers PHONE FAX Murata SUPPLIER 770-436-1300 770-436-3030 www.murata.com ON Semiconductor 602-244-6600 602-244-3345 www.on-semi.com Panasonic 714-373-7939 714-373-7183 www.panasonic.com TDK 847-803-6100 847-390-4405 www.tcs.tdk.com 1-800-551-6933 619-474-8920 www.vishay.com Vishay-Siliconix WEBSITE ______________________________________________________________________________________ 25 MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers all these issues when determining the number of phases necessary for the voltage regulator application. Inductor Selection The switching frequency per phase, peak-to-peak ripple current in each phase, and allowable ripple at the output determine the inductance value. Selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficiency. The charge/discharge cycle of the gate and drain capacitances in the switching MOSFETs create switching losses. The situation worsens at higher input voltages, since switching losses are proportional to the square of input voltage. Use 500kHz per phase for VIN = +5V and 250kHz or less per phase for VIN > +12V. Although lower switching frequencies per phase increase the peak-to-peak inductor ripple current (∆IL), the ripple cancellation in the multiphase topology reduces the input and output capacitor RMS ripple current. Use the following equation to determine the minimum inductance value: LMIN = (VINMAX − VOUT ) × VOUT VIN × fSW × ∆IL (10) Choose ∆IL equal to about 40% of the output current per phase. Since ∆IL affects the output-ripple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full-rated efficiency. Choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. Particular applications may require custom-made inductors. Use high-frequency core material for custom inductors. High ∆IL causes large peak-to-peak flux excursion increasing the core losses at higher frequencies. The high-frequency operation coupled with high ∆IL, reduces the required minimum inductance and even makes the use of planar inductors possible. The advantages of using planar magnetics include lowprofile design, excellent current-sharing between phases due to the tight control of parasitics, and low cost. For example, calculate the minimum inductance at VIN(MAX) = +13.2V, VOUT = +1.8V, ∆IL = 10A, and fSW = 250kHz: LMIN (13.2 − 1.8) × 1.8 = 0.6µH = (11) 13.2 × 250k × 10 The average-current-mode control feature of the 26 MAX5065/MAX5067 limits the maximum peak inductor current and prevents the inductor from saturating. Choose an inductor with a saturating current greater than the worst-case peak inductor current. Use the following equation to determine the worst-case inductor current for each phase: IL _ PEAK = 0.051V ∆IL + 2 RSENSE (12) where RSENSE is the sense resistor in each phase. Switching MOSFETs When choosing a MOSFET for voltage regulators, consider the total gate charge, RDS(ON), power dissipation, and package thermal impedance. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average gate-drive current from the MAX5065/ MAX5067 output is proportional to the total capacitance it drives from DH1, DH2, DL1, and DL2. The power dissipated in the MAX5065/MAX5067 is proportional to the input voltage and the average drive current. See the VIN, VCC, VDD section to determine the maximum total gate charge allowed from all the driver outputs combined. The gate charge and drain capacitance (CV2) loss, the cross-conduction loss in the upper MOSFET due to finite rise/fall time, and the I2R loss due to RMS current in the MOSFET RDS(ON) account for the total losses in the MOSFET. Estimate the power loss (PDMOS_) in the high-side and low-side MOSFETs using the following equations: PDMOS − HI = (QG × VDD × fSW ) + (13) VIN × IOUT × ( t R + t F ) × fSW 2 + 1.4RDS(ON) × I RMS − HI 4 where QG, RDS(ON), tR, and tF are the upper-switching MOSFET’s total gate charge, on-resistance at +25°C, rise time, and fall time, respectively. IRMS−HI = (I ) D 2 2 DC + I PK + IDC × IPK × (14) 3 where D = V OUT /V IN , I DC = (I OUT - ∆I L )/2 and I PK = (IOUT + ∆IL)/2 ______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers Input Capacitors (15) 2 2×C 2 OSS × VIN × fSW + 1.4R DS(ON) × I RMS − LO 3 where COSS is the MOSFET drain-to-source capacitance. IRMS−LO = (I ) ( ) 1− D 2 2 DC + I PK + IDC × IPK × (16) 3 For example, from the typical specifications in the Applications Information section with VOUT = +1.8V, the high-side and low-side MOSFET RMS currents are 9.9A and 24.1A, respectively. Ensure that the thermal impedance of the MOSFET package keeps the junction temperature at least 25°C below the absolute maximum rating. Use the following equation to calculate maximum junction temperature: TJ = PDMOS x θJ-A + TA (17) Table 3. Peak-to-Peak Output Ripple Current Calculations The discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple reflected back to the source dictate the capacitance requirement. Increasing the number of phases increases the effective switching frequency and lowers the peak-to-average current ratio, yielding a lower input capacitance requirement. The input ripple is comprised of ∆VQ (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the capacitor). Use low-ESR ceramic capacitors with high-ripple-current capability at the input. Assume the contributions from the ESR and capacitor discharge are equal to 30% and 70%, respectively. Calculate the input capacitance and ESR required for a specified ripple using the following equation: ESRIN = (∆VESR ) IOUT ∆IL + N 2 IOUT × D(1 − D) CIN = N ∆VQ × fSW (18) (19) NUMBER OF PHASES (N) DUTY CYCLE (D) EQUATION FOR ∆IP-P where IOUT is the total output current of the multiphase converter and N is the number of phases. 2 < 50% V (1 − 2D) ∆I = O L × fSW For example, at V OUT = +1.8V, the ESR and input capacitance are calculated for the input peak-to-peak ripple of 100mV or less yielding an ESR and capacitance value of 1mΩ and 200µF. 2 > 50% 4 0 to 25% V (1− 4D) ∆I = O L × fSW 4 25% to 50% V (1 − 2D)(4D − 1) ∆I = O 2 × D × L × fSW 4 > 50% V (2D − 1)(3 − 4D) ∆I = O D × L × fSW 6 < 17% V (1− 6D) ∆I = O L × fSW ∆I = (VIN − VO )(2D − 1) L × fSW Output Capacitors The worst-case peak-to-peak and capacitor RMS ripple current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage during step loads determine the capacitance and the ESR requirements for the output capacitors. In multiphase converter design, the ripple currents from the individual phases cancel each other and lower the ripple current. The degree of ripple cancellation depends on the operating duty cycle and the number of phases. Choose the right equation from Table 3 to calculate the peak-to-peak output ripple (∆IP-P) for a given duty cycle of two-, four-, and six-phase converters. The maximum ripple cancellation occurs when NPH = K / D. ______________________________________________________________________________________ 27 MAX5065/MAX5067 PDMOS − LO = (QG × VDD × fSW ) + MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers The allowable deviation of the output voltage during the fast transient load dictates the output capacitance and ESR. The output capacitors supply the load step until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closed-loop bandwidth of the converter. The resistive drop across the capacitor ESR and capacitor discharge causes a voltage drop during a step load. Use a combination of SP polymer and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output voltage deviation less than or equal to the adaptive voltage-positioning window (∆VOUT). Assume 50% contribution each from the output capacitance discharge and the ESR drop. Use the following equations to calculate the required ESR and capacitance value: ESROUT = ∆VESR ISTEP (20) I ×t COUT = STEP RESPONSE ∆VQ (21) where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth. Current Limit The average-current-mode control technique of the MAX5065/MAX5067 accurately limits the maximum output current per phase. The MAX5065/MAX5067 sense the voltage across the sense resistor and limit the peak inductor current (IL-PK) accordingly. The ON cycle terminates when the current-sense voltage reaches 45mV (min). Use the following equation to calculate maximum current-sense resistor value: 0.045 IOUT N (22) 2.5 × 10−3 RSENSE (23) RSENSE = PDR = where PDR is the power dissipation in sense resistors. Select 5% lower value of RSENSE to compensate for any parasitics associated with the PC board. Also, select a non inductive resistor with the appropriate wattage rating. Reverse Current Limit The MAX5065/MAX5067 limit the reverse current when VBUS is higher than the preset output voltage. 28 Calculate the maximum reverse current based on VCLR, the reverse-current-limit threshold, and the current-sense resistor. IREVERSE = 2 × VCLR RSENSE (24) where IREVERSE is the total reverse current into the converter. Compensation The main control loop consists of an inner current loop and an outer voltage loop. The MAX5065/MAX5067 use an average-current-mode control scheme to regulate the output voltage (Figure 4). IPHASE1 and IPHASE2 are the inner average current loops. The VEA output provides the controlling voltage for these current sources. The inner current loop absorbs the inductor pole reducing the order of the outer voltage loop to that of a single-pole system. A resistive feedback around the VEA provides the best possible response, since there are no capacitors to charge and discharge during large-signal excursions, RF and RIN determine the VEA gain. Use the following equation to calculate the value for RF: RF = IOUT × RIN N × GC × ∆VOUT (25) 0.05 RS (26) GC = where GC is the current-loop transconductance and N is number of phases. When designing the current-control loop ensure that the inductor downslope (when it becomes an upslope at the CEA output) does not exceed the ramp slope. This is a necessary condition to avoid sub-harmonic oscillations similar to those in peak current-mode control with insufficient slope compensation. Use the following equation to calculate the resistor RCF: RCF ≤ 2 × fSW × L × 102 VOUT × RSENSE (27) For example, the maximum RCF is 12kΩ for RSENSE = 1.35mΩ. CCF provides a low-frequency pole while RCF provides a midband zero. Place a zero at fZ to obtain a phase bump at the crossover frequency. Place a high-frequency pole ______________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers CCF = 1 2 × π × fZ × RCF 1 CCFF = 2 × π × fP × RCF (28) (29) PC Board Layout Use the following guidelines to layout the switching voltage regulator: 1) Place the VIN and VCC bypass capacitors close to the MAX5065/MAX5067. 2) Minimize the area and length of the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal. 3) Keep short the current loop from the lower-switching MOSFET, inductor, and output capacitor. 4) Place the Schottky diodes close to the lower MOSFETs and on the same side of the PC board. 5) Keep the SGND and PGND isolated and connect them at one single point close to the negative terminal of the input-filter capacitor. 6) Run the current-sense lines CS+ and CS- very close to each other to minimize the loop area. Similarly, run the remote-voltage sense lines SENSE+ and SENSE- close to each other. Do not cross these critical signal lines through power circuitry. Sense the current right at the pads of the current-sense resistors. 7) Avoid long traces between the VCC bypass capacitors, driver output of the MAX5065/MAX5067, MOSFET gates and PGND pin. Minimize the loop formed by the VCC bypass capacitors, bootstrap diode, bootstrap capacitor, MAX5065/MAX5067, and upper MOSFET gate. 8) Place the bank of output capacitors close to the load. 9) Distribute the power components evenly across the board for proper heat dissipation. 10) Provide enough copper area at and around the switching MOSFETs, inductor, and sense resistors to aid in thermal dissipation. 11) Use at least 4oz copper to keep the trace inductance and resistance to a minimum. Thin copper PC boards can compromise efficiency since high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance. Chip Information TRANSISTOR COUNT: 5451 PROCESS: BiCMOS Selector Guide PART OUTPUT MAX5065 Adjustable +0.6V to +3.3V MAX5067 Adjustable +0.8V to +3.3V with OVP, PGOOD, Phase Failure Detector ______________________________________________________________________________________ 29 MAX5065/MAX5067 (fP) at least a decade away from the crossover frequency to achieve maximum phase margin. Use the following equations to calculate CCF and CCFF: Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers CSP2 1 28 CLKIN CSN2 2 27 CLKOUT PHASE 3 26 BST2 PLLCMP 4 25 DH2 CLP2 5 24 LX2 SGND 6 MAX5065 23 DL2 22 PGND CLP1 7 BST2 SGND N.C. CLKOUT CLKIN CSN2 CSP2 PHASE CLP2 TOP VIEW PLLCMP N.C. 44 43 42 41 40 39 38 37 36 35 34 N.C. 1 33 N.C. N.C. 2 32 DH2 N.C. 3 31 LX2 N.C. 4 30 DL2 SGND 5 29 PGND OVPIN 6 28 IN CLP1 7 27 VCC OVPOUT 8 26 VDD MAX5067 SENSE+ 8 21 IN SENSE- 9 20 VCC PGOOD 9 25 DL1 DIFF 10 19 DL1 SENSE+ 10 24 LX1 EAN 11 18 LX1 SENSE- 11 23 DH1* EAOUT 12 17 DH1 CSP1 13 16 BST1 CSN1 14 15 EN 28 SSOP N.C. BST1 EN SGND N.C. CSN1 N.C. CSP1 EAN DIFF 12 13 14 15 16 17 18 19 20 21 22 EAOUT MAX5065/MAX5067 Pin Configurations 44 THIN QFN* *CONNECT THE THIN QFN EXPOSED PAD TO SGND GROUND PLANE. 30 _____________________________________________________________________________________ Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers SSOP.EPS 2 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C 0.20 0.09 0.004 0.008 SEE VARIATIONS D E e 0.205 0.212 0.0256 BSC 5.20 MILLIMETERS INCHES D D D D D 5.38 MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.33 7.33 0.317 0.397 0.328 0.407 8.07 10.07 8.33 10.33 N 14L 16L 20L 24L 28L 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.025 0∞ 0.037 8∞ 0.63 0∞ 0.95 8∞ N A C B e A1 L D NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. 21-0056 REV. 1 C ______________________________________________________________________________________ 1 31 MAX5065/MAX5067 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages. Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32, 44, 48L QFN.EPS MAX5065/MAX5067 Dual-Phase, +0.6V to +3.3V Output Parallelable, Average-Current-Mode Controllers D2 D CL D/2 b D2/2 k E/2 E2/2 E CL (NE-1) X e E2 k L DETAIL A e (ND-1) X e CL CL L L e A1 A2 e DALLAS SEMICONDUCTOR A PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L THIN QFN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 REV. 1 C 2 DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48L THIN QFN, 7x7x0.8 mm APPROVAL DOCUMENT CONTROL NO. 21-0144 REV. C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.