19-2734; Rev 1; 9/03 KIT ATION EVALU E L B A IL AVA Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies ♦ ±0.75% VOUT Accuracy Over Line, Load, and Temperature (1.3V) ♦ Active Voltage Positioning with Adjustable Gain and Offset ♦ 5-Bit On-Board DAC Mobile: 0.60V to 1.75V Output Range Desktop: 1.10V to 1.85V Output Range ♦ Selectable 100kHz/200kHz/300kHz/550kHz Switching Frequency ♦ 4V to 28V Battery Input Voltage Range ♦ Adjustable Slew-Rate Control ♦ Drive Large Synchronous Rectifier MOSFETs ♦ Output Overvoltage Protection (MAX1545 Only) ♦ Undervoltage and Thermal-Fault Protection ♦ Power Sequencing and Timing ♦ Selectable Suspend Voltage (0.675V to 1.45V) ♦ Soft-Shutdown ♦ Selectable Single- or Dual-Phase Pulse Skipping Ordering Information PART TEMP RANGE 40 Thin QFN 6mm ✕ 6mm MAX1545ETL -40°C to +100°C 40 Thin QFN 6mm ✕ 6mm Pentium is a registered trademark of Intel Corp. PGND 31 32 33 34 35 CMP V+ BSTS LXS DHS DLS 37 36 CSN CMN 38 CSP SUS S0 S1 SHDN 3 28 OFS REF ILIM 7 24 8 23 DLM DHM LXM BSTM VROK D0 D1 9 22 D2 VCC 10 21 D3 4 27 5 26 19 CODE D4 20 18 25 SKIP 16 15 6 14 MAX1519 MAX1545 17 Quick-PWM is a trademark of Maxim Integrated Products, Inc. VDD 29 13 Low-Voltage, Digitally Programmable Power Supplies 30 2 12 Servers/Desktop Computers 1 11 Voltage-Positioned Step-Down Converters TIME TON CCV GNDS CCI FB OAINOAIN+ Multiphase CPU Core Supply 39 TOP VIEW 40 Pin Configuration Applications Desktop and Mobile P4 Computers PIN-PACKAGE MAX1519ETL -40°C to +100°C GND The MAX1519/MAX1545 are intended for two different notebook CPU core applications: stepping down the battery directly or stepping down the 5V system supply to create the core voltage. The single-stage conversion method allows these devices to directly step down highvoltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery) at a higher switching frequency provides the minimum possible physical size. The MAX1519/MAX1545 comply with Intel’s P4 specifications. The switching regulator features soft-start, power-up sequencing, and soft-shutdown. The MAX1519/MAX1545 also feature independent four-level logic inputs for setting the suspend voltage (S0–S1). The MAX1519/MAX1545 include output undervoltage protection (UVP), thermal protection, and voltage regulator power-OK (VROK) output. When any of these protection features detect a fault, the controller shuts down. Additionally, the MAX1519/MAX1545 include overvoltage protection. The MAX1519/MAX1545 are available in low-profile, 40pin, 6mm x 6mm thin QFN packages. For other CPU platforms, refer to the pin-to-pin compatible MAX1544 and MAX1532/MAX1546/MAX1547 data sheets. Features ♦ Dual-Phase, Quick-PWM Controllers THIN QFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1519/MAX1545 General Description The MAX1519/MAX1545 are dual-phase, Quick-PWM™, step-down controllers for desktop and mobile Pentium®4 (P4) CPU core supplies. Dual-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The Quick-PWM control scheme provides instantaneous response to fast load-current steps. The MAX1519/MAX1545 include active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements. MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies ABSOLUTE MAXIMUM RATINGS V+ to GND ..............................................................-0.3V to +30V VCC to GND ..............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V SKIP, SUS, D0–D4 to GND.......................................-0.3V to +6V ILIM, FB, OFS, CCV, CCI, REF, OAIN+, OAIN- to GND.........................................-0.3V to (VCC + 0.3V) CMP, CSP, CMN, CSN, GNDS to GND ......-0.3V to (VCC + 0.3V) TON, TIME, VROK, S0–S1, CODE to GND.-0.3V to (VCC + 0.3V) SHDN to GND (Note 1)...........................................-0.3V to +18V DLM, DLS to PGND ....................................-0.3V to (VDD + 0.3V) BSTM, BSTS to GND ..............................................-0.3V to +36V DHM to LXM ...........................................-0.3V to (VBSTM + 0.3V) LXM to BSTM............................................................-6V to +0.3V DHS to LXS..............................................-0.3V to (VBSTS + 0.3V) LXS to BSTS .............................................................-6V to +0.3V GND to PGND .......................................................-0.3V to +0.3V REF Short-Circuit Duration .........................................Continuous Continuous Power Dissipation (TA = +70°C) 40-Pin 6mm ✕ 6mm Thin QFN (derate 23.2mW/°C above +70°C) ...............................1.860W Operating Temperature Range .........................-40°C to +100°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables fault protection and overlapping operation. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Battery voltage, V+ Input Voltage Range V+ = 4.5V to 28V, includes load regulation error DC Output Voltage Accuracy (Note 2) Line Regulation Error Input Bias Current 4 28 4.5 5.5 DAC codes ≥ 1V -10 +10 DAC codes from 0.60V to 1V -15 +15 VCC, VDD VCC = 4.5V to 5.5V, V+ = 4.5V to 28V IFB, IGNDS IOFS FB, GNDS OFS OFS Input Range OFS Gain AOFS TIME Frequency Accuracy -0.1 +0.1 0 2 -0.129 -0.125 -0.117 ∆VOUT/∆VOFS; ∆VOFS = VOFS - VREF, VOFS = 1V to 2V -0.129 -0.125 -0.117 fTIME µA V V/V +200 mV V/V ∆VOUT/∆VGNDS 0.97 0.99 1.01 1000kHz nominal, RTIME = 15kΩ 900 1000 1100 500kHz nominal, RTIME = 30kΩ 460 500 540 250kHz nominal, RTIME = 60kΩ 225 250 275 Shutdown, RTIME = 30kΩ 2 +2 -20 AGNDS mV mV -2 ∆VOUT/∆VOFS; ∆VOFS = VOFS, VOFS = 0 to 1V GNDS Input Range GNDS Gain 5 V 125 _______________________________________________________________________________________ kHz Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) PARAMETER On-Time (Note 3) SYMBOL tON Minimum Off-Time (Note 3) tOFF(MIN) CONDITIONS V+ = 12V, VFB = VCCI = 1.2V MIN TYP MAX TON = GND (550kHz) 155 180 205 TON = REF (300kHz) 320 355 390 UNITS ns TON = open (200kHz) 475 525 575 TON = VCC (100kHz) 920 1000 1140 TON = GND 300 375 TON = VCC, open, or REF 400 480 ns BIAS AND REFERENCE Quiescent Supply Current (VCC) ICC Measured at VCC, FB forced above the regulation point, OAIN- = FB, VOAIN+ = 1.3V 1.70 3.20 mA Quiescent Supply Current (VDD) IDD Measured at VDD, FB forced above the regulation point <1 5 µA Quiescent Battery Supply Current (V+) IV+ Measured at V+ 25 40 µA Measured at VCC, SHDN = GND 4 10 µA Shutdown Supply Current (VDD) Measured at VDD, SHDN = GND <1 5 µA Shutdown Battery Supply Current (V+) Measured at V+, SHDN = GND, VCC = VDD = 0 or 5V <1 5 µA 2.000 2.010 V +10 mV 19 % Shutdown Supply Current (VCC) Reference Voltage VREF Reference Load Regulation VCC = 4.5V to 5.5V, IREF = 0 1.990 ∆VREF IREF = -10µA to +100µA -10 VOVP SKIP = VCC, measured at FB with respect to unloaded output voltage 13 FAULT PROTECTION Output Overvoltage Protection Threshold (MAX1545 Only) SKIP = REF or GND Output Overvoltage Propagation Delay (MAX1545 Only) tOVP FB forced 2% above trip threshold Output Undervoltage Protection Threshold VUVP Measured at FB with respect to unloaded output voltage Output Undervoltage Propagation Delay tUVP FB forced 2% below trip threshold VROK Threshold Measured at FB with respect to unloaded output voltage 67 16 2.00 V 10 µs 70 73 10 % µs Lower threshold (undervoltage) -12 -10 -8 Upper threshold (overvoltage) SKIP = VCC +8 +10 +12 % _______________________________________________________________________________________ 3 MAX1519/MAX1545 ELECTRICAL CHARACTERISTICS (continued) MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) PARAMETER Output Undervoltage Fault and VROK Transition Blanking Time (Note 4) SYMBOL tBLANK tVROK VROK Output Low Voltage Thermal-Shutdown Threshold TYP 3 FB forced 2% outside the VROK trip threshold 5 TSHDN Hysteresis = 10°C Current-Limit Threshold Voltage (Positive, Default) VLIMIT CMP - CMN, CSP - CSN; ILIM = VCC Current-Limit Threshold Voltage (Positive, Adjustable) VLIMIT CMP - CMN, CSP - CSN Current-Limit Threshold Voltage (Negative) Current-Limit Threshold Voltage (Zero Crossing) 4.0 4.25 UNITS Clks 7 10 High state, VROK forced to 5.5V Rising edge, hysteresis = 90mV, PWM VUVLO(VCC) disabled below this level MAX 24 ISINK = 3mA VROK Leakage Current VCC Undervoltage Lockout Threshold MIN Measured from the time when FB reaches the voltage set by the DAC code; clock speed set by RTIME Measured from the time when FB first reaches the voltage set by the DAC code after startup VROK Startup Delay VROK Delay CONDITIONS ms µs 0.4 V 1 µA 4.4 V °C 160 CURRENT LIMIT AND BALANCE 28 30 32 VILIM = 0.2V 8 10 12 VILIM = 1.5V 73 75 77 VLIMIT(NEG) CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = VCC -41 -36 -31 VZERO CMP - CMN, CSP - CSN; SKIP = GND CMP, CMN, CSP, CSN Input Ranges CMP, CMN, CSP, CSN Input Current VCSP = VCSN = 0 to 5V Secondary Driver-Disable Threshold VCSP ILIM Input Current IILIM Current-Limit Default Switchover Threshold VILIM Current-Balance Offset VOS(IBAL) Current-Balance Transconductance Gm(IBAL) 4 1.5 mV mV mV 0 2 V -2 +2 µA VCC - 1 VCC 0.4 V 0.1 200 nA VCC - 1 VCC 0.4 V +2 mV 3 VILIM = 0 to 5V 3 (VCMP - VCMN) - (VCSP - VCSN); ICCI = 0, -20mV < (VCMP - VCMN) < 20mV, 1.0V < VCCI < 2.0V mV -2 400 _______________________________________________________________________________________ µS Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Ω GATE DRIVERS DH_ Gate-Driver On-Resistance DL_ Gate-Driver On-Resistance RON(DH) RON(DL) DH_ Gate-Driver Source/Sink Current DL_ Gate-Driver Sink Current DL_ Gate-Driver Source Current IDH IDL(SINK) BST_ - LX_ forced to 5V 1.0 4.5 High state (pullup) 1.0 4.5 Low start (pulldown) 0.4 2 DH_ forced to 2.5V, BST_ - LX_ forced to 5V 1.6 A 4 A 1.6 A DL_ forced to 5V IDL(SOURCE) DL_ forced to 2.5V Dead Time tDEAD DL_ rising 35 DH_ rising 26 Ω ns VOLTAGE-POSITIONING AMPLIFIER Input Offset Voltage VOS Input Bias Current IBIAS Op Amp Disable Threshold Common-Mode Input Voltage Range -1 OAIN+, OAIN- VOAINVCM 3 Guaranteed by CMRR test 0 +1 mV 0.1 200 nA VCC - 1 VCC 0.4 V 2.5 V Common-Mode Rejection Ratio CMRR VOAIN+ = VOAIN- = 0 to 2.5V 70 115 dB Power-Supply Rejection Ratio PSRR VCC = 4.5V to 5.5V 75 100 dB AOA RL = 1kΩ to VCC/2 80 112 Large-Signal Voltage Gain |VOAIN+ - VOAIN-| ≥ 10mV, RL = 1kΩ to VCC/2 Output Voltage Swing dB VCC - VFBH 77 300 VFBL 47 200 mV Input Capacitance 11 pF Gain-Bandwidth Product 3 MHz 0.3 V/µs 400 pF Slew Rate Capacitive-Load Stability No sustained oscillations LOGIC AND I/O SHDN Input High Voltage VIH SHDN Input Low Voltage VIL SHDN No-Fault Threshold VSHDN Three-Level Input Logic Levels 0.8 12 SUS, SKIP High 2.7 REF 1.2 Low SHDN, SUS, SKIP Logic Input Current D0–D4 Logic Input High Voltage D0–D4 Logic Input Low Voltage V 0.4 V 15 V 2.3 V 0.8 -1 +1 1.6 µA V 0.8 V _______________________________________________________________________________________ 5 MAX1519/MAX1545 ELECTRICAL CHARACTERISTICS (continued) MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) PARAMETER SYMBOL D0–D4 Input Current CONDITIONS D0–D4 MIN TYP -2 CODE Input High Voltage MAX UNITS +2 µA 2.4 V CODE Input Low Voltage CODE Input Current -1 Four-Level Input Logic Levels TON, S0–S1 V +1 µA V High VCC 0.4 Open 3.15 3.85 REF 1.65 2.35 Low Four-Level Input Current 0.8 TON, S0–S1 forced to GND or VCC 0.4 -3 +3 µA ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = -40°C to +100°C, unless otherwise specified.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Battery voltage, V+ Input Voltage Range 4 28 4.5 5.5 DAC codes ≥ 1V -13 +13 DAC codes from 0.60V to 1V -20 +20 0 2 ∆VOUT/∆VOFS; ∆VOFS = VOFS, VOFS = 0 to 1V -0.131 -0.115 ∆VOUT/∆VOFS; ∆VOFS = VOFS - VREF, VOFS = 1V to 2V -0.131 -0.115 VCC, VDD V+ = 4.5V to 28V, includes load regulation error DC Output Voltage Accuracy (Note 2) OFS Input Range OFS Gain GNDS Gain TIME Frequency Accuracy On-Time (Note 3) Minimum Off-Time (Note 3) 6 AOFS AGNDS fTIME tON tOFF(MIN) mV V V/V ∆VOUT/∆VGNDS 0.94 1.01 1000kHz nominal, RTIME = 15kΩ 880 1120 500kHz nominal, RTIME = 30kΩ 450 550 250kHz nominal, RTIME = 60kΩ 220 280 TON = GND (550kHz) 150 210 TON = REF (300kHz) 315 395 TON = open (200kHz) 470 580 TON = VCC (100kHz) 910 1150 V+ = 12V, VFB = VCCI = 1.2V V V/V kHz ns TON = GND 380 TON = VCC, open, or REF 490 _______________________________________________________________________________________ ns Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = -40°C to +100°C, unless otherwise specified.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BIAS AND REFERENCE Quiescent Supply Current (VCC) ICC Measured at VCC, FB forced above the regulation point, OAIN- = FB, VOAIN+ = 1.3V 3.2 mA Quiescent Supply Current (VDD) IDD Measured at VDD, FB forced above the regulation point 20 µA Quiescent Battery Supply Current (V+) IV+ Measured at V+ 50 µA Shutdown Supply Current (VCC) Measured at VCC, SHDN = GND 20 µA Shutdown Supply Current (VDD) Measured at VDD, SHDN = GND 20 µA Shutdown Battery Supply Current (V+) Measured at V+, SHDN = GND, VCC = VDD = 0 or 5V 20 µA 1.985 2.015 V Reference Voltage VREF VCC = 4.5V to 5.5V, IREF = 0 Output Overvoltage Protection Threshold (MAX1545 Only) VOVP SKIP = VCC, measured at FB with respect to unloaded output voltage 13 19 % Output Undervoltage Protection Threshold VUVP Measured at FB with respect to unloaded output voltage 67 73 % -13 -7 FAULT PROTECTION Measured at FB with respect to unloaded output voltage VROK Threshold Upper threshold (overvoltage) SKIP = VCC Measured from the time when FB first reaches the voltage set by the DAC code after startup VROK Startup Delay VCC Undervoltage Lockout Threshold Lower threshold (undervoltage) VUVLO(VCC) Rising edge, hysteresis = 90mV, PWM disabled below this level % +7 +13 3 ms 3.90 4.45 V 27 33 mV VILIM = 0.2V 7 13 VILIM = 1.5V 72 78 CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = VCC -30 -42 mV (VCMP - VCMN) - (VCSP - VCSN); ICCI = 0, -20mV < (VCMP - VCMN) < 20mV, 1.0V < VCCI < 2.0V -3 +3 mV CURRENT LIMIT AND BALANCE Current-Limit Threshold Voltage (Positive, Default) VLIMIT CMP - CMN, CSP - CSN; ILIM = VCC Current-Limit Threshold Voltage (Positive, Adjustable) VLIMIT CMP - CMN, CSP - CSN Current-Limit Threshold Voltage (Negative) VLIMIT(NEG) Current-Balance Offset VOS(IBAL) mV _______________________________________________________________________________________ 7 MAX1519/MAX1545 ELECTRICAL CHARACTERISTICS (continued) MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, V+ = 15V, VCC = VDD = V SHDN = VTON = V SKIP = VS0 = VS1 = VCODE = 5V, VFB = VCMP = VCMN = VCSP = VCSN = 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA = -40°C to +100°C, unless otherwise specified.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BST_ - LX_ forced to 5V 4.5 Ω High state (pullup) 4.5 GATE DRIVERS DH_ Gate-Driver On-Resistance RON(DH) DL_ Gate-Driver On-Resistance RON(DL) Low start (pulldown) 2 Ω VOLTAGE-POSITIONING AMPLIFIER Input Offset Voltage VOS Common-Mode Input Voltage Range VCM Guaranteed by CMRR test |VOAIN+ - VOAIN-| ≥ 10mV, RL = 1kΩ to VCC/2 Output Voltage Swing -2.0 +2.0 mV 0 2.5 V VCC - VFBH 300 VFBL 200 mV LOGIC AND I/O SHDN Input High Voltage VIH SHDN Input Low Voltage VIL Three-Level Input Logic Levels 0.8 SUS, SKIP High 2.7 REF 1.2 Low D0–D4 Logic Input High Voltage 0.4 V 2.3 V 0.8 1.6 D0–D4 Logic Input Low Voltage V 0.8 CODE Input High Voltage 2.4 CODE Input Low Voltage Four-Level Input Logic Levels V TON, S0–S1 V 0.8 V V High VCC 0.4 Open 3.15 3.85 REF 1.65 2.35 Low V 0.4 Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. When pulse skipping, the output slightly rises (< 0.5%) when transitioning from continuous conduction to no load. Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times may be different due to MOSFET switching speeds. Note 4: The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code. During normal operation (SUS = GND), regulation voltage is set by the VID DAC inputs (D0–D4). During suspend mode (SUS = REF or high), the regulation voltage is set by the suspend DAC inputs (S0–S1). Note 5: Specifications to TA = -40°C and +100°C are guaranteed by design and are not production tested. 8 _______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies VIN = 8V EFFICIENCY (%) 1.44 80 VIN = 12V 70 VIN = 20V 1.42 1.00 OUTPUT VOLTAGE (V) 90 1.48 1.46 1.02 MAX1519 toc02 1.50 60 1.40 10 20 30 40 50 1 10 0.90 100 20 30 40 50 60 LOAD CURRENT (A) EFFICIENCY vs. LOAD CURRENT (VOUT = 1.00V) OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 0.80V) DUAL-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.80V) VIN = 12V VIN = 20V 60 0.78 0.76 SKIP = REF 10 1 80 70 VIN = 12V VIN = 20V 60 0.74 50 0.72 0.1 VIN = 8V 90 SKIP = REF SKIP = VCC 50 MAX1519 toc06 0.80 100 MAX1519 toc05 SUS = VCC EFFICIENCY (%) 80 70 0.82 OUTPUT VOLTAGE (V) 90 0 100 10 20 30 0.1 40 10 1 100 LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A) SINGLE-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 0.80V) SWITCHING FREQUENCY vs. LOAD CURRENT NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (FORCED-PWM MODE) 90 80 70 VIN = 12V VIN = 20V 150 300 SKIP = VCC 120 SUPPLY CURRENT (mA) VIN = 8V 400 MAX1532toc08 SKIP = GND SWITCHING FREQUENCY (kHz) MAX1519 toc07 100 EFFICIENCY (%) 10 0 LOAD CURRENT (A) VIN = 8V 60 0.94 LOAD CURRENT (A) 100 EFFICIENCY (%) 0.1 60 MAX1519 toc04 0 0.96 0.92 SKIP = REF SKIP = VCC 50 1.38 0.98 FORCED-PWM (SKIP = VCC) 200 SKIP MODE (SKIP = REF) 100 MAX1519 toc09 OUTPUT VOLTAGE (V) 100 MAX1519 toc01 1.52 OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.00V) EFFICIENCY vs. LOAD CURRENT (VOUT = 1.50V) MAX1519 toc03 OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.50V) ICC + IDD 90 60 30 IIN VOUT = 1V (NO LOAD) 50 0 0 0.1 1 10 LOAD CURRENT (A) 100 0 10 20 LOAD CURRENT (A) 30 40 0 5 10 15 20 25 30 INPUT VOLTAGE (V) _______________________________________________________________________________________ 9 MAX1519/MAX1545 Typical Operating Characteristics (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = VCC), OFS = GND, TA = +25°C, unless otherwise specified.) Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = VCC), OFS = GND, TA = +25°C, unless otherwise specified.) OUTPUT OFFSET VOLTAGE vs. OFS VOLTAGE 1.0 SAMPLE SIZE = 100 40 50 0 -50 30 20 10 -100 0.5 IIN -150 0 0 0.5 1.0 0 1.990 2.0 1.5 INPUT VOLTAGE (V) OFS VOLTAGE (V) 2.005 2.000 REFERENCE VOLTAGE (V) CURRENT-BALANCE OFFSET VOLTAGE DISTRIBUTION CURRENT-LIMIT THRESHOLD DISTRIBUTION VOLTAGE-POSITIONING AMPLIFIER GAIN AND PHASE vs. FREQUENCY 5 10 15 20 25 30 50 MAX1519 toc13 50 SAMPLE SIZE = 100 SAMPLE PERCENTAGE (%) 40 VILIM = 0.20V SAMPLE SIZE = 100 30 20 40 1.995 2.010 MAX1519 toc15 60 30 20 144 40 108 72 GAIN 20 36 10 0 0 -36 -10 10 10 0 0 -72 PHASE -20 -108 -144 -30 -2.50 0 -1.25 1.25 2.50 9.5 9.0 OFFSET VOLTAGE (mV) 10.0 10.5 120 100 80 MAX1519 toc17 0.8 IL(CS) - IL(CM) (A) 140 SKIP = REF 0.6 0.4 SKIP = VCC 60 0.2 VPS AMPLIFIER DISABLED 20 100 FREQUENCY (kHz) 1.0 MAX1519 toc16 160 40 10 INDUCTOR CURRENT DIFFERENCE vs. LOAD CURRENT 180 OFFSET VOLTAGE (µV) 1 CURRENT LIMIT (mV) VPS AMPLIFIER OFFSET VOLTAGE vs. COMMON-MODE VOLTAGE RSENSE = 1mΩ 0 0 0 1 2 3 4 COMMON-MODE VOLTAGE (V) 10 -40 0.1 11.0 5 0 10 180 50 30 GAIN (dB) 0 UNDEFINED REGION 20 30 40 LOAD CURRENT (A) ______________________________________________________________________________________ 50 1000 -180 10,000 PHASE (DEGREES) ICC + IDD 1.5 100 SAMPLE PERCENTAGE (%) 2.0 50 MAX1519 toc14 SUPPLY CURRENT (mA) 2.5 150 MAX1519 toc11 SKIP = REF OUTPUT OFFSET VOLTAGE (mV) MAX1519 toc10 3.0 REFERENCE VOLTAGE DISTRIBUTION MAX1519 toc12 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (PULSE SKIPPING) SAMPLE PERCENTAGE (%) MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies SOFT-START POWER-UP SEQUENCE MAX1519 toc19 MAX1519 toc18 5V 5V A A 0V 0V 1.5V 2V B 0V B 1V C 10A 0V 5V C 0A D 0V 0A 100µs/div 1ms/div A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. IL1, 10A/div D. IL2, 10A/div RLOAD = 75mΩ, RTIME = 64.9kΩ A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. VROK, 5V/div RTIME = 64.9kΩ 1.50V LOAD TRANSIENT (10A TO 50A LOAD) SOFT-SHUTDOWN MAX1519 toc21 MAX1519 toc20 5V A 50A A 10A 0V 1.5V 1.5V B B 0V 20A 10A C 10A D 0A 200µs/div A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. IL1, 10A/div D. IL2, 10A/div RLOAD = 75mΩ, RTIME = 64.9kΩ 20A 0A C 0A D 20µs/div A. LOAD CURRENT, (ILOAD = 10A TO 50A), 50A/div B. OUTPUT VOLTAGE (1.5V NO LOAD), 100mV/div C. IL1, 10A/div D. IL2, 10A/div ______________________________________________________________________________________ 11 MAX1519/MAX1545 Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = VCC), OFS = GND, TA = +25°C, unless otherwise specified.) MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = VCC), OFS = GND, TA = +25°C, unless otherwise specified.) 1.00V LOAD TRANSIENT (10A TO 30A LOAD) OFFSET TRANSITION MAX1519 toc22 30A MAX1519 toc23 A 10A 0.2V A 0V B 1.5V B 0A 10A C 5A C 0A D 5A D 1.0V 10A 20µs/div 20µs/div A. LOAD CURRENT, (ILOAD = 10A TO 30A), 25A/div B. OUTPUT VOLTAGE (1.00V NO LOAD), 50mV/div C. IL1, 10A/div D. IL2, 10A/div A. VOFS = 0 TO 200mV, 0.2V/div B. VOUT = 1.500V TO 1.475V, 20mV/div C. IL1, 10A/div D. IL2, 10A/div 10A LOAD SUSPEND TRANSITION (DUAL-PHASE PWM OPERATION) SUSPEND TRANSITION (SINGLE-PHASE SKIP OPERATION) MAX1519 toc24 3.3V 0V MAX1519 toc25 A 1.5V 3.3V 0V A 1.5V B 1.0V B 1.0V 10A 2.5A C C 0A 2.5A D 10A D 0A 40µs/div A. SUS, 5V/div B. VOUT = 1.5V TO 1.0V, 0.5V/div C. IL1, 10A/div D. IL2, 10A/div 5A LOAD, SKIP = VCC, RTIME = 64.9kΩ 12 100µs/div A. SUS, 5V/div B. VOUT = 1.5V TO 1.0V, 0.5V/div C. IL1, 10A/div D. IL2, 10A/div 5A LOAD, COUT = (4) 680µF, SKIP = SUS, RTIME = 64.9kΩ ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies SINGLE-PHASE SKIP TO DUAL-PHASE PWM TRANSITION DUAL-PHASE SKIP TO DUAL-PHASE PWM TRANSITION MAX1519 toc26 MAX1519 toc27 A 5V 2V A 1.5V B 1.5V B 0A C 0A C 0A D 0A D 5V 20µs/div 20µs/div A. SKIP = VCC TO REF, 5V/div B. 1.5V OUTPUT, 50mV/div C. IL1, 10A/div D. IL2, 10A/div 2A LOAD A. SKIP = VCC TO GND, 5V/div B. 1.5V OUTPUT, 50mV/div C. IL1, 10A/div D. IL2, 10A/div 2A LOAD 100mV DAC CODE TRANSITION 400mV DAC CODE TRANSITION MAX1519 toc28 MAX1519 toc29 3.3V 3.3V A 0V A 0V 1.5V 1.5V B B 1.1V 1.4V 5A C 5A C 5A 5A D D 20µs/div A. D1, 5V/div B. VOUT = 1.50V TO 1.40V, 100mV/div C. IL1, 10A/div D. IL2, 10A/div 10A LOAD 40µs/div A. D3, 5V/div B. VOUT = 1.50V TO 1.10V, 0.5V/div C. IL1, 10A/div D. IL2, 10A/div 10A LOAD ______________________________________________________________________________________ 13 MAX1519/MAX1545 Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 12V, VCC = VDD = 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = VCC), OFS = GND, TA = +25°C, unless otherwise specified.) Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 Pin Description PIN NAME 1 TIME Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 150kΩ to 15kΩ resistor sets the clock from 100kHz to 1MHz, fSLEW = 500kHz × 30kΩ/RTIME. 2 TON On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the DH_ on-time (see the On-Time One-Shot TON section): GND = 550kHz, REF = 300kHz, OPEN = 200kHz, VCC = 100kHz. SUS Suspend Input. SUS is a three-level logic input. When the controller detects on-transition on SUS, the controller slews the output voltage to the new voltage level determined by SUS, S0–S1, and D0–D4. The controller blanks VROK during the transition and another 24 RTIME clock cycles after the new DAC code is reached. Connect SUS as follows to select which multiplexer sets the nominal output voltage: 3.3V or VCC (high) = suspend mode; S0–S1 low-range suspend code (Table 5), REF = suspend mode; S0–S1 high-range suspend code (Table 5), GND = normal operation; D0–D4 VID DAC code (Table 4). S0, S1 Suspend-Mode Voltage Select Inputs. S0–S1 are four-level digital inputs that select the suspend mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage setting (Figure 3). SHDN Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal operation. Connect to ground to put the IC into its 1µA (typ) shutdown state. During the transition from normal operation to shutdown, the output voltage ramps down at 4 times the output-voltage slew rate programmed by the TIME pin. In shutdown mode, DLM and DLS are forced to VDD to clamp the output to ground. Forcing SHDN to 12V ~ 15V disables both overvoltage protection and undervoltage protection circuits, disables overlap operation, and clears the fault latch. Do not connect SHDN to >15V. 7 OFS Voltage-Divider Input for Offset Control. For 0 < VOFS < 0.8V, 0.125 times the voltage at OFS is subtracted from the output. For 1.2V < VOFS < 2V, 0.125 times the difference between REF and OFS is added to the output. Voltages in the range of 0.8V < VOFS < 1.2V are undefined. The controller disables the offset amplifier during suspend mode (SUS = REF or high). 8 REF 2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor. The reference can source 100µA for external loads. Loading REF degrades output voltage accuracy according to the REF load regulation error. 9 ILIM Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is tied to VCC. In adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a 0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately VCC - 1V. 10 VCC Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC as possible. 11 GND Analog Ground. Connect the MAX1519/MAX1545’s exposed pad to analog ground. CCV Voltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF, typ) capacitor from CCV to analog ground (GND) to set the integration time constant. 3 4, 5 6 12 14 FUNCTION ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies PIN NAME 13 GNDS Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator ground to the load ground. 14 CCI Current-Balance Compensation. Connect a 470pF capacitor between CCI and FB (see the CurrentBalance Compensation (CCI) section). 15 FB Feedback Input. FB is internally connected to both the feedback input and the output of the voltagepositioning op amp. See the Setting Voltage Positioning section to set the voltage-positioning gain. 16 OAIN- Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for additional voltage-positioning gain, connect to the negative terminal of the current-sense resistor through a resistor as described in the Setting Voltage Positioning section. Connect OAIN- to VCC to disable the op amp. The logic threshold to disable the op amp is approximately VCC - 1V. 17 OAIN+ Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain, connect to the positive terminal of the current-sense resistor through a resistor as described in the Setting Voltage Positioning section. 18 SKIP Pulse-Skipping Select Input. When pulse skipping, the controller blanks the VROK upper threshold: 3.3V or VCC (high) = Dual-phase forced-PWM operation, REF = Dual-phase pulse-skipping operation, GND = Single-phase pulse-skipping operation. 19 CODE VID DAC Code Selection Output. Connect CODE to GND to select the desktop P4 code set, or connect CODE to VCC to select the mobile P4 code set (Table 4). D4–D0 Low-Voltage VID DAC Code Inputs. The D0–D4 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the output voltage is set by the VID code indicated by the logic-level voltages on D0–D4. In suspend mode (Table 5, SUS = REF or high), the decoded state of the four-level S0–S1 inputs sets the output voltage. 25 VROK Open-Drain Power-Good Output. After output voltage transitions, except during power-up and powerdown, if OUT is in regulation, then VROK is high impedance. The controller blanks VROK whenever the slew-rate control is active (output voltage transitions). VROK is forced low in shutdown. A pullup resistor on VROK causes additional finite shutdown current. During power-up, VROK includes a 3ms (min) delay after the output reaches the regulation voltage. 26 BSTM Main Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM pullup current to be adjusted. 27 LXM Main Inductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver. 28 DHM Main High-Side Gate-Driver Output. Swings LXM to BSTM. 29 DLM Main Low-Side Gate-Driver Output. DLM swings from PGND to VDD. DLM is forced high after the MAX1519/MAX1545 power down. 30 VDD Supply Voltage Input for the DLM and DLS Gate Drivers. Connect to the system supply voltage (4.5V to 5.5V). Bypass VDD to PGND with a 2.2µF or greater ceramic capacitor as close to the IC as possible. 20–24 FUNCTION ______________________________________________________________________________________ 15 MAX1519/MAX1545 Pin Description (continued) Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 Pin Description (continued) PIN NAME FUNCTION 31 PGND 32 DLS Secondary Low-Side Gate-Driver Output. DLS swings from PGND to VDD. DLS is forced high after the MAX1519/MAX1545 power down. 33 DHS Secondary High-Side Gate-Driver Output. Swings LXS to BSTS. 34 LXS Secondary Inductor Connection. LXS is the internal lower supply rail for the DHS high-side gate driver. 35 BSTS Secondary Boost Flying Capacitor Connection. An optional resistor in series with BSTS allows the DHS pullup current to be adjusted. 36 V+ Battery Voltage-Sense Connection. Used only for PWM one-shot timing. DH_ on-time is inversely proportional to input voltage over a range of 4V to 28V. Power Ground. Ground connection for low-side gate drivers DLM and DLS. 37 CMP Main Inductor Positive Current-Sense Input 38 CMN Main Inductor Negative Current-Sense Input 39 CSN Secondary Inductor Positive Current-Sense Input 40 CSP Secondary Inductor Negative Current-Sense Input Detailed Description Dual 180° Out-of-Phase Operation The two phases in the MAX1519/MAX1545 operate 180° out-of-phase (SKIP = REF or high) to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count—reducing cost, board space, and component power requirements—making the MAX1519/MAX1545 ideal for highpower, cost-sensitive applications. Typically, switching regulators provide transfer power using only one phase instead of dividing the power among several phases. In these applications, the input capacitors must support high instantaneous current requirements. The high-RMS ripple current can lower efficiency due to I2R power loss associated with the input capacitor’s effective series resistance (ESR). Therefore, the system typically requires several low-ESR input capacitors in parallel to minimize input voltage ripple, reduce ESR-related power losses, and to meet the necessary RMS ripple current rating. With the MAX1519/MAX1545, the controller shares the current between two phases that operate 180° out-ofphase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of either phase is effectively cut in half, resulting in reduced input voltage ripple, ESR power 16 loss, and RMS ripple current (see the Input Capacitor Selection section). As a result, the same performance can be achieved with fewer or less expensive input capacitors. Transient Overlap Operation When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 180° out-ofphase when a transient occurs actually respond slower than an equivalent single-phase controller. In order to provide fast transient response, the MAX1519/ MAX1545 support a phase-overlap mode, which allows the dual regulators to operate in-phase when heavy load transients are detected, reducing the response time. After either high-side MOSFET turns off and if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the controller simultaneously turns on both high-side MOSFETs during the next on-time cycle. This maximizes the total inductorcurrent slew rate. The phases remain overlapped until the output voltage exceeds the regulation voltage and after the minimum off-time expires. After the phase-overlap mode ends, the controller automatically begins with the opposite phase. For example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends. ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 Table 1. Component Selection for Standard Multiphase Applications* DESIGNATION MAX1519/MAX1545 2-PHASE DESKTOP P4 MAX1519/MAX1545 4- PHASE DESKTOP P4 Circuit of Figure 1 Circuit of Figure 12 Input Voltage Range 7V to 24V 7V to 24V VID Output Voltage (D4–D0) 1.5V (CODE = GND, D4–D0 = 01110) 1.5V (CODE = GND, D4–D0 = 01110) Not Used (SUS = GND) Not Used (SUS = GND) 60A 60A Two phases (1) MAX1519/MAX1545 Four phases (1) MAX1519/MAX1545 + (2) MAX1980 0.6µH Panasonic ETQP1H0R6BFA 0.7µH Panasonic ETQP2H0R7BFA or 0.8µH Sumida CDEP105L-0R8 Suspend Voltage (SUS, S0–S1) Maximum Load Current Number of Phases (ηTOTAL) Inductor (per phase) Switching Frequency 300kHz (TON = REF) 300kHz (TON = REF) High-Side MOSFET (NH, per phase) Siliconix (1) Si7886DP International Rectifier (2) IRF6604 International Rectifier (1) IRF7811W or Fairchild (1) FDS6694 Low-Side MOSFET (NL, per phase) Siliconix (2) Si7442DP or International Rectifier (2) IRF6603 Fairchild (2) FDS6688 or Siliconix (1) Si7442DP Total Input Capacitance (CIN) (6) 10µF, 25V Taiyo Yuden TMK432BJ106KM or TDK C4532X5R1E106M (6) 10µF, 25V Taiyo Yuden TMK432BJ106KM or TDK C4532X5R1E106M (4) 680µF, 2.5V Sanyo 2R5TPD680M (4) 680µF, 2.5V Sanyo 2R5TPD680M 1.0mΩ Panasonic ERJM1WTJ1M0U 1.5mΩ Panasonic ERJM1WTJ1M5U Total Output Capacitance (COUT) Current-Sense Resistor (RSENSE, per phase) *Contact Intel for the Mobile P4 specifications and contact Maxim for a reference schematic. Power-Up Sequence The MAX1519/MAX1545 are enabled when SHDN is driven high (Figure 2). The reference powers up first. Once the reference exceeds its undervoltage lockout threshold, the PWM controller evaluates the DAC target and starts switching. For the MAX1519/MAX1545, the slew-rate controller ramps up the output voltage in 25mV increments to the proper operating voltage (see Tables 3 and 4) set by either D0–D4 (SUS = GND) or S0–S1 (SUS = REF or high). The ramp rate is set with the RTIME resistor (see the Output Voltage Transition Timing section). The con- troller pulls VROK low until at least 3ms after the MAX1519/MAX1545 reach the target DAC code. Shutdown When SHDN goes low, the MAX1519/MAX1545 enter low-power shutdown mode. VROK is pulled low immediately, and the output voltage ramps down to 0V in 25mV increments at 4 times the clock rate set by RTIME: t SHDN ≤ VDAC fSLEW VLSB 4 ______________________________________________________________________________________ 17 MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies R11 100kΩ C1 2.2µF R10 10Ω C2 1µF POWERGOOD VDD VCC MAX1519 MAX1545 VROK D0 D1 D2 D3 D4 DAC INPUTS GND (DESKTOP P4) SUSPEND INPUTS (FOUR-LEVEL LOGIC) ON OFF U1 CODE S0 S1 SHDN 5V BIAS SUPPLY BST DIODES V+ BSTM INPUT* 7V TO 24V CIN CBST1 0.22µF DHM NH1 TIME CCCV 47pF COUT LXM DLM NL1 PGND R2 1kΩ ±1% GND RTIME 64.9kΩ RSENSE1 1.0mΩ L1 CMN CMP OAIN+ OAIN- R3 1kΩ ±1% R6 1.5kΩ ±1% CCV OUTPUT CREF 0.22µF REF (300kHz) R1 1.5kΩ ±1% TON REF R8 R9 49.9kΩ 100kΩ ±1% ±1% FB ILIM REF C3 100pF R28 182kΩ ±1% CCI CSP CSN BSTS R27 20kΩ ±1% DHS R5 1kΩ ±1% CIN NH2 L2 RSENSE2 1.0mΩ LXS DLS PWM SKIP CCCI 470pF CBST2 0.22µF OFS STP_CPU# R4 1kΩ ±1% COUT NL2 SKIP SUS GNDS POWER GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. ANALOG GROUND Figure 1. Standard Two-Phase Desktop P4 Application Circuit 18 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 SHDN DO NOT CARE VID (D0–D4) SOFT-SHUTDOWN 1LSB PER 4 RTIME CYCLES SOFT-START 1LSB PER RTIME CYCLE VCORE VROK tVROK(START) 3ms, TYP Figure 2. Power-Up and Shutdown Sequence Timing Diagram Table 2. Component Suppliers MANUFACTURER PHONE WEBSITE BI Technologies 714-447-2345 (USA) www.bitechnologies.com Central Semiconductor 631-435-1110 (USA) www.centralsemi.com Coilcraft 800-322-2645 (USA) www.coilcraft.com Coiltronics 561-752-5000 (USA) www.coiltronics.com Fairchild Semiconductor 888-522-5372 (USA) www.fairchildsemi.com International Rectifier 310-322-3331 (USA) www.irf.com Kemet 408-986-0424 (USA) www.kemet.com Panasonic 847-468-5624 (USA) www.panasonic.com 65-6281-3226 (Singapore) www.secc.co.jp Siliconix (Vishay) 203-268-6261 (USA) www.vishay.com Sumida 408-982-9660 (USA) www.sumida.com 03-3667-3408 (Japan) 408-573-4150 (USA) www.t-yuden.com Sanyo Taiyo Yuden TDK TOKO 847-803-6100 (USA) 81-3-5201-7241 (Japan) 858-675-8013 (USA) where fSLEW = 500kHz ✕ 30kΩ/RTIME, VDAC is the DAC setting when the controller begins the shutdown sequence, and VLSB = 25mV is the DAC’s smallest voltage increment. Slowly discharging the output capacitors by slewing the output over a long period of time (4/fSLEW) keeps the average negative inductor current low (damped response), thereby eliminating the negative output voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). www.component.tdk.com www.tokoam.com This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output voltage excursion. When the DAC reaches the 0V setting, DL_ goes high, DH_ goes low, the reference turns off, and the supply current drops to about 1µA. When a fault condition—output undervoltage lockout, output overvoltage lockout (MAX1545), or thermal shutdown—activates the shutdown sequence, the controller sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 1V. ______________________________________________________________________________________ 19 MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies Table 3. Operating Mode Truth Table SHDN SUS SKIP OFS OUTPUT VOLTAGE GND x x x GND Low-Power Shutdown Mode. DL_ is forced high, DH_ is forced low, and the PWM controller is disabled. The supply current drops to 1µA (typ). VCC GND VCC GND or REF D0–D4 (no offset) Normal Operation. The no-load output voltage is determined by the selected VID DAC code (CODE and D0–D4, Table 4). VCC x REF or GND GND or REF D0–D4 (no offset) Pulse-Skipping Operation. When SKIP is pulled low, the MAX1519/MAX1545 immediately enter pulse-skipping operation, allowing automatic PWM/PFM switchover under light loads. The VROK upper threshold is blanked. VCC GND x 0 to 0.8V or 1.2V to 2V D0–D4 (plus offset) Deep-Sleep Mode. The no-load output voltage is determined by the selected VID DAC code (CODE and D0–D4, Table 4), plus the offset voltage set by OFS. VCC REF or high x x SUS, S0–S1 (no offset) Suspend Mode. The no-load output voltage is determined by the selected suspend code (SUS, S0–S1, Table 5), overriding all other active modes of operation. GND Fault Mode. The fault latch has been set by either UVP, OVP (MAX1545 only), or thermal shutdown. The controller remains in FAULT mode until VCC power is cycled or SHDN toggled. VCC x x x When SHDN goes high, the reference powers up. Once the reference voltage exceeds its UVLO threshold, the controller evaluates the DAC target and starts switching. The slew-rate controller ramps up from 0V in 25mV increments to the currently selected output-voltage setting (see the Power-Up Sequence section). There is no traditional soft-start (variable current-limit) circuitry, so full output current is available immediately. OPERATING MODE a new output voltage level. Change D0–D4 together, avoiding greater than 1µs skew between bits. Otherwise, incorrect DAC readings can cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with desktop and mobile P4 (Table 4) specifications. Internal Multiplexers Four-Level Logic Inputs The MAX1519/MAX1545 have a unique internal DAC input multiplexer (muxes) that selects one of three different DAC code settings for different processor states (Figure 3). On startup, the MAX1519/MAX1545 select the DAC code from the D0–D4 (SUS = GND) or S0–S1 (SUS = REF or high) input decoders. TON and S0–S1 are four-level logic inputs. These inputs help expand the functionality of the controller without adding an excessive number of pins. The fourlevel inputs are intended to be static inputs. When left open, an internal resistive voltage-divider sets the input voltage to approximately 3.5V. Therefore, connect the four-level logic inputs directly to VCC, REF, or GND when selecting one of the other logic levels. See Electrical Characteristics for exact logic level voltages. DAC Inputs (CODE, D0–D4) During normal forced-PWM operation (SUS = GND), the DAC programs the output voltage using code and the D0–D4 inputs. Connect CODE to VCC or GND for the mobile or desktop P4 setting, respectively. Do not leave D0–D4 unconnected. D0–D4 can be changed while the MAX1519/MAX1545 are active, initiating a transition to 20 Suspend Mode When the processor enters low-power suspend mode, it sets the regulator to a lower output voltage to reduce power consumption. The MAX1519/MAX1545 include ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 D0–D4 DECODER D0 D1 D2 D3 D4 IN OUT CODE 0 SUSPEND MUX SEL S0–S1 DECODER S0 S1 IN OUT SEL 1 OUT DAC SEL SUS 2.5V SUS 3-LEVEL DECODER 1.0V Figure 3. Internal Multiplexers Functional Diagram independent suspend-mode output voltage codes set by the four-level S0–S1 inputs and the three-level SUS input. When the CPU suspends operation (SUS = REF or high), the controller disables the offset amplifier and overrides the 5-bit VID DAC code set by D0–D4 (normal operation). The master controller slews the output to the selected suspend-mode voltage. During the transition, the MAX1519/MAX1545 blank VROK and the UVP fault protection until 24 RTIME clock cycles after the slew-rate controller reaches the suspend-mode voltage. SUS is a three-level logic input: GND, REF, or high. This expands the functionality of the controller without adding an additional pin. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive-divider from V CC ) or to a logic-level bias supply (3.3V or greater). When pulled up to REF, the MAX1519/ MAX1545 select the upper suspend voltage range. When pulled high (2.7V or greater), the controller selects the lower suspend voltage range. See Electrical Characteristics for exact logic level voltages. Output Voltage Transition Timing The MAX1519/MAX1545 are designed to perform mode transitions in a controlled manner, automatically minimiz- ing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. At the beginning of an output voltage transition, the MAX1519/MAX1545 blank the VROK output, preventing them from changing states. VROK remains blanked during the transition and is enabled 24 clock cycles after the slew-rate controller has set the final DAC code value. The slew-rate clock frequency (set by resistor RTIME) must be set fast enough to ensure that the transition is completed within the maximum allotted time. The slew-rate controller transitions the output voltage in 25mV steps during soft-start, soft-shutdown, and suspend-mode transitions. The total time for a transition depends on R TIME , the voltage difference, and the accuracy of the MAX1519/MAX1545s’ slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX1519/MAX1545 automatically control the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less ______________________________________________________________________________________ 21 MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies SUS 1 LSB PER RTIME CYCLE VDAC OUTPUT SET BY D0–D4 OUTPUT SET BY SUS AND S0–S1 tSLEW tBLANK = 24 CLKS tSLEW tBLANK = 24 CLKS TIME CLOCK VROK VROK BLANKING VROK BLANKING Figure 4. Suspend Transition than the current limit set by ILIM. The transition time is given by: t SLEW ≈ t SLEW ≈ 1 VOLD − VNEW for VOUT rising fSLEW VLSB VOLD − VNEW + 2 for VOUT falling fSLEW VLSB 1 where fSLEW = 500kHz ✕ 30kΩ / RTIME, VOLD is the original DAC setting, VNEW is the new DAC setting, and V LSB is the DAC’s smallest voltage increment. The additional two clock cycles on the falling edge time are due to internal synchronization delays. See TIME Frequency Accuracy in the Electrical Characteristics for fSLEW limits. The practical range of RTIME is 15kΩ to 150kΩ corresponding to 1.0µs to 10µs per 25mV step. Although the DAC takes discrete steps, the output filter makes the transitions relatively smooth. The average inductor current required to make an output voltage transition is: IL ≅ COUT × VLSB × fSLEW Fault Protection Output Overvoltage Protection (MAX1545 Only) The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX1519/MAX1545 continuously monitor the output for 22 an overvoltage fault. During normal forced-PWM operation (SKIP = high), the controller detects an OVP fault if the output voltage exceeds the set DAC voltage by more than 13% (min). During pulse-skipping operation (SKIP = REF or GND), the controller detects an OVP fault if the output voltage exceeds the fixed 2V (typ) threshold. When the OVP circuit detects an overvoltage fault, it immediately sets the fault latch, pulls VROK low, and activates the shutdown sequence. This action discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 1V. Overvoltage protection can be disabled through the “nofault” test mode (see the No-Fault Test Mode section). Output Undervoltage Shutdown The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX1519/MAX1545 output voltage is under 70% of the nominal value, the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate-driver high, and pulls the DH_ high-side gate-driver low. Toggle SHDN or cycle the VCC power supply below 1V to clear the fault latch and reactivate the controller. UVP is ignored during output voltage transitions and remains blanked ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies CODE = VCC CODE = GND D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 0 0 0 0 0 1.750 0 0 0 0 0 1.850 0 0 0 0 1 1.700 0 0 0 0 1 1.825 0 0 0 1 0 1.650 0 0 0 1 0 1.800 0 0 0 1 1 1.600 0 0 0 1 1 1.775 0 0 1 0 0 1.550 0 0 1 0 0 1.750 0 0 1 0 1 1.500 0 0 1 0 1 1.725 0 0 1 1 0 1.450 0 0 1 1 0 1.700 0 0 1 1 1 1.400 0 0 1 1 1 1.675 0 1 0 0 0 1.350 0 1 0 0 0 1.650 0 1 0 0 1 1.300 0 1 0 0 1 1.625 0 1 0 1 0 1.250 0 1 0 1 0 1.600 0 1 0 1 1 1.200 0 1 0 1 1 1.575 0 1 1 0 0 1.150 0 1 1 0 0 1.550 0 1 1 0 1 1.100 0 1 1 0 1 1.525 0 1 1 1 0 1.050 0 1 1 1 0 1.500 0 1 1 1 1 1.000 0 1 1 1 1 1.475 1 0 0 0 0 0.975 1 0 0 0 0 1.450 1 0 0 0 1 0.950 1 0 0 0 1 1.425 1 0 0 1 0 0.925 1 0 0 1 0 1.400 1 0 0 1 1 0.900 1 0 0 1 1 1.375 1 0 1 0 0 0.875 1 0 1 0 0 1.350 1 0 1 0 1 0.850 1 0 1 0 1 1.325 1 0 1 1 0 0.825 1 0 1 1 0 1.300 1 0 1 1 1 0.800 1 0 1 1 1 1.275 1 1 0 0 0 0.775 1 1 0 0 0 1.250 1 1 0 0 1 0.750 1 1 0 0 1 1.225 1 1 0 1 0 0.725 1 1 0 1 0 1.200 1 1 0 1 1 0.700 1 1 0 1 1 1.175 1 1 1 0 0 0.675 1 1 1 0 0 1.150 1 1 1 0 1 0.650 1 1 1 0 1 1.125 1 1 1 1 0 0.625 1 1 1 1 0 1.100 1 1 1 1 1 0.600 1 1 1 1 1 Shutdown for an additional 24 clock cycles after the controller reaches the final DAC code value. UVP can be disabled through the “no-fault” test mode (see the No-Fault Test Mode section). D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) Thermal-Fault Protection The MAX1519/MAX1545 feature a thermal fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor activates the fault latch and activates the soft-shutdown sequence. Once the con- ______________________________________________________________________________________ 23 MAX1519/MAX1545 Table 4. Output Voltage VID DAC Codes (SUS = GND) MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies Table 5. Suspend Mode DAC Codes LOWER SUSPEND CODES UPPER SUSPEND CODES SUS* S1 S0 OUTPUT VOLTAGE (V) High GND GND 0.675 REF GND GND 1.075 High GND REF 0.700 REF GND REF 1.100 High GND OPEN 0.725 REF GND OPEN 1.125 High GND VCC 0.750 REF GND VCC 1.150 High REF GND 0.775 REF REF GND 1.175 High REF REF 0.800 REF REF REF 1.200 High REF OPEN 0.825 REF REF OPEN 1.225 High REF VCC 0.850 REF REF VCC 1.250 High OPEN GND 0.875 REF OPEN GND 1.275 High OPEN REF 0.900 REF OPEN REF 1.300 High OPEN OPEN 0.925 REF OPEN OPEN 1.325 High OPEN VCC 0.950 REF OPEN VCC 1.350 High VCC GND 0.975 REF VCC GND 1.375 High VCC REF 1.000 REF VCC REF 1.400 High VCC OPEN 1.025 REF VCC OPEN 1.425 High VCC VCC 1.050 REF VCC VCC 1.450 SUS* S1 S0 OUTPUT VOLTAGE (V) *Connect the three-level SUS input to a 2.7V or greater supply (3.3V or VCC) for an input logic level high. troller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate-driver high, and pulls the DH_ high-side gate-driver low. Toggle SHDN or cycle the VCC power supply below 1V to clear the fault latch and reactivate the controller after the junction temperature cools by 15°C. Thermal shutdown can be disabled through the “no-fault” test mode (see the No-Fault Test Mode section). No-Fault Test Mode The latched-fault protection features and overlap mode can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a “nofault” test mode is provided to disable the fault protection (overvoltage protection, undervoltage protection, and thermal shutdown) and overlap mode. Additionally, the test mode clears the fault latch if it has been set. The nofault test mode is entered by forcing 12V to 15V on SHDN. Multiphase Quick-PWM 5V Bias Supply (VCC and VDD) The Quick-PWM controller requires an external 5V bias supply in addition to the battery. Typically, this 5V bias 24 supply is the notebook’s 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V bias supply can be generated with an external linear regulator. The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW(QG(LOW) + QG(HIGH)) where ICC is provided in the Electrical Characteristics, fSW is the switching frequency, and QG(LOW) and QG(HIGH) are the MOSFET data sheet’s total gate-charge specification limits at V GS = 5V. V+ and V DD can be tied together if the input power source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup. Free-Running, Constant On-Time PWM Controller with Input Feed Forward The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies On-Time One-Shot (TON) The core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFETs on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB): t ON(MAIN) = K (VFB + 0.075V) VIN where K is set by the TON pin-strap connection (Table 6) and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch. The one-shot for the secondary phase varies the on-time in response to the input voltage and the difference between the main and secondary inductor currents. Two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. The summed output is internally connected to CCI, allowing adjustment of the integration time constant with a compensation network connected between CCI and FB. The resulting compensation current and voltage are determined by the following equations: ICCI = GM (VCMP - VCMN ) - GM ( VCSP - VCSN ) VCCI = VFB + ICCI ZCCI Table 6. Approximate K-Factor Errors FREQUENCY SETTING (kHz) K-FACTOR (µs) MAX K-FACTOR ERROR (%) VCC 100 10 ±10 Float 200 5 ±10 REF 300 3.3 ±10 GND 550 1.8 ±12.5 TON CONNECTION where ZCCI is the impedance at the CCI output. The secondary on-time one-shot uses this integrated signal (VCCI) to set the secondary high-side MOSFETs on-time. When the main and secondary current-sense signals (VCM = VCMP - VCMN and VCS = VCSP - VCSM) become unbalanced, the transconductance amplifiers adjust the secondary on-time, which increases or decreases the secondary inductor current until the current-sense signals are properly balanced: V + 0.075V t ON(2ND) = K CCI VIN I Z V + 0.075V + K CCI CCI = K FB VIN VIN = (Main On − Time) + (Secondary Current Balance Correction) This algorithm results in a nearly constant switching frequency and balanced inductor currents, despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-time one-shots have good accuracy at the operating points specified in the Electrical Characteristics. On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wider range. For example, the 300kHz setting typically runs about 3% slower with inputs much greater than 12V due to the very short on-times required. ______________________________________________________________________________________ 25 MAX1519/MAX1545 with input voltage feed forward (Figure 5). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to the input voltage, and directly proportional to the output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot (TON) section). Another one-shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley currentlimit threshold, and the minimum off-time one-shot times out. The controller maintains 180° out-of-phase operation by alternately triggering the main and secondary phases after the error comparator drops below the output voltage set point. MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies BSTS CSN DHS SECONDARY PHASE DRIVERS CSP LXS DLS ILIM Q 19R CMP TRIG Gm ON-TIME ONE-SHOT R CMN CCI MINIMUM OFF-TIME CMP Q CSN TRIG Gm ONE-SHOT CMN FB VCC ON-TIME ONE-SHOT CSP V+ TON REF REF (2.0V) Q TRIG Q T Q SHDN MAIN PHASE DRIVERS R Q GND DHM S LXM S Q CMP CCV R CMN Gm BSTM 1.5mV VDD REF 1.0V DLM SKIP FAULT T PGND T=1 T=0 MAX1519 MAX1545 Gm OFS FB OAIN+ Gm OAIN- R-2R DAC INTERNAL MULTIPLEXERS, MODE CONTROL, AND SLEW-RATE CONTROL S[0:1] D[0:4] SUS SKIP CODE GNDS Figure 5. Dual-Phase Quick-PWM Functional Diagram 26 ______________________________________________________________________________________ TIME Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is: fSW = (VOUT + VDROP1) tON (VIN + VDROP1 - VDROP2 ) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PC board resistances; and tON is the on-time as determined above. Current Balance Without active current-balance circuitry, the current matching between phases depends on the MOSFET’s on-resistance (RDS(ON)), thermal ballasting, on-/off-time matching, and inductance matching. For example, variation in the low-side MOSFET on-resistance (ignoring thermal effects) results in a current mismatch that is proportional to the on-resistance difference: R IMAIN - I2ND = IMAIN 1 - MAIN R2ND However, mismatches between on-times, off-times, and inductor values increase the worst-case current imbalance, making it impossible to passively guarantee accurate current balancing. The multiphase Quick-PWM controller integrates the difference between the current-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. The current balance now relies on the accuracy of the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the lowside MOSFETs. With active current balancing, the current mismatch is determined by the current-sense resistor values and the offset voltage of the transconductance amplifiers: IOS(IBAL) = ILM - ILS = VOS(IBAL) RSENSE where VOS(IBAL) is the current-balance offset specification in the Electrical Characteristics. The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. Feedback Adjustment Amplifiers Voltage-Positioning Amplifier The multiphase Quick-PWM controllers include an independent operational amplifier for adding gain to the voltage-positioning sense path. The voltage-positioning gain allows the use of low-value current-sense resistors in order to minimize power dissipation. This 3MHz gainbandwidth amplifier was designed with low offset voltage (70µV, typ) to meet the IMVP output accuracy requirements. The inverting (OAIN-) and noninverting (OAIN+) inputs are used to differentially sense the voltage across the voltage-positioning sense resistor. The op amp’s output is internally connected to the regulator’s feedback input (FB). The op amp should be configured as a noninverting, differential amplifier, as shown in Figure 10. The voltage-positioning slope is set by properly selecting the feedback resistor connected from FB to OAIN- (see the Setting Voltage Positioning section). For applications using a slave controller, additional differential input resistors (summing configuration) can be connected to the slave’s voltage-positioning sense resistor. Summing together both the master and slave current-sense signals ensures that the voltage-positioning slope remains constant when the slave controller is disabled. The controller also uses the amplifier for remote output sensing (FBS) by summing the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (Figure 10). In applications that do not require voltage-positioning gain, the amplifier can be disabled by connecting the OAIN- pin directly to VCC. The disabled amplifier’s output becomes high impedance, guaranteeing that the unused amplifier does not corrupt the FB input signal. The logic threshold to disable the op amp is approximately VCC - 1V. ______________________________________________________________________________________ 27 MAX1519/MAX1545 On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in the external highside MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forcedPWM operation and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies Table 7. SKIP Settings* SKIP CONNECTION MODE OPERATION High (3.3V or VCC) Two-phase forced-PWM The controller operates with a constant switching frequency, providing low-noise forced-PWM operation. The controller disables the zero-crossing comparators, forcing the low-side gatedrive waveform to constantly be the complement of the high-side gate-drive waveform. REF Two-phase pulse skipping The controller automatically switches over to PFM operation under light loads. The controller keeps both phases active and uses the automatic pulse-skipping control scheme—alternating between the primary and secondary phases with each cycle. GND One-phase pulse skipping The controller automatically switches over to PFM operation under light loads. Only the main phase is active. The secondary phase is disabled—DHS and DLS are pulled low so LXS is high impedance. *Settings for a dual 180° out-of-phase controller. Integrator Amplifier A feedback amplifier forces the DC average of the feedback voltage to equal the VID DAC setting. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 5), allowing accurate DC output voltage regulation regardless of the output ripple voltage. The feedback amplifier has the ability to shift the output voltage. The differential input voltage range is at least ±80mV total, including DC offset and AC ripple. The integration time constant can be set easily with an external compensation capacitor at the CCV pin. Use a capacitor value of 47pF to 1000pF (47pF, typ). Differential Remote Sense The multiphase Quick-PWM controllers include differential remote-sense inputs to eliminate the effects of voltage drops down the PC board traces and through the processor’s power pins. The remote output sense (FBS) is accomplished by summing the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (Figure 10). The controller includes a dedicated input and internal amplifier for the remote ground sense. The GNDS amplifier adds an offset directly to the feedback voltage, adjusting the output voltage to counteract the voltage drop in the ground path. Together, the feedback sense resistor (RFBS) and GNDS input sum the remote-sense voltages with the feedback signals that set the voltage-positioned output, enabling true differential remote sense of the processor voltage. Connect the feedback sense resistor (R FBS ) and ground-sense input (GNDS) directly to the processor’s core supply remote-sense outputs as shown in the Standard Applications Circuit. 28 Offset Amplifier The multiphase Quick-PWM controllers include a third amplifier used to add small offsets to the voltage-positioned load line. The offset amplifier is summed directly with the feedback voltage, making the offset gain independent of the DAC code. This amplifier has the ability to offset the output by ±100mV. The offset is adjusted using resistive voltage-dividers at the OFS input. For inputs from 0 to 0.8V, the offset amplifier adds a negative offset to the output that is equal to 1/8 the voltage appearing at the selected OFS input (VOUT = VDAC - 0.125 × VOFS). For inputs from 1.2V to 2V, the offset amplifier adds a positive offset to the output that is equal to 1/8 the difference between the reference voltage and the voltage appearing at the selected OFS input (VOUT = VDAC + 0.125 × (VREF - VOFS)). With this scheme, the controller supports both positive and negative offsets with a single input. The piecewise linear transfer function is shown in the Typical Operating Characteristics. The regions of the transfer function below zero, above 2V, and between 0.8V and 1.2V are undefined. OFS inputs are disallowed in these regions, and the respective effects on the output are not specified. The controller disables the offset amplifier during suspend mode (SUS = REF or high). Forced-PWM Operation (Normal Mode) During normal mode, when the CPU is actively running (SKIP = high, Table 7), the Quick-PWM controller operates with the low-noise forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate-drive waveform to constantly be the complement of the high-side gatedrive waveform. This keeps the switching frequency fairly constant and allows the inductor current to ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 UNDEFINED REGION ∆i VBATT - VOUT = ∆t L IPEAK 100 INDUCTOR CURRENT OUTPUT OFFSET VOLTAGE (mV) 200 0 -100 0.8 -200 0 0.5 ILOAD = IPEAK/2 1.2 1.0 1.5 0 2.0 ON-TIME TIME OFS VOLTAGE (V) Figure 7. Pulse-Skipping/Discontinuous Crossover Point reverse under light loads, providing fast, accurate negative output voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load 5V bias supply current remains between 10mA to 60mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light load conditions, the processor may switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. Low-Power Pulse Skipping During pulse-skipping override mode (SKIP = REF or GND, Table 7), the multiphase Quick-PWM controllers use an automatic pulse-skipping control scheme. When SKIP is pulled low, the controller uses the automatic pulse-skipping control scheme, overriding forced-PWM operation, and blanks the upper VROK threshold. SKIP is a three-level logic input—GND, REF, or high. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive divider from VCC) or to a logic-level high bias supply (3.3V or greater). When driven to GND, the multiphase Quick-PWM controller disables the secondary phase (DLS = PGND and DHS = LXS) and the primary phase uses the automatic pulse-skipping control scheme. When pulled up to REF, the controller keeps both phases active and uses the automatic pulse-skipping control scheme—alternating between the primary and secondary phases with each cycle. Automatic Pulse-Skipping Switchover In skip mode (SKIP = REF or GND), an inherent automatic switchover to PFM takes place at light loads (Figure 7). A comparator that truncates the low-side IPEAK ILOAD INDUCTOR CURRENT Figure 6. Offset Voltage ILIMIT ILIMIT(VALLEY) = ILOAD(MAX) ( 2 - LIR 2η ) 0 TIME Figure 8. “Valley” Current-Limit Threshold Point switch on-time at the inductor current’s zero crossing affects this switchover. The zero-crossing comparator senses the inductor current across the current-sense resistors. Once V C_P - VC_N drops below the zerocrossing comparator threshold (see the Electrical Characteristics), the comparator forces DL low (Figure 5). This mechanism causes the threshold between pulseskipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 7). For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on ______________________________________________________________________________________ 29 MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (ILOAD(SKIP)) is approximately: CBYP VDD DBST BST K V -V V ILOAD(SKIP) = η TOTAL OUT IN OUT L VIN where ηTOTAL is the number of active phases, and K is the on-time scale factor (Table 6). The switching waveforms may appear noisy and asynchronous when light loading activates the pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Varying the inductor value makes trade-offs between PFM noise and light-load efficiency. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. Current-Limit Circuit The current-limit circuit employs a unique “valley” current-sensing algorithm that uses current-sense resistors between the current-sense inputs (C_P to C_N) as the current-sensing elements. If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle (Figure 8) until the inductor current of the selected phase drops below the valley current-limit threshold. When either phase trips the current limit, both phases are effectively current limited since the interleaved controller does not initiate a cycle with either phase. Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. There is also a negative current limit that prevents excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. When a phase drops below the negative current limit, the controller immediately activates an ontime pulse—DL turns off, and DH turns on—allowing the inductor current to remain above the negative current threshold. 30 (RBST)* INPUT (VIN) CBST DH NH L LX VDD DL NL (CNL)* PGND (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS. Figure 9. Optional Gate-Driver Circuitry The current-limit threshold is adjusted with an external resistive voltage-divider at ILIM. The current-limit threshold voltage adjustment range is from 10mV to 75mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM. The threshold defaults to 30mV when ILIM is connected to VCC. The logic threshold for switchover to the 30mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (C_P, C_N). MOSFET Gate Drivers (DH, DL) The DH and DL drivers are optimized for driving moderately sized, high-side and larger, low-side power MOSFETs. This is consistent with the low-duty factor seen in the notebook CPU environment, where a large VIN - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate in order for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the Quick-PWM controller interprets the MOSFET gate as “off” while there is actually charge still left on the gate. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the device). The dead time at the other edge (DH turning off) is determined by a fixed 35ns internal delay. The internal pulldown transistor that drives DL low is robust, with a 0.4Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive cou- ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies C VGS(TH) < VIN RSS CISS Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Typically, adding a 4700pF between DL and power ground (CNL in Figure 9), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5Ω in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 9). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise. at the trigger input initiate a corresponding on-time pulse (see the On-Time One-Shot section). If the VCC voltage drops below 4.25V, it is assumed that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller activates the shutdown sequence. Multiphase Quick-PWM Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Power-On Reset Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch, activating boot mode, and preparing the PWM for operation. VCC undervoltage lockout (UVLO) circuitry inhibits switching, and forces the DL gate driver high (to enforce output overvoltage protection). When V CC rises above 4.25V, the DAC inputs are sampled and the output voltage begins to slew to the target voltage. For automatic startup, the battery voltage should be present before V CC . If the Quick-PWM controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. Toggle the SHDN pin to reset the fault latch. ILOAD(PHASE) = ILOAD η TOTAL where ηTOTAL is the total number of active phases. • Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. • Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient Input Undervoltage Lockout During startup, the VCC UVLO circuitry forces the DL gate driver high and the DH gate driver low, inhibiting switching until an adequate supply voltage is reached. Once VCC rises above 4.25V, valid transitions detected Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) × 80%. For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: ______________________________________________________________________________________ 31 MAX1519/MAX1545 pling from the drain to the gate of the low-side MOSFETs when LX switches from ground to V IN . Applications with high input voltages and long, inductive DL traces may require additional gate-to-source capacitance to ensure fast-rising LX edges do not pull up the low-side MOSFET’s gate voltage, causing shootthrough currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-to-drain capacitance (C RSS ), gate-to-source capacitance (C ISS C RSS ), and additional board parasitics should not exceed the minimum threshold voltage: MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies response vs. output noise. Low-inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. Inductor Selection The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: VIN − VOUT VOUT L = η TOTAL fSWILOAD(MAX)LIR VIN where ηTOTAL is the total number of phases. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): I LIR IPEAK = LOAD(MAX) 1 + η 2 TOTAL Transient Response The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum offtime. For a dual-phase controller, the worst-case output sag voltage can be determined by: VSAG = V K L(∆ILOAD(MAX))2 OUT + tOFF(MIN) VIN (V − 2VOUT)K 2COUTVOUT IN − 2tOFF(MIN) VIN ∆ILOAD(MAX) VOUTK + + tOFF(MIN) 2COUT VIN where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 6. The amount of overshoot due to stored inductor energy 32 can be calculated as: VSOAR ≈ (∆ILOAD(MAX))2 L 2η TOTAL COUT VOUT where ηTOTAL is the total number of active phases. Setting the Current Limit The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: I LIR ILIMIT(LOW) > LOAD(MAX) 1 − η 2 TOTAL where ηTOTAL is the total number of active phases, and ILIMIT(LOW) equals the minimum current-limit threshold voltage divided by the current-sense resistor (RSENSE). For the 30mV default setting, the minimum current-limit threshold is 28mV. Connect ILIM to VCC for the default current-limit threshold (see the Electrical Characteristics). In adjustable mode, the current-limit threshold is precisely 1/20 the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to GND with ILIM connected to the center tap. When adjusting the current limit, use 1% tolerance resistors with approximately 10µA of divider current to prevent a significant increase of errors in the current-limit tolerance. Output Capacitor Selection The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. In CPU VCORE converters and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR ≤ VSTEP ∆ILOAD(MAX) In non-CPU applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. When operating multiphase systems out-of- ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies RESR ≤ VRIPPLEL (2VIN − ηTOTAL VOUT )t ON − ηTOTAL VOUT t TRIG where ηTOTAL is the total number of active phases, tON is the calculated on-time per phase, and tTRIG is the trigger delay between the master’s DH rising edge and the slave’s DH rising edge. The trigger delay must be less than 1/(fSW × ηTOTAL) for stable operation. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types). When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: fESR ≤ fSW π where: fESR = 1 2πREFF COUT and: REFF = RESR + AVPSRSENSE + RPCB where COUT is the total output capacitance, RESR is the total equivalent-series resistance, RSENSE is the current-sense resistance, AVPS is the voltage-positioning gain, and R PCB is the parasitic board resistance between the output capacitors and sense resistors. For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP capacitors in widespread use at the time of publication have typical ESR zero frequencies below 50kHz. For example, the ESR needed to support a 30mVP-P ripple in a 40A design is 30mV/(40A × 0.3) = 2.5mΩ. Four 330µF/2.5V Panasonic SP (type XR) capacitors in parallel provide 2.5mΩ (max) ESR. Their typical combined ESR results in a zero at 40kHz. Ceramic capacitors have a high ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PC board resistance to ensure stability. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. The efficiency penalty for operating at 550kHz is about 5% when compared to the 300kHz circuit, primarily due to the high-side MOSFET switching losses. Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. ______________________________________________________________________________________ 33 MAX1519/MAX1545 phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. For 3- or 4phase operation, the maximum ESR to meet ripple requirements is: MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The multiphase Quick-PWM controllers operate out-ofphase, while the Quick-PWM slave controllers provide selectable out-of-phase or in-phase on-time triggering. Out-of-phase operation reduces the RMS input current by dividing the input current between several staggered stages. For duty cycles less than 100%/ηOUTPH per phase, the IRMS requirements may be determined by the following equation: ILOAD IRMS = η OUTPH VIN η OUTPH VOUT (VIN − η OUTPH VOUT) where ηOUTPH is the total number of out-of-phase switching regulators. The worst-case RMS current requirement occurs when operating with VIN = 2ηOUTPHVOUT. At this point, the above equation simplifies to IRMS = 0.5 × ILOAD/ηOUTPH. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON™) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than 10°C temperature rise at the RMS input current for optimal circuit longevity. Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderate- sized package (i.e., one or two SO-8s, DPAK, or D2PAK), and is reasonably priced. Ensure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Driver section). MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: 2 V I PD (NH RESISTIVE) = OUT LOAD RDS(ON) VIN η TOTAL where ηTOTAL is the total number of phases. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFETs can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: f I C PD (NH SWITCHING) = (VIN(MAX))2 RSS SW LOAD IGATE η TOTAL where CRSS is the reverse transfer capacitance of NH and IGATE is the peak gate-drive source/sink current (1A, typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C × VIN2 × fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. OS-CON is a trademark of Sanyo. 34 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 CMN CMP MAIN PHASE L1 MAX1519 MAX1545 RSENSE RA RB PC BOARD TRACE RESISTANCE OAIN+ RFBS ERROR COMPARATOR CPU SENSE POINT OAINPC BOARD TRACE RESISTANCE RF FB RA SECOND PHASE L2 RB RSENSE CSP CSN Figure 10. Voltage-Positioning Gain For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage: VOUT ILOAD 2 PD (NL RESISTIVE) = 1 − RDS(ON) VIN(MAX) η TOTAL The worst-case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can “overdesign” the circuit to tolerate: ∆IINDUCTOR ILOAD = η TOTA IVALLEY(MAX) + L 2 LIR I = η TOTALIVALLEY(MAX) + LOAD(MAX) 2 where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 of the load current-per-phase. This diode is optional and can be removed if efficiency is not critical. Boost Capacitors The boost capacitors (CBST) selected must be large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFET’s gates: CBST = N x QGATE 200mV where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET’s data sheet. For example, assume (2) IRF7811W N-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 2 x 24nC = 0.24µF 200mV Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor. ______________________________________________________________________________________ 35 MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies Current-Balance Compensation (CCI) The current-balance compensation capacitor (CCCI) integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (RCCI = 20kΩ) improves transient response by increasing the phase margin. This allows the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the integration time constant, resulting in larger current differences between the phases during transients. Excessively small capacitor values allow the current loop to respond cycle-by-cycle but can result in small DC current variations between the phases. Likewise, excessively large resistor values can also cause DC current variations between the phases. Small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator’s output works well. Connecting the compensation network to the output (VOUT) allows the controller to feed forward the output voltage signal, especially during transients. To reduce noise pickup in applications that have a widely distributed layout, it is sometimes helpful to connect the compensation network to the quiet analog ground rather than VOUT. Setting Voltage Positioning Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the processor’s power dissipation. When the output is loaded, an op amp (Figure 5) increases the signal fed back to the Quick-PWM controller’s feedback input. The adjustable amplification allows the use of standard, current-sense resistor values, and significantly reduces the power dissipated since smaller current-sense resistors can be used. The load-transient response of this control loop is extremely fast, yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor powersupply guidelines. The voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (RSENSE = RCM = RCS) connected between the inductors and output capacitors, as shown in Figure 10. The voltage drop can be determined by the following equation: VVPS = AVPSILOADRSENSE AVPS = η SUM RF η TOTAL RB for voltage-positioning feedback, and ηTOTAL is the total number of active phases. When the slave controller is disabled, the current-sense summation maintains the proper voltage-positioned slope. Select the positive input summing resistors so RFBS = RF and RA = RB. Minimum Input Voltage Requirements and Dropout Performance The nonadjustable minimum off-time one-shot and the number of phases restrict the output voltage adjustable range for continuous-conduction operation. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 6). Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN) as much as it ramps up during the on-time (∆IUP). The ratio h = ∆IUP/∆IDOWN is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V SAG greatly increases unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VFB − VVPS + VDROP1 VIN(MIN) = η OUTPH h x tOFF(MIN) 1 − η OUTPH K + VDROP2 − VDROP1 + VVPS where η OUTPH is the total number of out-of-phase switching regulators, VVPS is the voltage-positioning droop, VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the OnTime One-Shot section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 6. The absolute minimum input voltage is calculated with h = 1. where ηSUM is the number of phases summed together 36 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies KMIN = 3µs for fSW = 300kHz tOFF(MIN) = 400ns VVPS = 3mV/A × 30A = 90mV VDROP1 = VDROP2 = 150mV (30A load) 3) 4) h = 1.5 and ηOUTPH = 2 1.4 V − 90mV + 150mV VIN(MIN) = 2 x 1 − 2 x (0.4 µs x 1.5 / 3.0µs + 150mV − 150mV + 90mV = 4.96V Calculating again with h = 1 gives the absolute limit of dropout: 1.4 V − 90mV + 150mV VIN(MIN) = 2 x 1 − 2 x (0.4 µs x 1.0 / 3.0µs + 150mV − 150mV + 90mV = 4.07V 5) 6) 7) Therefore, VIN must be greater than 4.1V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5V. Applications Information PC Board Layout Guidelines Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all of the power components on the topside of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: 1) 2) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitter-free operation. Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the VCC bypass capacitor, REF and GNDS bypass capacitors, compensation (CC_) components, and the resistive dividers connected to ILIM and OFS. 8) Each slave controller should also have a separate analog ground. Return the appropriate noise-sensitive slave components to this plane. Since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to prevent ground offsets. A low-value (≤10Ω) resistor is sufficient to link the two grounds. Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty. Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents. C_P, C_N, OAIN+, and OAIN- connections for current limiting and voltage positioning must be made using Kelvin-sense connections to guarantee the current-sense accuracy. When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor. Route high-speed switching nodes away from sensitive analog areas (REF, CCV, CCI, FB, C_P, C_N, etc). Make all pin-strap control input connections (SHDN, ILIM, SKIP, SUS, S_, TON) to analog ground or VCC rather than power ground or VDD. Layout Procedure Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas: 1) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). ______________________________________________________________________________________ 37 MAX1519/MAX1545 If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate V SAG to be sure of adequate transient response. Dropout design example: VFB = 1.4V MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies 2) 3) 38 Group the gate-drive components (BST diodes and capacitors, VDD bypass capacitor) together near the controller IC. Make the DC-to-DC controller ground connections as shown in the Standard Application Circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and V DD bypass capacitor go; the master’s analog ground plane, where sensitive analog components, the master’s GND pin, and VCC bypass capacitor go; and the slave’s analog ground plane, where the slave’s GND pin and VCC bypass capacitor go. The master’s GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 4) Connect the output power planes (V CORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close to the CPU as is practical. Chip Information TRANSISTOR COUNT: 11,015 PROCESS: BiCMOS ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies MAX1519/MAX1545 KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT) CPU MAIN PHASE SECONDARY PHASE OUTPUT COUT RSENSE COUT COUT COUT COUT COUT RSENSE INDUCTOR INDUCTOR CIN CIN CIN CIN CIN CIN POWER GROUND INPUT PLACE CONTROLLER ON BACK SIDE WHEN POSSIBLE, USING THE GROUND PLANE TO SHIELD THE IC FROM EMI VIAS TO POWER GROUND CONNECT THE EXPOSED PAD TO ANALOG GND VIAS TO ANALOG GROUND POWER GROUND (2ND LAYER) CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN POWER GROUND (2ND LAYER) Figure 11. PC Board Layout Example ______________________________________________________________________________________ 39 MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies R11 100kΩ C1 2.2µF R10 10Ω C2 1µF POWERGOOD VDD VCC MAX1519 MAX1545 VROK D0 D1 D2 D3 D4 DAC INPUTS GND (DESKTOP P4) SUSPEND INPUTS (FOUR-LEVEL LOGIC) ON OFF U1 CODE S0 S1 SHDN 5V BIAS SUPPLY BST DIODES V+ BSTM INPUT* 7V TO 24V CIN CBST1 0.22µF DHM NH1 TIME CCCV 47pF COUT LXM DLM NL1 PGND R2 1kΩ ±1% GND RTIME 64.9kΩ RSENSE1 1.5mΩ L1 CMN CMP OAIN+ OAIN- R3 1kΩ ±1% R6 3.0kΩ ±1% CCV OUTPUT CREF 0.22µF REF (300kHz) R1 3.0kΩ ±1% TON REF R8 R9 30.1kΩ 100kΩ ±1% ±1% FB ILIM REF C3 100pF R28 182kΩ ±1% CCI CSP CSN CBST2 0.22µF R27 20kΩ ±1% DHS NH2 L2 RSENSE2 1.5mΩ LXS DLS PWM SKIP R5 1kΩ ±1% CIN BSTS OFS STP_CPU# R4 1kΩ ±1% CCCI 470pF COUT NL2 SKIP SUS POWER GROUND GNDS *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. ANALOG GROUND Figure 12a. Standard 4-Phase Desktop P4 Application Circuit (1st and 2nd Phases—MAX1519/MAX1545 Master) 40 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies R12 10Ω DBST3 POL BST OUTPUT COMP CCOMP1 RCOMP1 270pF 20kΩ INPUT* 7V TO 24V CIN V+ D1 1N4148 DH CBST3 0.22µF NH3 RSENSE3 1.5mΩ L3 R17 200kΩ U2 LX MAX1980 DL OUTPUT COUT NL3 ILIM PGND R18 49.9kΩ FLOAT (300kHz) GND TON LIMIT R13 100Ω CS+ C7 1000pF CS- DD TRIG R15 100Ω CM+ DLM (MASTER) SKIP (MASTER) C8 1000pF CONNECT TO MAX1519/MAX1545 (SEE FIGURE 12a) R14 100Ω R16 100Ω CM- CMP C9 100pF CMN REF (MASTER) 5V BIAS SUPPLY VDD VCC C6 0.22µF MAX1519/MAX1545 C5 1µF CONNECT TO MAX1519/MAX1545 (SEE FIGURE 12a) POWER GROUND ANALOG GROUND (MASTER) *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. ANALOG GROUND (SLAVE) Figure 12b. Standard 4-Phase Desktop 4 Application Circuit (3rd Phase—MAX1980 Slave) ______________________________________________________________________________________ 41 C10 1µF R19 10Ω VDD VCC C11 0.22µF DBST4 POL BST OUTPUT COMP CCOMP2 RCOMP2 270pF 20kΩ INPUT* 7V TO 24V CIN V+ D2 1N4148 DH CBST4 0.22µF NH4 RSENSE4 1.5mΩ L4 R24 200kΩ U3 LX MAX1980 DL OUTPUT COUT NL4 ILIM PGND C14 100pF R25 49.9kΩ FLOAT (300kHz) GND TON LIMIT R20 100Ω CS+ C12 1000pF CS- DD TRIG R22 100Ω CM+ DLS (MASTER) SKIP (MASTER) C13 1000pF CONNECT TO MAX1519/MAX1545 (SEE FIGURE 12a) R21 100Ω R23 100Ω CM- CSP REF (MASTER) 5V BIAS SUPPLY CSN MAX1519/MAX1545 Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies CONNECT TO MAX1519/MAX1545 (SEE FIGURE 12a) POWER GROUND ANALOG GROUND (MASTER) *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. ANALOG GROUND (SLAVE) Figure 12c. Standard 4-Phase Desktop 4 Application Circuit (4th Phase—MAX1980 Slave) 42 ______________________________________________________________________________________ Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies QFN THIN 6x6x0.8.EPS D2 D CL D/2 b D2/2 k E/2 E2/2 E (NE-1) X e CL E2 k L e (ND-1) X e CL CL L L e A1 A2 e A PACKAGE OUTLINE 36,40L QFN THIN, 6x6x0.8 mm C 21-0141 COMMON DIMENSIONS 1 2 EXPOSED PAD VARIATIONS D2 E2 PKG. CODES MIN. NOM. MAX. MIN. NOM. MAX. T3666-1 3.60 3.70 3.80 3.60 3.70 3.80 T4066-1 4.00 4.10 4.20 4.00 4.10 4.20 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 36, 40L QFN THIN, 6x6x0.8 mm 21-0141 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 43 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1519/MAX1545 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)