PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 FEATURES • • • Available in the Texas Instruments NanoFree™ Package Low Standby Current Consumption of 1 µA Max I2C to Parallel Port Expander Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5-V Tolerant I/O Ports 400-kHz Fast I2C Bus Input/Output Configuration Register Polarity Inversion Register Internal Power-On Reset • • • • • • • • 1 P1 2 • • DGK PACKAGE (TOP VIEW) D PACKAGE (TOP VIEW) P0 • • No Glitch on Power Up Power-Up With All Channels Configured as Inputs Noise Filter on SCL/SDA Inputs Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 8 7 VCC SDA P2 3 6 SCL GND 4 5 P3 DCU PACKAGE (TOP VIEW) P0 1 8 VCC P1 2 7 SDA P2 3 6 SCL GND 4 5 P3 VCC SDA SCL IO3 1 2 3 4 8 7 6 5 YZP PACKAGE (BOTTOM VIEW) IO0 IO1 IO2 GND GND P2 P1 P0 4 5 3 6 2 7 1 8 P3 SCL SDA VCC See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION ORDERING INFORMATION PACKAGE (1) TA NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) Reel of 3000 Reel of 2500 SOIC – D –40°C to 85°C VSSOP – DCU VSSOP – DGK (1) (2) TOP-SIDE MARKING (2) ORDERABLE PART NUMBER Tube of 75 PCA9536YZPR PCA9536DR PCA9536DRG4 PCA9536D PD536 PCA9536DG4 Reel of 250 PCA9536DT Reel of 3000 PCA9536DCUR Reel of 2500 PREVIEW PCA9536DGKR PCA9536DGKRG4 PREVIEW 7C_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DCU/DGK: The actual top-side marking has one additional character that designates the assembly/test site. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This 4-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The PCA9536 features 4-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs with a weak pullup to VCC. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. If no signals are applied externally to the PCA9536, the voltage level is 1, or high, because of the internal pullup resistors. The data for each input or output is stored in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The system master can reset the PCA9536 in the event of a timeout or other improper operation by utilizing the power-on reset feature, which puts the registers in their default state and initializes the I2C/SMBus state machine. The device's outputs (latched) have high-current drive capability for directly driving LEDs. It has low current consumption. TERMINAL FUNCTIONS NO. 2 NAME DESCRIPTION D, DGK, AND YZP PACKAGE DCU PACKAGE 1 4 P0 P-port input/output. Push-pull design structure. 2 3 P1 P-port input/output. Push-pull design structure. 3 2 P2 P-port input/output. Push-pull design structure. 4 1 GND 5 8 P3 6 7 SCL Serial clock bus. Connect to VCC through a pullup resistor. 7 6 SDA Serial data bus. Connect to VCC through a pullup resistor. 8 5 VCC Supply voltage Ground P-port input/output. Push-pull design structure. Submit Documentation Feedback PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 LOGIC DIAGRAM SCL SDA 6 7 I2C Bus Control Input Filter I/O Port 4 Bits Shift Register P3−P0 Write Pulse Read Pulse VCC GND A. 8 Power-On Reset 4 All I/Os are set to inputs at reset. SIMPLIFIED SCHEMATIC OF P0 TO P3 Data From Shift Register Data From Shift Register Output Port Register Data Configuration Register D VCC Q1 Q FF Write Configuration Pulse Write Pulse CK Q 100 kW D Q FF P0 to P3 CK Q Q2 Output Port Register Input Port Register D Q FF Read Pulse ESD Protection Diode GND Input Port Register Data CK Q Data From Shift Register D Q Polarity Register Data FF Write Polarity Pulse CK Q Polarity Inversion Register A. At power-on reset, all registers return to default values. Submit Documentation Feedback 3 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 I/O Port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pullup (100 kΩ typ) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P Start Condition Stop Condition Figure 1. Definition of Start and Stop Conditions 4 Submit Documentation Feedback PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 2. Bit Transfer Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3. Acknowledgment on the I2C Bus Interface Definition BYTE I2C slave address Px I/O data bus BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) H L L L L L H R/W P3 P2 P1 P0 Does not affect operation of the PCA9536 P7 P6 P5 P4 Device Address Figure 4 shows the address byte of the PCA9536. Slave Address 1 0 0 0 0 0 1 R/W Fixed Figure 4. PCA9536 Address Submit Documentation Feedback 5 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 The slave address equates to 65 (decimal) and 41 (hexadecimal). The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation. Control Register and Command Byte Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9536. Two bits of this data byte state the operation (read or write) and the internal register (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. 0 0 0 0 0 0 B1 B0 Figure 5. Control Register Bits Command Byte CONTROL REGISTER BITS 6 B1 B0 COMMAND BYTE (HEX) 0 0 0x00 0 1 0x01 1 0 0x02 1 1 0x03 PROTOCOL POWER-UP DEFAULT Input Port Read byte 1111 XXXX Output Port Read/write byte 1111 1111 Polarity Inversion Read/write byte 0000 0000 Configuration Read/write byte 1111 1111 REGISTER Submit Documentation Feedback PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 Register Descriptions The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to instruct the I2C device that the Input Port register will be accessed next. Register 0 (Input Port Register) BIT DEFAULT I7 I6 I5 I4 Not Used 1 1 1 1 I3 I2 I1 I0 X X X X The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Register 1 (Output Port Register) BIT DEFAULT O7 O6 O5 O4 Not Used 1 1 1 1 O3 O2 O1 O0 1 1 1 1 The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained. Register 2 (Polarity Inversion Register) BIT DEFAULT N7 N6 N5 N4 Not Used 0 0 0 0 N3 N2 N1 N0 0 0 0 0 The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Register 3 (Configuration Register) BIT DEFAULT C7 C6 C5 C4 Not Used 1 1 1 1 C3 C2 C1 C0 1 1 1 1 Power-On Reset When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9536 in a reset condition until VCC has reached VPOR. At that time, the reset condition is released and the PCA9536 registers and I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle. Submit Documentation Feedback 7 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 Bus Transactions Data is exchanged between the master and PCA9536 through write and read commands. Writes Data is transmitted to the PCA9536 by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission (see Figure 6 and Figure 7). SCL 1 2 3 4 5 6 7 8 9 Slave Address S SDA 1 0 0 0 0 Command Byte 0 1 0 A 0 0 0 0 0 0 Data to Port 0 1 Data 1 A P ACK From Slave ACK From Slave R/W ACK From Slave Start Condition A Write to Port Data Out From Port Data 1 Valid tpv Figure 6. Write to Output Port Register <br/> SCL 1 2 3 4 5 6 7 8 9 Slave Address SDA S 1 0 0 0 Start Condition 0 0 Command Byte 1 0 R/W A 0 0 0 0 ACK From Slave 0 0 Data to Register 1 1 A Data ACK From Slave Data to Register Figure 7. Write to Configuration or Polarity Inversion Registers 8 Submit Documentation Feedback A P ACK From Slave PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 Reads The bus master first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the PCA9536 (see Figure 8 and Figure 9). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. S 1 0 0 0 0 0 ACK From Slave ACK From Slave Slave Address 1 0 Command Byte A A S 1 0 0 0 0 0 1 1 A A Data R/W At this time, the master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter R/W ACK From Master ACK From Data from Register Slave Slave Address Data from Register Data NACK From Master NA P Last Byte Figure 8. Read From Register <br/> 1 SCL 2 3 4 5 6 7 8 9 Data From Port Slave Address SDA S 1 0 Start Condition 0 0 0 0 1 0 R/W Data 1 A Data From Port Data 4 A ACK From Slave ACK From Master NA P NACK From Master Stop Condition Read From Port Data Into Port Data 2 tph Data 3 Data 4 Data 5 tps A. This figure assumes that the command byte previously has been programmed with 00h. B. Transfer of data can be stopped at any moment by a Stop condition. C. This figure eliminates the command byte transfer, a restart, and the slave address call between the initial slave address call and actual data transfer from the P-port (see Figure 8). Figure 9. Read Input Port Register Submit Documentation Feedback 9 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6 V VI Input voltage range (2) –0.5 6 V range (2) VO Output voltage IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IIOK Input/output clamp current VO < 0 or VO > VCC ±20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC –50 mA ICC –0.5 Continuous current through GND –200 Continuous current through VCC 160 D package θJA Package thermal impedance (3) Tstg Storage temperature range (2) (3) V mA 97 DCU package 227 DGK package 172 YZP package (1) 6 UNIT °C/W 102 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions MIN MAX 2.3 5.5 0.7 × VCC 5.5 2 5.5 SCL, SDA –0.5 0.3 × VCC P3–P0 –0.5 0.8 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current P3–P0 –10 mA IOL Low-level output current P3–P0 25 mA TA Operating free-air temperature 85 °C 10 SCL, SDA P3–P0 –40 Submit Documentation Feedback V V V PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input diode clamp voltage II = –18 mA VPOR Power-on reset voltage VI = VCC or GND, IO = 0 IOH = –8 mA P-port high-level output voltage (2) VOH IOH = –10 mA SDA VOL = 0.4 V VOL = 0.5 V IOL P-port (3) VOL = 0.7 V VCC MIN 2.3 V to 5.5 V –1.2 VPOR 2.3 V 1.8 3V 2.6 4.5 V 4.1 4.75 V 4.1 2.3 V 1.7 3V 2.5 TYP (1) MAX 1.5 1.65 UNIT V V V 4.5 V 4 4.75 V 4 2.3 V to 5.5 V 3 10 2.3 V 8 10 3V 8 14 4.5 V 8 17 4.75 V 8 32 2.3 V 10 13 3V 10 19 4.5 V 10 24 4.75 V 10 44 mA II SCL, SDA VI = VCC or GND 2.3 V to 5.5 V ±1 µA IIH P-port VI = VCC 2.3 V to 5.5 V 1 µA IIL P-port VI = GND 2.3 V to 5.5 V –100 µA VI = VCC, IO = 0, I/O = inputs, fscl = 400 kHz Operating mode VI = VCC, IO = 0, I/O = inputs, fscl = 100 kHz ICC VI = GND, IO = 0, I/O = inputs, fscl = 0 kHz Standby mode VI = VCC, IO = 0, I/O = inputs, fscl = 0 kHz ∆ICC CI Cio (1) (2) (3) Additional current in standby mode SCL SDA P-port 5.5 V 73 150 3.6 V 9 50 2.7 V 7 30 5.5 V 14 25 3.6 V 9 20 2.7 V 6 15 5.5 V 225 350 3.6 V 175 250 2.7 V 125 200 5.5 V 0.25 1 3.6 V 0.2 0.9 2.7 V 0.1 0.8 One input at VCC – 0.6 V, Other inputs at VCC or GND 2.3 V to 5.5 V 0.35 Every LED I/O at VI = 4.3 V, fscl = 0 kHz 5.5 V 0.4 µA mA VI = VCC or GND 2.3 V to 5.5 V VIO = VCC or GND 2.3 V to 5.5 V 4 5 5 6.5 7.5 9.5 pF pF All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C. The total current sourced by all I/Os must be limited to 85 mA. Each I/O must be limited externally to a maximum of 25 mA, and the P-port (P3–P0) must be limited to a maximum current of 100 mA. Submit Documentation Feedback 11 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.3 µs tsp I2C tsds I2C serial-data setup time tsdh I2C serial-data hold time ticr I2C input rise time ticf I2C tocf I2C output fall time, 10-pF to 400-pF bus tbuf I2C bus free time between Stop and Start 4.7 1.3 µs tsts I2C Start or repeated Start condition setup time 4.7 0.6 µs tsth I2C Start or repeated Start condition hold time 4 0.6 µs tsps I2C Stop condition setup time 4 0.6 µs spike time 50 100 0 0 Cb I2C bus capacitive load (1) ns ns 20 + 0.1Cb (1) 300 ns 300 20 + 0.1Cb (1) 300 ns 300 20 + 0.1Cb (1) 300 tvd(data) Valid data time, SCL low to SDA output valid tvd(ack) ns 1000 input fall time Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 50 250 kHz ns 1 0.9 µs 1 0.9 µs 400 400 pF Cb = Total capacitive load of one bus in pF Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12) PARAMETER FROM (INPUT) TO (OUTPUT) STANDARD MODE I2C BUS MIN MAX FAST MODE I2C BUS MIN tpv Output data valid SCL P3–P0 tps Input data setup time P-port SCL 100 100 ns tph Input data hold time P-port SCL 1 1 µs 12 Submit Documentation Feedback 200 UNIT MAX 200 ns PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) SUPPLY CURRENT vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE 55 300 70 VCC = 5 V f SCL = 400 kHz I/Os unloaded 35 30 25 VCC = 3.3 V 15 VCC = 2.5 V 10 ICC – Supply Current – µA 40 20 60 250 ICC – Supply Current – nA 45 200 VCC = 3.3 V 150 VCC = 2.5 V 100 50 40 30 20 SCL = VCC 0 -50 -25 0 25 50 75 0 -50 100 -25 TA – Free-Air Temperature – °C 0 25 50 75 0 100 2.3 VOL – Output Low Voltage – mV 225 200 TA = –40°C 150 TA = 25°C 125 100 TA = 85°C 75 50 25 225 200 175 150 VCC = 5 V, ISINK = 10 mA 125 100 75 VCC = 2.5 V, ISINK = 1 mA 50 VCC = 5 V, ISINK = 1 mA 25 0 0 1 2 3 0 -50 4 -25 Number of I/Os Held Low 0 25 50 75 250 5.5 VCC = 2.5 V, IOL = 10 mA 175 150 125 VCC = 5 V, IOL = 10 mA 100 75 50 25 0 -50 100 -25 0 25 50 75 100 TA – Free-Air Temperature – °C I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 60 40 VCC = 3.3 V VCC = 2.5 V 5.1 200 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 30 4.7 225 TA – Free-Air Temperature – °C I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 4.3 275 250 250 3.9 300 VCC = 2.5 V, ISINK = 10 mA (V CC – V OH ) – Output High Voltage – mV 275 3.5 I/O OUTPUT HIGH VOLTAGE vs TEMPERATURE 300 VCC = 5 V 175 3.1 VCC – Supply Voltage – V I/O OUTPUT LOW VOLTAGE vs TEMPERATURE 300 275 2.7 TA – Free-Air Temperature – °C SUPPLY CURRENT vs NUMBER OF I/Os HELD LOW VCC = 5 V 55 35 25 ISINK – I/O Sink Current – mA TA = –40°C 20 TA = 25°C 15 TA = 85°C 10 5 50 TA = –40°C ISINK – I/O Sink Current – mA ICC – Supply Current – µA 50 10 5 ISINK – I/O Sink Current – mA f SCL = 400 kHz I/Os unloaded VCC = 5 V 50 ICC – Supply Current – µA SUPPLY CURRENT vs SUPPLY VOLTAGE 30 TA = 25°C 25 20 15 TA = 85°C 10 45 TA = –40°C 40 35 TA = 25°C 30 25 20 TA = 85°C 15 10 5 5 0 0 0.0 0.1 0.2 0.3 0.4 0.5 VOL – Output Low Voltage – V 0.6 0.7 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 VOL – Output Low Voltage – V Submit Documentation Feedback 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VOL – Output Low Voltage – V 13 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 30 70 45 VCC = 3.3 V VCC = 2.5 V 20 TA = 25°C 15 TA = 85°C 10 5 0 TA = –40°C ISOURCE – I/O Source Current – mA TA = –40°C 35 30 TA = 25°C 25 20 15 10 TA = 85°C 5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.1 0.2 0.3 0.4 0.5 0.6 0.7 50 TA = –40°C 45 40 35 TA = 25°C 30 25 TA = 85°C 20 15 10 OUTPUT HIGH VOLTAGE vs SUPPLY VOLTAGE 6 TA = 25°C 5 4 IOH = –8 mA 3 IOH = –10 mA 2 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VCC – Supply Voltage – V Submit Documentation Feedback 0.0 0.1 0.2 0.3 0.4 0.5 0.6 (VCC – VOH) – Output High Voltage – V (VCC – VOH) – Output High Voltage – V VOH – Output High Voltage – V 55 0 0.0 (VCC – VOH) – Output High Voltage – V 14 60 5 0 0.0 VCC = 5 V 65 40 25 ISOURCE – I/O Source Current – mA ISOURCE – I/O Source Current – mA I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 5.5 0.7 PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr tsts tPHL ticf tbuf tPLH tsp 0.7 × VCC SDA 0.3 × VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2, 3 P-port data A. CL include probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 10. I2C Interface Load Circuit and Voltage Waveforms Submit Documentation Feedback 15 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.7 kΩ INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 1 0 0 0 0 0 1 1 A 1 2 3 4 5 6 7 8 A Data 1 ACK From Slave Data From Port A Data 2 1 A tir tir B B INT A tiv tsps A Data Into Port Address Data 1 0.7 × VCC INT 0.3 × VCC SCL Data 2 0.7 × VCC R/W tiv A 0.3 × VCC tir 0.7 × VCC Pn 0.7 × VCC INT 0.3 × VCC 0.3 × VCC View A−A View B−B A. CL include probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 11. Interrupt Load Circuit and Voltage Waveforms 16 Submit Documentation Feedback P PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) Pn 500 W DUT CL = 50 pF (see Note A) 2 × VCC 500 W P-PORT LOAD CONFIGURATION SCL 0.7 × VCC P0 A P3 0.3 × VCC Slave ACK ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) SCL 0.7 × VCC P0 A tps P3 0.3 × VCC tph 0.7 × VCC Pn 0.3 × VCC READ MODE (R/W = 1) A. CL include probe and jig capacitance. B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 12. P-Port Load Circuit and Voltage Waveforms Submit Documentation Feedback 17 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) VCC Pn RL = 1 kΩ DUT 500 W 2 × VCC DUT SDA CL = 50 pF (see Note A) 500 W CL = 50 pF (see Note A) P-PORT LOAD CONFIGURATION SDA LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw Px (see Note D) VCC/2 tRESET A. CL include probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 13. Reset Load Circuits and Voltage Waveforms 18 Submit Documentation Feedback PCA9536 REMOTE 4-BIT AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS I2C www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 APPLICATION INFORMATION Figure 14 shows an application in which the PCA9536 can be used. VCC 10 kW VCC 2 kW 10 kW VCC SCL SCL Master SDA Controller SDA P0 Subsystem 1 (e.g., temperature sensor) P1 INT P2 PCA9536 GND RESET P3 Subsystem 2 (e.g., counter) A GND Controlled Device (e.g., CBT device) ENABLE B A. Device address is 10000001. B. P0, P2, and P3 are configured as outputs. C. P1 is configured as an input. Figure 14. Typical Application Submit Documentation Feedback 19 PCA9536 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS www.ti.com SCPS125C – APRIL 2006 – REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) Minimizing ICC When I/Os Control LEDs When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown in Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The supply current, ICC, increases as VIN becomes lower than VCC and is specified as ∆ICC in Electrical Characteristics. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VCC when the LED is off. Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional supply-current consumption when the LED is off. VCC LED 100 kW VCC Pn Figure 15. High-Value Resistor in Parallel With the LED 3.3 V VCC 5V LED Pn Figure 16. Device Supplied by a Lower Voltage 20 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCA9536D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9536DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9536DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9536DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9536DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9536DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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