ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 11.3-GBPS DIFFERENTIAL VCSEL DRIVER FEATURES APPLICATIONS • • • • • • • • • • • • • • Up to 11.3-Gbps Operation Two-Wire Digital Interface Digitally Selectable Modulation Current up to 40 mA Digitally Selectable Bias Current up to 20 mA Automatic Power Control (APC) Loop Supports Transceiver Management System (TMS) Programmable Input Equalizer Includes Laser Safety Features Analog Temperature Sensor Output Single 3.3-V Supply Operating Temperature –40°C to 85°C Surface-Mount, Small-Footprint, 4-mm × 4-mm, 20-Pin QFN Package • • • 10-Gigabit Ethernet Optical Transmitters 8× and 10× Fibre Channel Optical Transmitters SONET OC-192/SDH STM-64 Optical Transmitters XFP and SFP+ Transceiver Modules XENPAK, XPAK, X2, and 300-Pin MSA Transponder Modules DESCRIPTION The ONET1191V is a high-speed, 3.3-V laser driver designed to directly modulate VCSELs at data rates up to 11.3 Gbps. The device provides a two-wire serial interface which allows digital control of the modulation and bias currents, eliminating the need for external components. An optional input equalizer can be used for equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed-circuit boards. The ONET1191V includes an integrated automatic power control (APC) loop as well as circuitry to support laser safety and transceiver management systems. The VCSEL driver is characterized for operation from –40°C to 85°C ambient temperatures and is available in a small-footprint, 4-mm × 4-mm, 20-pin QFN package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. BLOCK DIAGRAM A simplified block diagram of the ONET1191V is shown in Figure 1. The VCSEL driver consists of an equalizer, a high-speed current modulator, a modulation current generator, power-on reset circuitry, a two-wire interface and control logic block, a bias current generator and automatic power control loop, and an analog reference block. 2 VCC 2 GND 55 W GND 55 W VCC MOD+ Power-On Reset MOD– RESET DIN+ Limiting Gain Stage High-Speed Current Modulator Equalizer 100 W DIN– EQENB EQADJ 8 MODC 8 MODR ENA 8 EQENB EQADJ RESET SCK SCK SDA SDA DIS DIS MODC MODR IMOD Modulation Current Generator ENA 2-Wire Interface and Control Logic Clock ENA OLE BIASC PDP FAULT PDP FAULT FLT FLT BIAS BIAS 8 Analog Reference RZTC RZTC BGV BGV TS TS ENA OLE BIASC Bias Current Generator and Automatic Power Control (APC) Loop MONB MONB MONP MONP PD COMP PD COMP B0072-02 Figure 1. Simplified Block Diagram of the ONET1191V 2 Submit Documentation Feedback ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 EQUALIZER The data signal can be applied to an input equalizer by means of the input signal pins DIN+/DIN–, which provide on-chip differential 100-Ω line termination. The equalizer is enabled by setting EQENB = 0 (bit 1 of register 0). Equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of equalization is digitally controlled by the two-wire interface and control logic block and depends on the register settings EQADJ[0..7] (register 3). The equalizer can also be turned off and bypassed by setting EQENB = 1. For details about the equalizer settings, see Table 6. HIGH-SPEED CURRENT MODULATOR The output of the equalizer is applied to the high-speed current modulator. The limiting gain stage ensures sufficient drive amplitude and edge speed for driving the current modulator differential pair. The modulation current is sunk from the common-emitter node of the named differential pair by means of a modulation current generator, which is digitally controlled by the two-wire interface and control logic block. The collector nodes of the differential pair are connected to the output pins MOD+/MOD–, which include on-chip 2 × 55-Ω back-termination to VCC. The 55-Ω back-termination helps to suppress signal distortion caused by double reflections for VCSEL diodes with impedances from 50 Ω through 75 Ω. MODULATION CURRENT GENERATOR The modulation current generator provides the current for the current modulator described previously. The circuit is digitally controlled by the two-wire interface and control logic block. An 8-bit-wide control bus, MODC, is used to set the desired modulation current. Furthermore, two modulation current ranges are selected by means of the MODR signal. The ENA signal enables or disables the modulation current generator. The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current is also disabled in a fault condition if the fault detection enable register flag FLTEN is set. For more information about the register functionality, see the register mapping description in Table 6. TWO-WIRE INTERFACE AND CONTROL LOGIC The ONET1191V uses a two-wire serial interface for digital control. A simplified block diagram of this interface is shown in Figure 2. The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include 100-kΩ pullup resistors to VCC. For driving these inputs, an open-drain output is recommended. A write cycle consists of a START command, three address bits with MSB first, 8 data bits with MSB first, and a STOP command. In idle mode, both the SDA and SCK lines are at a high level. A START command is initiated by the falling edge of SDA with SCK at a high level, transitioning to a low level. Bits are clocked into an 11-bit-wide shift register during the high level of the serial clock, SCK. A STOP command is detected on the rising edge of SDA after SCK has changed from a low to a high level. At the time of detection of a STOP command, the eight data bits from the shift register are copied to a selected 8-bit register. Register selection occurs according to the three address bits in the shift register, which are decoded to eight independent select signals using an 3-to-8 decoder block. In the ONET1191V, addresses 0 (000b) through 3 (011b) are used. Submit Documentation Feedback 3 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 SDA 11-Bit Shift Register SCK 8 Bits Data 3 Bits Addr 3 8 8 Start 000 001 Stop 010 8 8-Bit Register Modulation Current (8 Bits) 011 100 3-to-8 Decoder Start/Stop Detector Logic 8-Bit Register Control Functions (7 Bits) Unused (1 Bit) 101 110 8 111 8-Bit Register Bias Current (8 Bits) 8 8-Bit Register Equalizer Setting (8 Bits) B0068-03 Figure 2. Simplified Two-Wire Interface Block Diagram The timing definition for the serial data signal SDA and the serial clock signal SCK is shown in Figure 3. The corresponding timing requirements are listed in Table 1. 4 Submit Documentation Feedback ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 START 1 0 1 0 1 1 STOP DTAF DTAR DTAHI DTAWT SDA SCK STRTHLD DTASTP CLKR DTAHLD CLKF STOPSTP CLKHI T0077-01 Figure 3. Two-Wire Interface Timing Diagram Table 1. Two-Wire Interface Timing PARAMETER DESCRIPTION MIN MAX UNIT STRTHLD START hold time Time required from data falling edge to clock falling edge at START 10 CLKR, DTAR Clock and data rise time Clock and data rise time ns CLKF, DTAF Clock and data fall time Clock and data fall time CLKHI Clock high time Minimum clock high period 50 ns DTAHI Data high time Minimum data high period 100 ns DTASTP Data setup time Minimum time from data rising edge to clock rising edge 10 ns DTAWT Data wait time Minimum time from data falling edge to data rising edge 50 ns DTAHLD Data hold time Minimum time from clock falling edge to data falling edge 10 ns STOPSTP STOP setup time Minimum time from clock rising edge to data rising edge at STOP 10 ns 10 ns 10 ns REGISTER MAPPING The register mapping for the register addresses 0 (000b) through 3 (011b) are shown in Table 2 through Table 5. Table 6 describes the circuit functionality based on the register settings. Table 2. Register 0 (000b) Mapping address 0 (000b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ENA PDP PDR OLE FLTEN MODR EQENB – Table 3. Register 1 (001b) Mapping address 1 (001b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 MODC7 MODC6 MODC5 MODC4 MODC3 MODC2 MODC1 MODC0 Submit Documentation Feedback 5 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 Table 4. Register 2 (010b) Mapping address 2 (010b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BIASC7 BIASC6 BIASC5 BIASC4 BIASC3 BIASC2 BIASC1 BIASC0 Table 5. Register 3 (011b) Mapping address 3 (011b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EQADJ7 EQADJ6 EQADJ5 EQADJ4 EQADJ3 EQADJ2 EQADJ1 EQADJ0 Table 6. Register Functionality SYMBOL 6 REGISTER FUNCTION ENA Enable Enables chip when set to 1. Can be toggled low to reset a fault condition. PDP Photodiode polarity Photodiode polarity bit: 1 = photodiode cathode connected to VCC 0 = photodiode anode connected to GND PDR Photodiode current range Photodiode current range bit: With coupling ratio CR between VCSEL bias current and photodiode current = 30 1 = 12 µA–640 µA with 2.5 µA resolution 0 = 2.5 µA–12 8µA with 0.5µA resolution OLE Open loop enable Open-loop enable bit: 1 = open-loop bias current control 0 = closed-loop bias current control FLTEN Fault detection enable Fault detection enable bit: 1 = fault detection on 0 = fault detection off MODR Modulation tail current range Laser modulation tail current range: 1 = 0 mA–40 mA 0 = 0 mA–20 mA EQENB Equalizer enable Equalizer enable bit 1 = equalizer disabled 0 = equalizer enabled MODC7 Modulation current bit 7 (MSB) Modulation current setting: MODC6 Modulation current bit 6 MODC5 Modulation current bit 5 MODR = 1: MODC4 Modulation current bit 4 Modulation current up to 40 mA in 156-µA steps MODC3 Modulation current bit 3 MODC2 Modulation current bit 2 MODR = 0: MODC1 Modulation current bit 1 Modulation current up to 20 mA in 78-µA steps MODC0 Modulation current bit 0 (LSB) BIASC7 Bias current bit 7 (MSB) Closed loop (APC): BIASC6 Bias current bit 6 Coupling ratio CR = IBIAS-VCSEL/IPD BIASC5 Bias current bit 5 PDR = 0, BIASC = 0..255, IBIAS-VCSEL ≤ 20 mA: BIASC4 Bias current bit 4 BIASC3 Bias current bit 3 BIASC2 Bias current bit 2 BIASC1 Bias current bit 1 BIASC0 Bias current bit 0 (LSB) Open loop: IBIAS-VCSEL = 75 µA × BIASC EQADJ7 Equalizer adjustment bit 7 (MSB) Equalizer adjustment setting EQADJ6 Equalizer adjustment bit 6 EQADJ5 Equalizer adjustment bit 5 EQENB = 1 EQADJ4 Equalizer adjustment bit 4 Equalizer is turned off and bypassed EQADJ3 Equalizer adjustment bit 3 IBIAS-VCSEL = 0.5 µA × CR × BIASC PDR = 1, BIASC = 0..255, IBIAS-VCSEL ≤ 20 mA: IBIAS-VCSEL = 2.5 µA × CR × BIASC Submit Documentation Feedback ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 Table 6. Register Functionality (continued) SYMBOL REGISTER FUNCTION EQADJ2 Equalizer adjustment bit 2 EQENB = 0 EQADJ1 Equalizer adjustment bit 1 Maximum equalization for 0000 0000 EQADJ0 Equalizer adjustment bit 0 (LSB) Minimum equalization for 1111 1111 BIAS CURRENT GENERATION AND APC LOOP The bias current generation and APC loop are controlled by means of the two-wire interface. In open-loop operation, selected by setting OLE = 1 (bit 4 of register 0), the bias current is set directly by the 8-bit-wide control word BIASC[0..7] (register 2). In automatic power control mode, selected by setting OLE = 0, the bias current depends on the register settings BIASC[0..7] and the coupling ratio (CR) between the VCSEL bias current and the photodiode current. CR = IBIAS-VCSEL/IPD. Two photodiode current ranges can be selected by means of the PDR register (bit 5 of register 0). The photodiode range should be chosen to keep the laser bias control DAC close to the center of its range. This keeps the laser bias current setpoint resolution high and the loop settling time constant within specification. For details regarding the bias current setting in open- as well as in closed-loop mode, see Table 6. In closed-loop mode, the photodiode polarity bit, PDP, must be set for common-anode or common-cathode configuration to ensure proper operation. In open-loop mode, if a photodiode is present, the photodiode polarity bit must be set to the opposite setting. ANALOG REFERENCE The ONET1191V VCSEL driver is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins. This voltage is referred to ground (GND). On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which all other internally required voltages and bias currents are derived. An external zero-temperature-coefficient resistor must be connected from the RZTC pin of the device to ground (GND). This resistor is used to generate a precise, zero-TC current, which is required as a reference current for the on-chip DACs. In order to minimize the module component count, the ONET1191V provides an on-chip temperature sensor. The output voltage of the temperature sensor is available at the TS pin. The voltage is VTS = (8.2 mV/°C × TEMP) + 1140 mV, with TEMP given in °C. Note that the voltage at TS is not buffered. As a result, TS can only drive capacitive loads. POWER-ON RESET AND REGISTER LOADING SEQUENCE The ONET1191V has power-on-reset circuitry, which ensures that all registers are reset to zero during startup. After the power-on to initialize time (tINIT1), the internal registers are ready to be loaded. It is important that the registers are loaded in the following order: 1. Bias current register (register 2, 010b) 2. Modulation current register (register 1, 001b) 3. Control register (register 0, 000b) 4. Loading of equalizer register (register 3, 011b) is not required. The part is ready to transmit data after the initialize to transmit time tINIT2, assuming that the control register enable bit ENA is set to 1 and the disable pin DIS is low. The ONET1191V can be disabled using either the ENA control register bit or the disable pin DIS. In both cases, the internal registers are not reset. After the disable pin DIS is set low and/or the enable bit ENA is set back to 1, the part returns to its prior output settings. Submit Documentation Feedback 7 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE The ONET1191V provides built-in laser safety features. The following fault conditions are detected: • Voltage at MONB exceeds the voltage at RZTC (1.15V). • Photodiode current exceeds 150% of its set value. • Bias control DAC drops in value by more than 50% in one step. If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET1191V responds by: • Setting the VCSEL bias current to zero • Setting the modulation current to zero • Asserting and latching the FLT pin Fault recovery is performed by the following procedure: 1. The disable pin DIS and/or the enable control bit ENA are toggled for at least the fault latch reset time tRESET. 2. The FLT pin deasserts while the disable pin DIS is asserted or the enable bit ENA is deasserted. 3. If the fault condition is no longer present, the part returns to normal operation with its prior output settings after the disable negate time tON. 4. If the fault condition is still present, FLT reasserts once DIS is set to a low level, and the part does not return to normal operation. PACKAGE The ONET1191V is packaged in a small-footprint, 4-mm × 4-mm, 20-pin QFN package with a lead pitch of 0,5 mm. The pinout is shown in Figure 4. MOD+ MOD– VCC 20 19 18 17 16 BIAS VCC RGP PACKAGE (TOP VIEW) DIS 1 RZTC 15 PD 14 COMP 2 TS 3 13 MONP EP 6 7 8 9 10 GND FLT 11 BGV DIN– SDA 5 DIN+ 12 MONB GND SCK 4 P0031-04 Figure 4. Pinout of ONET1191V in a 4-mm × 4-mm, 20-Pin QFN Package 8 Submit Documentation Feedback ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION Buffered bandgap voltage with open emitter output. This is a replica of the bandgap voltage at RZTC. For best matching, use the same 28.7-kΩ resistor to GND as used at RZTC. BGV 11 Anolog-out BIAS 16 Analog Sinks average bias current for VCSEL in both APC and open-loop modes. Connect to laser cathode through an inductor. BLM15HG102SN1D recommended. COMP 14 Analog Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF capacitor to ground. DIN+ 7 Analog-in Noninverted data input. On-chip differentially 100-Ω terminated to DIN–. Must be ac-coupled. DIN– 8 Analog-in Inverted data input. On-chip differentially 100-Ω terminated to DIN+. Must be ac-coupled. DIS 1 Digital-in Disables both bias and modulation currents when set to high state. Toggle to reset a fault condition. FLT 10 Digital-out GND Fault detection flag. 6, 9, EP Supply MOD+ 19 CML-out Noninverted modulation current output. On-chip, 55-Ω back-terminated to VCC. MOD– 18 CML-out Inverted modulation current output. On-chip, 55-Ω back-terminated to VCC. MONB 12 Analog-out Bias current monitor. Sources a 3.3% replica of the bias current. Connect an external resistor to ground (GND). If the voltage at this pin exceeds 1.15 V, a fault is triggered. Typically, choose a resistor to give MONB voltage of 0.8 V at the maximum desired bias current. MONP 13 Analog-out Photodiode current monitor. Sources a 50% replica of the photodiode current when PDR = 1 and a 250% replica when PDR = 0. Connect an external resistor (5 kΩ typical) to ground (GND). PD 15 Analog Photodiode input. Pin can source or sink current dependent on PDP register setting. PDP = 0: source; PDP = 1: sink. Pin supplies >1.5-V reverse bias. RZTC 2 Analog Connect external zero-TC, 28.7-kΩ resistor to ground (GND). Used to generate a defined zero-TC reference current for internal DACs. SCK 4 Digital-in Two-wire interface serial clock. Includes a 100-kΩ pullup resistor to VCC. SDA 5 Digital-in Two-wire interface serial data input. Includes a 100-kΩ pullup resistor to VCC. 3 Analog-out 17, 20 Supply TS VCC Circuit ground. Exposed die pad (EP) must be grounded. Temperature sensor output. Not buffered, capacitive load only. 3.3-V ±10% supply voltage ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltage (2) VCC VDIS, VRZTC, VTS, VSCK, VSDA, Voltage at DIS, RZTC, TS, SCK, SDA, DIN+, DIN–, FLT, BGV, MONB, VDIN+, VDIN–, VFLT, VBGV, VMONB, MONP, CAPC, PD, BIAS, MOD+, MOD– (2) VMONP, VCAPC, VPD, VBIAS, VMOD+, VMOD– VALUE UNIT –0.3 to 4 V –0.3 to 4 V 2 kV (HBM) ESD ESD rating at all pins TJ,max Maximum junction temperature 125 °C Tstg Storage temperature range –65 to 85 °C TA Characterized free-air operating temperature range –40 to 85 °C TLEAD Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Submit Documentation Feedback 9 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 RECOMMENDED OPERATING CONDITIONS VCC Supply voltage VIH Digital input high voltage DIS, SCK, SDA VIL Digital input low voltage DIS, SCK, SDA Bias output headroom voltage VBIAS – GND Photodiode current range RRZTC Zero-TC resistor value (1) MAX 2.9 3.3 3.6 2 300 Control bit PDR = 0 step size = 0.5 µA 2.5 128 1.15-V bandgap bias across resistor 28.4 Control bit EQENA = 1 200 1200 Control bit EQENA = 0 500 1200 Input rise time 20%–80% tF-IN Input fall time 20%–80% TA Operating free-air temperature –40 Changing the value alters the DAC ranges. Submit Documentation Feedback V V mV 640 tR-IN UNIT V 0.8 12 Differential input voltage swing 10 NOM Control bit PDR = 1, step size = 2.5 µA VIN (1) MIN 28.7 29 µA kΩ mVp-p 30 55 ps 30 55 ps 85 °C ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions; all values are for open-loop operation, IMODC = 12 mA, IBIASC = 6 mA, and RRZTC = 28.7 kΩ (unless otherwise noted) PARAMETER VCC TEST CONDITIONS MIN TYP MAX 2.9 3.3 3.6 IMODC = 24mA, IBIASC = 6 mA, including IMODC and IBIASC, EQENB = 1 62 71 IMODC = 24mA, IBIASC = 6mA, including IMODC and IBIASC, EQENB = 0 70 Disabled, DIS = high and/or control bit ENA = low, EQENB = 1 35 42 Supply voltage IVCC Supply current UNIT V mA Ω RIN Data input resistance Differential between DIN+/DIN– 85 100 125 ROUT Data output resistance Single-ended to VCC 45 55 65 Ω Digital input current SCK, SDA, 100-kΩ pullup to VCC (1) –50 10 µA DIS (1) –10 10 µA 2.4 VOH Digital output high voltage FLT, ISOURCE = 500 µA VOL Digital output low voltage FLT, ISINK = 500 µA IBIAS-DIS Bias current during disable IBIAS-MIN Minimum bias current See IBIAS-MAX Maximum bias current DAC set to maximum, open- and closed-loop 14 20 mA VPD Photodiode reverse bias voltage APC active, IPD = max 1.5 2.3 V V 0.4 (2) Photodiode fault current level, percent of target IPD (1) 100 µA 0.2 mA 150% Temperature sensor voltage range –40°C to 120°C junction temperature, capacitive load only, with midscale calibration. (1) Temperature sensor accuracy With midscale calibration (1) Temperature sensor drive current Source or sink (1) Photodiode current monitor ratio IMONP/IPD with control bit PDR = 1 40% 50% 60% IMONP/IPD with control bit PDR = 0 200% 265% 300% Bias current monitor ratio IMONB/IBIAS (nominal 1/30 = 3.3%). 1.2-kΩ sense resistor 2.7% 3.3% 4% VCC-RST VCC reset threshold voltage VCC voltage level which triggers power-on reset (1) 2.4 2.5 2.8 VCC-RSTHYS VCC reset threshold voltage hysteresis VMONB-FLT Fault voltage at MONB VTS ITS (1) (2) V 0.5 2.5 ±3 –1 Fault occurs if voltage at MONB exceeds value 1.05 °C 1 100 (1) 1.15 V µA V mV 1.25 V Assured by simulation over process, supply, and temperature variation The bias current can be set below the specified minimum according to the corresponding register setting described in the register mapping section. However, in closed-loop operation, settings below the specified value may trigger a fault. Submit Documentation Feedback 11 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 AC ELECTRICAL CHARACTERISTICS Over recommended operating conditions with 50-Ω output load, open-loop operation, IMODC = 12 mA, IBIASC = 6 mA, and RRZTC = 28.7 kΩ, unless otherwise noted. Typical operating condition is at VCC = 3.3 V and TA = 25°C. TYP MAX tr-OUT Output rise time PARAMETER 20%–80%, tr-IN < 40 ps, 50-Ω load 20 30 ps tf-OUT Output fall time 20%–80%, tf-IN < 40 ps, 50-Ω load 25 30 ps IMOD-MAX TEST CONDITIONS Maximum modulation current IMOD-STEP Modulation current step size MIN Control bit MODR = 1, 50-Ω load 36 45 Control bit MODR = 0, 50-Ω load 18 27 Control bit MODR = 1, 50-Ω load 175 Control bit MODR = 0, 50-Ω load 100 UNIT mA µA Control bit EQENB = 1, K28.5 pattern at 11.3 Gbps 4 12 DJ Deterministic output jitter Control bit EQENB = 0, K28.5 pattern at 11.3 Gbps, maximum equalization with 300-mm FR4 trace 10 20 psp-p RJ Random output jitter 50-Ω load 0.5 0.8 psRMS τAPC APC time constant CAPC = 0.01 µF, IPD = 100 µA, PD coupling ratio CR = 40 (1) 200 tOFF Transmitter disable time Rising edge of DIS to IBIAS ≤ 0.1 × IBIAS-NOMINAL tON Disable negate time Falling edge of DIS to IBIAS ≥ 0.9 × IBIAS-NOMINAL (1) tINIT1 Power-on to initialize Power-on to registers ready to be loaded tINIT2 Initialize to transmit Register load STOP command to part ready to transmit valid data (1) tRESET DIS pulse duration Time DIS must held high to reset part (1) tFAULT Fault assert time Time from fault condition to FLT high (1) (1) (1) µs 5 µs 1 ms 10 ms 2 ms 50 µs 1 1 100 ns Assured by simulation over process, supply, and temperature variation TYPICAL CHARACTERISTICS Typical operating condition is at VCC = 3.3 V, TA = 25°C, IBIASC = 6 mA, IMODC = 12 mA, MODR = 0 (unless otherwise noted). DETERMINISTIC JITTER vs TEMPERATURE 8 8 6 6 Deterministic Jitter − psPP Deterministic Jitter − psPP DETERMINISTIC JITTER vs MODULATION CURRENT 4 2 0 5 10 15 20 4 2 0 −40 Modulation Current − mA G001 Figure 5. 12 −20 0 20 40 Figure 6. Submit Documentation Feedback 60 TA − Free-Air Temperature − °C 80 100 G002 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3 V, TA = 25°C, IBIASC = 6 mA, IMODC = 12 mA, MODR = 0 (unless otherwise noted). RANDOM JITTER vs TEMPERATURE 0.5 0.5 0.4 0.4 Random Jitter − psrms Random Jitter − psrms RANDOM JITTER vs MODULATION CURRENT 0.3 0.2 0.3 0.2 0.1 0.1 0.0 −40 0.0 5 10 15 20 25 30 −20 G003 40 60 80 Figure 8. RISE TIME AND FALL TIME vs MODULATION CURRENT BIAS CURRENT IN OPEN-LOOP MODE vs BIASC REGISTER SETTING 35 14 30 12 Fall Time 20 Rise Time 15 10 5 100 G004 Figure 7. Open-Loop Bias Current − mA tt − Transition Time − ps 20 TA − Free-Air Temperature − °C Modulation Current − mA 25 0 10 8 6 4 2 0 0 5 10 15 20 25 30 0 Modulation Current − mA G005 Figure 9. 2 4 6 8 10 12 14 16 Bias Current Register Setting − mA G006 Figure 10. Submit Documentation Feedback 13 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3 V, TA = 25°C, IBIASC = 6 mA, IMODC = 12 mA, MODR = 0 (unless otherwise noted). BIAS-MONITOR CURRENT IMONB vs BIAS CURRENT MODULATION CURRENT vs MODC REGISTER SETTING, MODR = 1 0.6 50 40 Modulation Current − mA IMONB − Bias-Monitor Current − mA 45 0.5 0.4 0.3 0.2 35 30 25 20 15 10 0.1 5 0.0 0 0 2 4 6 8 10 12 14 5 Bias Current − mA 10 15 20 25 30 35 40 Modulation Current Register Setting − mA G016 Figure 11. Figure 12. SUPPLY CURRENT vs TEMPERATURE EYE DIAGRAM AT 11.3 GBPS 80 K28.5 Pattern IMOD = 6 mA MODR = 0 EQENB = 1 75 Supply Current − mA G007 70 65 60 55 50 −40 −20 0 20 40 60 80 TA − Free-Air Temperature − °C 100 150 mV/ Div G009 G008 Figure 13. 14 14.7 ps / Div Figure 14. Submit Documentation Feedback ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3 V, TA = 25°C, IBIASC = 6 mA, IMODC = 12 mA, MODR = 0 (unless otherwise noted). EYE DIAGRAM AT 11.3 GBPS EYE DIAGRAM AT 11.3 GBPS K28.5 Pattern IMOD = 10 mA MODR = 0 EQENB = 1 K28.5 Pattern IMOD = 15 mA MODR = 1 EQENB = 1 320 mV/ Div 14.7 ps / Div 740 mV/ Div 14.7 ps / Div G010 G011 Figure 15. Figure 16. EYE DIAGRAM AT 8.5 GBPS EYE DIAGRAM AT 11.3 GBPS 12" OF FR4 AT INPUTS K28.5 Pattern IMOD = 10 mA MODR = 0 EQENB = 1 K28.5 Pattern IMOD = 10 mA MODR = 0 EQENB = 0 320 mV/ Div 20 ps / Div 320 mV/ Div 14.7 ps / Div G012 Figure 17. G013 Figure 18. Submit Documentation Feedback 15 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3 V, TA = 25°C, IBIASC = 6 mA, IMODC = 12 mA, MODR = 0 (unless otherwise noted). DIFFERENTIAL S11 DIFFERENTIAL S22 0 SDD22 − Differential Input Return Gain − dB SDD11 − Differential Input Return Gain − dB 0 −5 −10 −15 −20 −25 −30 −35 −40 10 100 1k 10k 100k −5 −10 −15 −20 −25 −30 −35 10 f − Frequency − MHz 100 1k 100k f − Frequency − MHz G014 Figure 19. 16 10k G015 Figure 20. Submit Documentation Feedback ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 APPLICATION INFORMATION Figure 21 shows a typical application circuit using the ONET1191V with a common-cathode VCSEL, biased to VCC, and driven differentially. The VCSEL driver is controlled via the two-wire interface SDA/SCK by a microprocessor. In a typical application, the FLT, MONP, MONB, and TS outputs are also connected to the microcontroller for transceiver management purposes. The monitor photodiode anode is grounded and the photodiode polarity bit, PDP, must be set to 0. The component values in Figure 21 are typical examples and may be varied according to the intended application. For best performance, it is recommended to use differential drive. Single-ended VCSEL drive can be implemented by terminating the unused driver output in a resistance that matches the VCSEL series resistance; however, the available VCSEL modulation current is halved. DIS TS– SDK C1 0.01 mF DIN+ DIS RZTC L1 BLM15HG102SN1 NdB Pad C3 0.01 mF MOD+ BIAS NdB Pad C4 0.01 mF Monitor Photodiode L3 100 nH L4 BLM15HG102SN1 PD COMP FLT MONP VCC MONB 100 W Diff MOD– GND BGV L2 100 nH VCSEL 100 W Diff ONET1191V 20-Pin QFN DIN– C2 0.01 mF RZTC 28.7 kW VCC GND DIN+ DIN– FLT TS SDA SCK SDA BGV VCC C5 0.01 mF C6 0.1 mF L5 BLM15HG102SN1 MONB RMONB 1.2 kW RMONP 5 kW MONP C7 0.01 mF S0212-01 Figure 21. Typical Application Circuit With a Common Cathode VCSEL In the recommended application circuit, the purpose of the attenuator pads is to improve the signal integrity between the VCSEL driver and the VCSEL. Because the VCSEL impedance is reactive, the pads attenuate reflections and provide a better matching impedance for the modulation current outputs. The disadvantage of using the attenuator pads is that the efficiency is reduced. That is, not all of the modulation current at the outputs of the VCSEL driver is available to drive the VCSEL. Table 7 lists the available modulation current at the VCSEL, IMOD, depending on the modulation tail current register setting, IMODC, the attenuator value, and the VCSEL series resistance. If care is taken in matching the output impedance of the ONET1191V to the impedance of the VCSEL, and if controlled-impedance transmission lines are used, attenuator pads may not be necessary. Submit Documentation Feedback 17 ONET1191V www.ti.com SLLS750A – AUGUST 2006 – REVISED SEPTEMBER 2006 Table 7. IMOD vs IMODC for a Given Attenuator Pad and VCSEL IMODC (mA): REGISTER SETTING 50-Ω PAD ATTENUATION (dB) VCSEL SERIES RESISTANCE (Ω) IMOD (mA): MODULATION CURRENT AT THE VCSEL 40 3 100 14.76 40 6 100 10.52 30 3 100 11.07 30 6 100 7.89 20 3 100 7.38 20 6 100 5.26 40 3 60 18.33 40 6 60 13.12 30 3 60 13.75 30 6 60 9.84 20 3 60 9.17 20 6 60 6.56 LAYOUT GUIDELINES For optimum performance, use 50-Ω transmission lines (100-Ω differential) for connecting the signal source to the DIN+ and DIN– pins and for connecting the modulation current outputs, MOD+ and MOD–, to the VCSEL. The length of the transmission lines should be kept as short as possible to reduce loss and pattern-dependent jitter. 18 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 20-Sep-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ONET1191VRGPR ACTIVE QFN RGP 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ONET1191VRGPRG4 ACTIVE QFN RGP 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ONET1191VRGPT ACTIVE QFN RGP 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ONET1191VRGPTG4 ACTIVE QFN RGP 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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