JANSR2N7408 Data Sheet Formerly Available As FSF450R4, Radiation Hardened, SEGR Resistant, N-Channel Power MOSFETs The Discrete Products Operation of Intersil has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Also available at other radiation and screening levels. See us on the web, Intersil’ home page: http://www.semi.intersil.com. Contact your local Intersil Sales Office for additional information. December 1998 File Number Features • 9A, 500V, rDS(ON) = 0.600Ω • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) • Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM • Photo Current - 30nA Per-RAD(Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 3E12 Neutrons/cm2 • Usable to 3E13 Neutrons/cm2 Symbol Packaging TO-254AA G Ordering Information 4637 S D PART NUMBER JANSR2N7408 PACKAGE TO-254AA BRAND JANSR2N7408 Die Family TA17659. MIL-PRF-19500/634. CAUTION: Beryllia Warning per MIL-S-19500 refer to package specifications. 4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 JANSR2N7408 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JANSR2N7408 500 500 UNITS V V 9 6 27 ±20 A A A V 125 50 1.00 27 9 27 -55 to 150 300 W W W/oC A A A oC oC 9.3 g CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 500 - - V TC = -55oC - - 5.0 V TC = 25oC 1.5 - 4.0 V TC = 125oC 0.5 - - V VDS = 400V, VGS = 0V TC = 25oC - - 25 µA TC = 125oC - - 250 µA VGS = ±20V TC = 25oC - - 100 nA TC = 125oC - - 200 nA - - 5.67 V TC = 25oC - 0.425 0.600 Ω TC = 125oC - - 1.20 Ω - - 150 ns - - 140 ns td(OFF) - - 180 ns tf - - 70 ns - - 220 nC - 110 150 nC - - 8.2 nC Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 1mA Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On-State Voltage Drain to Source On Resistance Turn-On Delay Time IDSS IGSS VDS(ON) rDS(ON)12 td(ON) Rise Time tr Turn-Off Delay Time Fall Time Total Gate Charge (Not on slash sheet) VGS = 12V, ID = 9A ID = 6A, VGS = 12V VDD = 250V, ID = 9A, RL = 27.8Ω, VGS = 12V, RGS = 2.35Ω Qg(TOT) VGS = 0V to 20V Gate Charge at 12V Qg(12) VGS = 0V to 12V Threshold Gate Charge (Not on slash sheet) Qg(TH) VGS = 0V to 2V VDD = 250V, ID = 9A Gate Charge Source Qgs - 21 28 nC Gate Charge Drain Qgd - 49 62 nC Thermal Resistance Junction to Case RθJC - - 1.00 oC/W Thermal Resistance Junction to Ambient RθJA - - 48 oC/W 4-2 JANSR2N7408 Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage TEST CONDITIONS VSD Reverse Recovery Time MIN TYP MAX UNITS 0.6 - 1.8 V - - 810 ns ISD = 9A trr ISD = 9A, dISD/dt = 100A/µs Electrical Specifications up to 100K RAD TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS - V Drain to Source Breakdown Volts (Note 3) BVDSS VGS = 0, ID = 1mA 500 Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA 1.5 4.0 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±20V, VDS = 0V - 100 nA IDSS Zero Gate Leakage (Note 3) VGS = 0, VDS = 400V - 25 µA Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = 12V, ID = 9A - 5.67 V Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = 12V, ID = 6A - 0.600 Ω NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) Note 4 ENVIRONMENT (NOTE 5) TEST SYMBOL ION SPECIES Single Event Effects Safe Operating Area SEESOA Ni TYPICAL LET (MeV/mg/cm) TYPICAL RANGE (µ) APPLIED VGS BIAS (V) (NOTE 6) MAXIMUM VDS BIAS (V) 26 43 -15 500 Ni 26 43 -20 450 Br 37 36 -5 500 Br 37 36 -10 400 Br 37 36 -15 100 NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). Typical Performance Curves Unless Otherwise Specified LET = 26MeV/mg/cm2, RANGE = 43µ LET = 37MeV/mg/cm2, RANGE = 36µ 600 1E-3 LIMITING INDUCTANCE (HENRY) FLUENCE = 1E5 IONS/cm2 (TYPICAL) 500 VDS (V) 400 300 200 100 TEMP = 25oC 0 0 -5 -10 -15 VGS (V) -20 -25 FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA 4-3 1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6 1E-7 10 30 100 300 DRAIN SUPPLY (V) FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS 1000 JANSR2N7408 Typical Performance Curves Unless Otherwise Specified (Continued) 12 100 TC = 25oC ID , DRAIN CURRENT (A) ID, DRAIN (A) 10 8 6 4 10 100µs 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 2 1ms 100ms 0 -50 0 50 10ms 0.1 150 100 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) TC, CASE TEMPERATURE (oC) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE 1000 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 NORMALIZED rDS(ON) PULSE DURATION = 250µs, VGS = 12V, ID = 6A QG 12V QGS QGD 2.0 1.5 1.0 0.5 VG 0.0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) CHARGE FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE THERMAL RESPONSE (ZθJC) NORMALIZED 10 1 0.5 0.1 0.2 0.1 0.05 0.02 0.01 PDM SINGLE PULSE 0.01 0.001 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE 4-4 t1 t2 100 101 JANSR2N7408 Typical Performance Curves Unless Otherwise Specified (Continued) IAS , AVALANCHE CURRENT (A) 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 1 IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 0.1 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS VDD 50V-150V DUT tP VDD + 50Ω VGS ≤ 20V 0V VDS IAS 50Ω tAV FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS VGS = 12V 10% DUT 10% 0V 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT 4-5 FIGURE 12. RESISTIVE SWITCHING WAVEFORMS JANSR2N7408 Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = ±20V ±20 (Note 7) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 7) µA Drain to Source On Resistance rDS(ON) TC = 125oC at Rated ID ±20% (Note 8) Ω Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANS Gate Stress VGS = 30V, t = 250µs Pind Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER SYMBOL Safe Operating Area SOA Unclamped Inductive Switching IAS TEST CONDITIONS MAX UNITS 0.90 A VGS(PEAK) = 15V, L = 0.1mH 27 A VDS = V, t = 10ms Thermal Response ∆VSD tH = 100ms; VH = 25V; IH = 4A 136 mV Thermal Impedance ∆VSD tH = 500ms; VH = 25V; IH = 4A 187 mV 4-6 JANSR2N7408 Rad Hard Data Packages - Intersil Power Transistors 1. JANS Rad Hard - Standard Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A - Attributes Data Sheet G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. JANS Rad Hard - Optional Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data I. Group D - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data 4-7 JANSR2N7408 TO-254AA 3 LEAD JEDEC TO-254AA HERMETIC METAL PACKAGE INCHES A ØP E SYMBOL A1 Q H1 D 1 2 3 e J1 e1 MAX NOTES 0.249 0.260 6.33 6.60 - 0.040 0.050 1.02 1.27 - Øb 0.035 0.045 0.89 1.14 2, 3 D 0.790 0.800 20.07 20.32 - E 0.535 0.545 13.59 13.84 e1 Øb MILLIMETERS MIN A H1 L MAX A1 e 0.065 R MAX. TYP. MIN 0.150 TYP 0.300 BSC 0.245 0.265 - 3.81 TYP 4 7.62 BSC 4 6.23 6.73 - J1 0.140 0.160 3.56 4.06 4 L 0.520 0.560 13.21 14.22 - ØP 0.139 0.149 3.54 3.78 - Q 0.110 0.130 2.80 3.30 - NOTES: 1. These dimensions are within allowable dimensions of Rev. A of JEDEC outline TO-254AA dated 11-86. 2. Add typically 0.002 inches (0.05mm) for solder coating. 3. Lead dimension (without solder). 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Die to base BeO isolated, terminals to case ceramic isolated. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93. WARNING! BERYLLIA WARNING PER MIL-S-19500 Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’ compounds. 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