INTERSIL JANSR2N7400

JANSR2N7400
Formerly FSS230R4
8A, 200V, 0.440 Ohm, Rad Hard,
N-Channel Power MOSFET
June 1998
Features
Description
• 8A, 200V, rDS(ON) = 0.440Ω
The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm2 with
VDS up to 80% of Rated Breakdown and
VGS of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BVDSS
- Typically Survives 2E12 if Current Limited to IDM
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.
• Photo Current
- 3.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm2
- Usable to 1E14 Neutrons/cm2
Ordering Information
PART NUMBER
JANSR2N7400
Die Family TA17637.
PACKAGE
TO-257AA
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
BRAND
JANSR2N7400
Also available at other radiation and screening levels. See us
on the web, Intersil’s home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional
information.
Symbol
MIL-PRF-19500/632.
Package
TO-257AA
S
D
G
CAUTION: Beryllia Warning per MIL-S-19500
refer to package specifications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
2-58
File Number
4373.1
JANSR2N7400
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS
Maximum Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JANSR2N7400
200
200
UNITS
V
V
8
5
24
±20
A
A
A
V
50
20
0.40
24
8
24
-55 to 150
300
W
W
W/oC
A
A
A
oC
oC
4.4
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge (Not on Slash Sheet)
SYMBOL
BVDSS
VGS(TH)
IDSS
IGSS
VDS(ON)
TEST CONDITIONS
ID = 1mA, VGS = 0V
MIN
TYP
MAX
UNITS
200
-
-
V
TC = -55oC
-
-
5.0
V
TC = 25oC
1.5
-
4.0
V
TC = 125oC
0.5
-
-
V
VDS = 160V,
VGS = 0V
TC = 25oC
-
-
25
µA
TC = 125oC
-
-
250
µA
VGS = ±20V
TC = 25oC
-
-
100
nA
TC = 125oC
-
-
200
nA
VGS = VDS,
ID = 1mA
VGS = 12V, ID = 8A
-
-
3.70
V
TC = 25oC
-
0.320
0.440
Ω
TC = 125oC
-
-
0.744
Ω
-
-
65
ns
-
-
160
ns
td(OFF)
-
-
120
ns
tf
-
-
90
ns
-
-
64
nC
-
33
42
nC
-
-
3.1
nC
nC
rDS(ON)12 ID = 5A,
VGS = 12V
td(ON)
tr
Qg(TOT)
VDD = 100V, ID = 8A,
RL = 12.5Ω, VGS = 12V,
RGS = 7.5Ω
Gate Charge at 12V
Qg(12)
VGS = 0V to 20V VDD = 100V,
ID = 8A,
VGS = 0V to 12V
Threshold Gate Charge (Not on Slash Sheet)
Qg(TH)
VGS = 0V to 2V
Gate Charge Source
Qgs
-
7.8
12
Gate Charge Drain
Qgd
-
17
22
nC
Thermal Resistance Junction to Case
RθJC
-
-
2.5
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
60
oC/W
2-59
JANSR2N7400
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Forward Voltage
VSD
Reverse Recovery Time
TEST CONDITIONS
trr
TYP
MAX
UNITS
0.6
-
1.8
V
-
-
340
ns
ISD = 8A, dISD/dt = 100A/µs
Electrical Specifications up to 100K RAD
PARAMETER
TC = 25oC, Unless Otherwise Specified
SYMBOL
Drain to Source Breakdown Volts
MIN
ISD = 8A
MIN
MAX
UNITS
(Note 3)
BVDSS
VGS = 0, ID = 1mA
TEST CONDITIONS
200
-
V
VGS(TH)
VGS = VDS, ID = 1mA
1.5
4.0
V
IGSS
VGS = ±20V, VDS = 0V
-
100
nA
IDSS
Gate to Source Threshold Volts
(Note 3)
Gate to Body Leakage
(Notes 2, 3)
Zero Gate Leakage
(Note 3)
VGS = 0, VDS = 160V
-
25
µA
Drain to Source On-State Volts
(Notes 1, 3)
VDS(ON)
VGS = 12V, ID = 8A
-
3.70
V
Drain to Source On Resistance
(Notes 1, 3)
rDS(ON)12
VGS = 12V, ID = 5A
-
0.440
Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS .
Single Event Effects (SEB, SEGR)
(Note 4)
ENVIRONMENT (NOTE 5)
TEST
SYMBOL
Single Event Effects Safe Operating
Area
SEESOA
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
APPLIED
VGS BIAS
(V)
(NOTE 6)
MAXIMUM
VDS BIAS
(V)
Ni
26
43
-20
200
Br
37
36
-5
200
Br
37
36
-10
160
Br
37
36
-15
100
Br
37
36
-20
40
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm2 (typical), T = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Typical Performance Curves
Unless Otherwise Specified
LET = 26MeV/mg/cm2, RANGE = 43µ
LET = 37MeV/mg/cm2, RANGE = 36µ
240
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
1E-3
LIMITING INDUCTANCE (HENRY)
200
VDS (V)
160
120
80
40
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
TEMP = 25oC
0
0
-5
-10
-15
VGS (V)
-20
1E-7
10
-25
30
100
300
DRAIN SUPPLY (V)
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
2-60
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO IAS
1000
JANSR2N7400
Typical Performance Curves
Unless Otherwise Specified
(Continued)
10
50
TC = 25oC
ID , DRAIN CURRENT (A)
ID , DRAIN (A)
8
6
4
2
10
100µs
1ms
1
10ms
OPERATION IN THIS
AREA MAY BE
100ms
LIMITED BY rDS(ON)
0
-50
0
50
0.1
150
100
TC , CASE TEMPERATURE (oC)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
1
600
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250ms, VGS = 12V, ID = 5A
NORMALIZED rDS(ON)
2.0
QG
12V
QGS
QGD
VG
1.5
1.0
0.5
0.0
-80
-40
0
CHARGE
FIGURE 5. BASIC GATE CHARGE WAVEFORM
NORMALIZED THERMAL RESPONSE (ZθJC)
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
10
1
0.5
0.1
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
PDM
0.01
0.001
10-5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-61
t1
100
t2
101
JANSR2N7400
Typical Performance Curves
Unless Otherwise Specified
(Continued)
IAS , AVALANCHE CURRENT (A)
50
STARTING TJ = 25oC
10
STARTING TJ = 150oC
IF R = 0
tAV = (L) (IAS) /
(1.3 RATED BVDSS - VDD)
IF R ≠ 0
tAV = (L/R) ln [(IAS*R) /
(1.3 RATED BVDSS - VDD) + 1]
1
0.01
0.1
1
tAV , TIME IN AVALANCHE (ms)
10
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
VDS
L
BVDSS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
tP
VDD
VDS
IAS
-
VGS
VDD
DUT
tP
0V
IAS
0.01Ω
tAV
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
tON
VDD
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
VDS
VGS = 12V
10%
DUT
10%
0V
90%
RGS
50%
VGS
50%
PULSE WIDTH
10%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
2-62
JANSR2N7400
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
UNITS
Gate to Source Leakage Current
IGSS
VGS = ±20V
±20 (Note 7)
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 80% Rated Value
Drain to Source On Resistance
rDS(ON)
TC = 25oC at Rated ID
Gate Threshold Voltage
VGS(TH)
ID = 1.0mA
±25 (Note 7)
µA
±20% (Note 8)
Ω
±20% (Note 8)
V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
VGS = 30V, t = 250µs
Pind
Required
Pre Burn-In Tests (Note 9)
MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 9)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours
PDA
5%
Final Electrical Tests (Note 9)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
Unclamped Inductive Switching
SYMBOL
SOA
TEST CONDITIONS
VDS = 160V, t = 10ms
MAX
UNITS
0.65
A
IAS
VGS(PEAK) = 15V, L = 0.1mH
24
A
Thermal Response
∆VSD
tH = 10ms; VH = 25V; IH = 1A
90
mV
Thermal Impedance
∆VSD
tH = 500ms; VH = 25V; IH = 1A
125
mV
2-63
JANSR2N7400
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A
- Attributes Data Sheet
G. Group B
- Attributes Data Sheet
H. Group C
- Attributes Data Sheet
I. Group D
- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
I. Group D
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
2-64
JANSR2N7400
TO-257AA
3 LEAD JEDEC TO-257AA HERMETIC METAL PACKAGE
A
INCHES
ØP
E
A1
SYMBOL
Q
H1
D
0.065 R TYP.
L1
Øb1
L
b
1
2
3
J1
e
e1
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.190
0.200
4.83
5.08
-
A1
0.035
0.045
0.89
1.14
-
Øb
0.025
0.035
0.64
0.88
2, 3
Øb1
0.060
0.090
1.53
2.28
-
D
0.645
0.665
16.39
16.89
-
E
0.410
0.420
10.42
10.66
-
e
0.100 TYP
2.54 TYP
4
e1
0.200 BSC
5.08 BSC
4
H1
0.230
0.250
5.85
6.35
-
J1
0.110
0.130
2.80
3.30
4
15.24
L
0.600
0.650
16.51
-
L1
-
0.035
-
0.88
-
ØP
0.140
0.150
3.56
3.81
-
Q
0.113
0.133
2.88
3.37
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. B of
JEDEC TO-257AA dated 9-88.
2. Add typically 0.002 inches (0.05mm) for solder coating.
3. Lead dimension (without solder).
4. Position of lead to be measured 0.150 inches (3.81mm) from bottom
of dimension D.
5. Die to base BeO isolated, terminals to case ceramic isolated.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
WARNING!
BERYLLIA WARNING PER MIL-S-19500
Packages containing beryllium oxide (BeO) shall not be ground, machined, sandblasted, or subject to any mechanical
operation which will produce dust containing any beryllium compound. Packages containing any beryllium compound
shall not be subjected to any chemical process (etching, etc.) which will produce fumes containing beryllium or its’
compounds.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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TEL: (407) 724-7000
FAX: (407) 724-7240
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TEL: (32) 2.724.2111
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2-65
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