LTC1164-7 Low Power, Linear Phase 8th Order Lowpass Filter U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ Better Than Bessel Roll-Off fCUTOFF up to 20kHz, Single 5V Supply ISUPPLY = 2.5mA (Typ), Single 5V Supply 75dB THD + Noise with Single 5V Supply Phase and Group Delay Response Fully Tested Transient Response with No Ringing Wide Dynamic Range No External Components Needed UO APPLICATI ■ ■ ■ S The LTC1164-7 is a low power, clock-tunable monolithic 8th order lowpass filter with linear passband phase and flat group delay. The amplitude response approximates a maximally flat passband and exhibits steeper roll-off than an equivalent 8th order Bessel filter. For instance, at twice the cutoff frequency the filter attains 34dB attenuation (vs12dB for Bessel), while at three times the cutoff frequency the filter attains 68dB attenuation (vs 30dB for Bessel). The cutoff frequency of the LTC1164-7 is tuned via an external TTL or CMOS clock. Low power is achieved without sacrificing dynamic range. With single 5V supply, the S/N + THD is up to 75dB. Optimum 91dB S/N is obtained with ±7.5V supplies. Data Communication Filters Time Delay Networks Phase Matched Filters The clock-to-cutoff frequency ratio of the LTC1164-7 can be set to 50:1 (pin 10 to V +) or 100:1 (pin 10 to V –). When the filter operates at the clock-to-cutoff frequency ratio of 50:1, the input is double-sampled to lower the risk of aliasing. The LTC1164-7 is pin-compatible with the LTC1064-X series and LTC1264-7. UO TYPICAL APPLICATI Frequency Response 10kHz Linear Phase Lowpass Filter 5V 14 2 13 3 12 4 LTC1164-7 11 10 6 9 7 8 NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A 0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT PIN AND THE fCLK LINE. 1164-7 TA01 130 –20 CLK = 500kHz VOUT 140 –10 –5V 5V 150 DELAY –30 120 –40 110 –50 100 –60 90 –70 80 –80 70 1 10 FREQUENCY (kHz) DELAY (µs) 5 GAIN 0 GAIN (dB) VIN 1 100 1164-7 TA02 1 LTC1164-7 W W W AXI U U ABSOLUTE RATI GS Total Supply Voltage (V + to V –) ............................. 16V Power Dissipation............................................. 400mW Burn-In Voltage ...................................................... 16V Voltage at Any Input ..... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V) Storage Temperature Range ................ – 65°C to 150°C Operating Temperature Range LTC1164-7C ...................................... – 40°C to 85°C LTC1164-7M ................................... – 55°C to 125°C Lead Temperature (Soldering, 10 sec)................ 300°C U W U PACKAGE/ORDER I FOR ATIO TOP VIEW TOP VIEW NC 1 16 CONNECT 2 13 NC VIN 2 15 NC 12 V – GND 3 14 V – V+ 13 NC NC 1 14 CONNECT 2 VIN 2 GND 3 V+ 4 11 fCLK GND 5 10 50/100 LP6 6 9 VOUT CONNECT 1 7 8 NC J PACKAGE 14-LEAD CERAMIC DIP ORDER PART NUMBER LTC1164-7CN LTC1164-7CJ LTC1164-7MJ 4 GND 5 LTC1164-7CS 12 fCLK NC 6 11 50/100 LP6 7 10 NC CONNECT 1 8 N PACKAGE 14-LEAD PLASTIC DIP ORDER PART NUMBER 9 VOUT S PACKAGE 16-LEAD PLASTIC SOL TJMAX = 150°C, θJA = 65°C/W (J) TJMAX = 110°C, θJA = 65°C/W (N) TJMAX = 110°C, θJA = 85°C/W ELECTRICAL CHARACTERISTICS VS = ±7.5V, RL = 10k, TA = 25°C, fCUTOFF = 8kHz or 4kHz, fCLK = 400kHz, TTL or CMOS level and all gain measurements are referenced to passband gain, unless otherwise specified. (Maximum clock rise or fall time ≤ 1µs) PARAMETER Passband Gain Gain at 0.50 fCUTOFF (Note 3) Gain at 0.75 fCUTOFF Gain at fCUTOFF Gain at 2.0 fCUTOFF Gain with fCLK = 20kHz Gain with fCLK = 400kHz, VS = ±2.375V Phase Factor (F ) Phase = 180° – F (f/fC) (Note 1) Phase Nonlinearity (Note 1) 2 CONDITIONS 0.1Hz ≤ f ≤ 0.25 fCUTOFF fTEST = 2kHz, (fCLK / fC) = 50:1 (Note 4) fTEST = 4kHz, (fCLK / fC) = 50:1 fTEST = 2kHz, (fCLK / fC) = 100:1 fTEST = 6kHz, (fCLK / fC) = 50:1 fTEST = 8kHz, (fCLK / fC) = 50:1 fTEST = 4kHz, (fCLK / fC) = 100:1 fTEST = 16kHz, (fCLK / fC) = 50:1 fTEST = 8kHz, (fCLK / fC) = 100:1 fTEST = 200Hz, (fCLK / fC) = 100:1 fTEST = 4kHz, (fCLK / fC) = 50:1 fTEST = 8kHz, (fCLK / fC) = 50:1 0.1Hz ≤ f ≤ fCUTOFF (fCLK / fC) = 50:1 (fCLK / fC) = 100:1 (fCLK / fC) = 50:1 (fCLK / fC) = 100:1 (fCLK / fC) = 50:1 (fCLK / fC) = 100:1 (fCLK / fC) = 50:1 (fCLK / fC) = 100:1 ● ● ● ● ● ● ● ● MIN TYP MAX UNITS – 0.50 – 0.50 – 0.85 – 1.2 – 4.1 – 5.5 – 37 – 38 – 5.7 – 0.50 – 3.75 – 0.10 – 0.20 – 0.65 –1.1 – 3.4 – 5.2 – 34 – 34 – 5.2 – 0.2 – 3.4 0.30 0.30 0.15 0.1 –1.9 – 2.5 – 30 – 30 – 2.5 0.2 – 2.5 dB dB dB dB dB dB dB dB dB dB dB 435 ± 2 428 ± 2 ● ● 430 423 442 434 ±1.0 ±1.0 ● ● ± 2.0 ± 2.5 Deg Deg Deg Deg % % % % LTC1164-7 ELECTRICAL CHARACTERISTICS VS = ±7.5V, RL = 10k, TA = 25°C, f CUTOFF = 8kHz or 4kHz, fCLK = 400kHz, TTL or CMOS level and all gain measurements are referenced to passband gain, unless otherwise specified. (Maximum clock rise or fall time ≤ 1µs) PARAMETER Group Delay (td) td = (1/360)(f/fC) (Note 2) Group Delay Deviation (Note 2) Input Frequency Range (Table 9) Maximum fCLK Clock Feedthrough (f = fCLK) Wideband Noise (1Hz ≤ f < fCLK) Input Impedance Output DC Voltage Swing (Note 4) Output DC Offset Output DC Offset TempCo Power Supply Current CONDITIONS (fCLK/fC) = 50:1, f ≥ fCUTOFF (fCLK/fC) = 100:1, f ≥ f CUTOFF (fCLK/fC) = 50:1, f ≥ fCUTOFF (fCLK/fC) = 100:1, f ≥ f CUTOFF (fCLK/fC) = 50:1, f ≥ fCUTOFF (fCLK/fC) = 100:1, f ≥ f CUTOFF (fCLK/fC) = 50:1, f ≥ fCUTOFF (fCLK/fC) = 100:1, f ≥ f CUTOFF (fCLK/fC) = 50:1 (fCLK/fC) = 100:1 VS = Single 5V (Pins 3 and 5 at 2V) VS = ±5V VS = ±7.5V 50:1, ±5V, Input at GND VS = ±2.5V VS = ±5V VS = ±7.5V MIN TYP 151.0 ± 1 297.2 ± 1 MAX 149.3 293.8 ● ● 153.5 301.4 ±1.0 ±1.0 ±2.0 ±2.5 ● ● VS = ±2.375V VS = ±5V VS = ±7.5V 50:1, VS = ±5V 100:1, VS = ±5V 50:1, VS = ±5V 100:1, VS = ±5V VS = ±2.375V, TA = 25°C 35 ±1.25 ±3.70 ±5.40 ● ● <fCLK <fCLK /2 1 1 1 100 95 ± 5% 105 ± 5% 115 ± 5% 55 ±1.4 ±3.9 ±6.1 ±100 ±100 ±200 ±200 2.5 90 ±220 4.0 4.5 7.0 8.0 11.0 12.5 ±8 ● VS = ±5V, TA = 25°C 4.5 ● VS = ±7.5V, TA = 25°C 7.0 ● ±2.375 Power Supply Range 180 fCLK = 500kHz (fCLK /fC) = 50:1 90 PHASE (DEG) The ● denotes specifications which apply over the full operating temperature range. Note 1: Input frequencies, f, are linearly phase shifted through the filter as long as f ≤ fC; fC = cutoff frequency. Figure 1 curve shows the typical phase response of an LTC1164-7 operating at fCLK = 400kHz, fC = 8kHz and it closely matches an ideal straight line. The phase shift is described by: phase shift = 180° – F (f/fC); f ≤ fC. F is arbitrarily called the “phase factor” expressed in degrees. The phase factor together with the specified deviation from the ideal straight line allows the calculation of the phase at a given frequency. Example: The phase shift at 7kHz of the LTC1164-7 shown in Figure 1 is: phase shift = 180° – 434° (7kHz/10kHz) ± nonlinearity = –123.8° ± 1% or –123.9° ± 1.24°. Note 2: Group delay and group delay deviation are calculated from the measured phase factor and phase deviation specifications. Note 3: The filter cutoff frequency is abbreviated as f CUTOFF or fC. Note 4: The AC swing is typically 11VP-P, 7VP-P, 2.8VP-P for ±7.5V, ± 5V, ± 2.5V supply respectively. For more information refer to the THD + Noise vs Input graphs. UNITS µs µs µs µs % % % % kHz kHz MHz MHz MHz µVRMS µVRMS µVRMS µVRMS kΩ V V V mV mV µV/°C µV/°C mA mA mA mA mA mA V 0 –90 –180 –270 –360 0 1 2 3 4 5 6 7 FREQUENCY (kHz) 8 9 10 1164-7 F01 Figure 1. Phase Response in the Passband (Note 1) 3 LTC1164-7 U W TYPICAL PERFOR A CE CHARACTERISTICS Phase Factor vs fCLK (Typical Unit) Gain vs Frequency 10 Phase Factor vs fCLK (Typical Unit) 436 438 VS = ±5V (fCLK /fC) = 50:1 0 –10 434 100:1 –40 50:1 –50 –60 –70 433 437 PHASE FACTOR GAIN (dB) –30 PHASE FACTOR –20 70°C 25°C 0°C 436 VS = ±5V fCLK = 500kHz TA = 25°C –90 –100 –110 0.1 25°C 431 70°C 430 0°C 428 427 1 10 FREQUENCY (kHz) 435 0.25 100 0.75 0.5 426 0.25 1.0 1164-7 G03 Phase Factor vs fCLK (Min and Max Representative Units) Gain vs Frequency 10 438 VS = ±5V (fCLK /fC) = 50:1 TA = 25°C PHASE FACTOR 437 435 VS = SINGLE 5V PINS 3, 5 AT 2V (fCLK /fC) = 50:1 TA = 25°C 0 –10 –20 436 GAIN (dB) 438 435 –30 –40 –50 VS = SINGLE 5V fCLK = 1MHz fC = 10kHz (fCLK /fC) = 50:1 TA = 25°C –60 –70 434 434 –80 433 0.25 0.75 0.5 1.0 –90 433 0.25 0.75 0.5 Passband Gain and Phase Passband Gain and Phase GAIN 0 –90 VS = ±5V fCLK = 50kHz fC = 1kHz (fCLK /fC) = 50:1 200 800 400 600 FREQUENCY (Hz) 1000 180 90 GAIN 0 –5 PHASE –10 –180 –15 –270 –20 –90 VS = ±5V fCLK = 100kHz fC = 1kHz (fCLK /fC) = 100:1 –180 –270 200 800 400 600 FREQUENCY (Hz) 1000 1164-7 G08 PHASE (DEG) GAIN (dB) 90 PHASE (DEG) PHASE –10 1164-7 G07 4 5 0 –5 –20 180 GAIN (dB) 5 100 1164-7 G06 1164-7 G05 1164-7 G04 –15 10 FREQUENCY (kHz) 1 1.0 fCLK (MHz) fCLK (MHz) 0 1.0 fCLK (MHz) 1164-7 G02 Phase Factor vs fCLK (Min and Max Representative Units) 436 0.75 0.5 fCLK (MHz) 1264-7 G01 PHASE FACTOR 432 429 –80 437 VS = ±5V (fCLK /fC) = 100:1 435 LTC1164-7 U W TYPICAL PERFOR A CE CHARACTERISTICS Passband Gain vs Frequency and fCLK Passband Gain vs Frequency and fCLK 3 2 A. fCLK = 250kHz B. fCLK = 500kHz C. fCLK = 750kHz D. fCLK = 1000kHz VS = ±5V (fCLK /fC) = 50:1 TA = 85°C 4 3 A. fCLK = 250kHz B. fCLK = 500kHz C. fCLK = 750kHz D. fCLK = 1000kHz 2 GAIN (dB) 1 0 –1 3 2 1 0 –1 A –3 B C D A –3 B C D 0 –1 –4 –4 –5 –5 10 FREQUENCY (kHz) 1 100 10 FREQUENCY (kHz) Delay vs Frequency and fCLK Delay vs Frequency and fCLK A A. fCLK = 250kHz B. fCLK = 500kHz C. fCLK = 750kHz D. fCLK = 1000kHz 1 0 –1 B A B 400 350 100 C D C D VS = ±5V (fCLK /fC) = 100:1 TA = 25°C A 450 A. fCLK = 250kHz B. fCLK = 500kHz C. fCLK = 750kHz D. fCLK = 1000kHz 150 –2 –3 VS = ±5V (fCLK /fC) = 50:1 TA = 25°C 200 DELAY (µs) 2 500 DELAY (µs) 3 100 1164-7 G11 250 5 VS = SINGLE 5V (fCLK /fC) = 50:1 TA = 85°C 10 FREQUENCY (kHz) 1 100 B C D 1164-7 G10 Passband Gain vs Frequency and fCLK 4 A –3 –5 1164-7 G09 50 A. fCLK = 250kHz B. fCLK = 500kHz C. fCLK = 750kHz D. fCLK = 1000kHz 300 B 250 200 C 150 D 100 –4 50 0 –5 1 10 FREQUENCY (kHz) 2 100 4 6 8 10 12 14 16 18 20 FREQUENCY (kHz) 1164-7 G12 0 22 1 THD + Noise vs Frequency THD + Noise vs Frequency – 55 – 60 – 50 –65 –70 –75 – 55 – 60 – 50 –65 – 70 –75 – 55 – 60 –65 – 70 –75 –80 –80 –85 –85 –85 –90 –90 5 FREQUENCY (kHz) 10 1164-7 G15 10 11 1 5 FREQUENCY (kHz) VS = ±7.5V VIN = 2VRMS fCLK = 500kHz (fCLK /fC) = 100:1 (5 REPRESENTATIVE UNITS) –45 –80 1 9 THD + Noise vs Frequency VS = ±5V VIN = 1VRMS fCLK = 500kHz (fCLK /fC) = 50:1 (5 REPRESENTATIVE UNITS) –45 THD + NOISE (dB) – 50 4 5 6 7 8 FREQUENCY (kHz) – 40 THD + NOISE (dB) VS = ±7.5V VIN = 2VRMS fCLK = 500kHz (fCLK /fC) = 50:1 (5 REPRESENTATIVE UNITS) 3 1264-7 G14 – 40 –45 2 1264-7 G13 – 40 THD + NOISE (dB) 1 –4 1 A. fCLK = 250kHz B. fCLK = 500kHz C. fCLK = 750kHz D. fCLK = 1000kHz –2 –2 –2 VS = ±5V (fCLK /fC) = 100:1 TA = 25°C 4 GAIN (dB) VS = ±5V fC = 5kHz (fCLK /fC) = 50:1 TA = 25°C 4 GAIN (dB) 5 5 5 GAIN (dB) Passband Gain vs Frequency and fCLK 10 1164-7 G16 –90 1 2 3 FREQUENCY (kHz) 4 5 1164-7 G17 5 LTC1164-7 U W TYPICAL PERFOR A CE CHARACTERISTICS THD + Noise vs Frequency – 55 – 60 VS = SINGLE 5V VIN = 0.5VRMS fCLK = 500kHz (fCLK /fC) = 50:1 AGND = 2V (5 REPRESENTATIVE UNITS) –45 – 50 THD + NOISE (dB) –65 – 70 –75 – 55 – 60 –65 – 50 – 70 –75 –65 – 70 –75 –80 –80 –85 –85 –85 –90 1 2 3 FREQUENCY (kHz) 4 1 5 5 FREQUENCY (kHz) –90 10 THD + Noise vs Frequency THD + Noise vs Input VS = SINGLE 5V VIN = 0.5VRMS fCLK = 500kHz (fCLK /fC) = 100:1 AGND = 2.5V (5 REPRESENTATIVE UNITS) THD + Noise vs Input fIN = 1kHz fCLK = 500kHz (fCLK /fC) = 50:1 –50 –65 – 70 –75 A. VS = ±5V B. VS = ±7.5V –50 A B –55 –60 –65 –70 –75 –55 –70 –75 –80 –85 –85 –85 2 3 FREQUENCY (kHz) 4 –90 0.1 5 1 B –65 –70 –75 –80 4 3 11 –55°C 10 9 2 8 25°C 7 125°C 6 5 4 3 1 2 A. AGND = 2V B. AGND = 2.5V –90 0.1 1 1 2 INPUT (VRMS) 1164-7 G24 6 PHASE DIFFERENCE BETWEEN ANY TWO UNITS (SAMPLE OF 50 REPRESENTATIVE UNITS) VS ≥ ±5V fCLK ≤ 500kHz (fCLK /fC) = 50:1 OR 100:1 TA = 0°C TO 70°C A –60 –85 12 5 PHASE DIFFERENCE (DEG) –55 Power Supply Current vs Power Supply Voltage Phase Matching vs Frequency –40 –50 1164-7 G23 1164-7 G22 THD + Noise vs Input VS = SINGLE 5V fCLK = 500kHz fIN = 1kHz (fCLK /fC) = 100:1 2 1 INPUT (VRMS) INPUT (VRMS) 1164-7 G21 –45 A. AGND = 2V B. AGND = 2.5V –90 0.1 5 A –65 –80 1 B –60 –80 –90 VS = SINGLE 5V fCLK = 500kHz fIN = 1kHz (fCLK /fC) = 50:1 –45 THD + NOISE (dB) – 55 – 60 –40 –45 THD + NOISE (dB) – 50 10 1164-7 G20 –40 – 40 –45 5 FREQUENCY (kHz) 1 1164-7 G19 1164-7 G18 THD + NOISE (dB) – 55 – 60 –80 –90 VS = SINGLE 5V VIN = 0.5VRMS fCLK = 500kHz (fCLK /fC)= 50:1 AGND = 2.5V (5 REPRESENTATIVE UNITS) –45 CURRENT (mA) THD + NOISE (dB) – 50 – 40 THD + NOISE (dB) VS = ±5V VIN = 1VRMS fCLK = 500kHz (fCLK /fC) = 100:1 (5 REPRESENTATIVE UNITS) –45 THD + NOISE (dB) THD + Noise vs Frequency THD + Noise vs Frequency – 40 – 40 0 0 0 0.2 0.6 0.8 0.4 FREQUENCY (fCUTOFF /FREQUENCY) 1.0 1164-7 G25 0 1 3 4 2 5 6 7 8 POWER SUPPLY (V + OR V –) 9 10 1164-7 G26 LTC1164-7 U W TYPICAL PERFOR A CE CHARACTERISTICS Table 1. Passband Gain and Phase VS = ±7.5V, Ratio = 50:1, TA = 25°C FREQUENCY (kHz) fCLK = 250kHz (Typical Unit) 0.000 1.250 2.500 3.750 5.000 – 0.085 – 0.085 – 0.261 – 1.092 – 3.647 180.00 71.51 – 37.31 – 146.38 – 255.45 FREQUENCY (kHz) fCLK = 250kHz (Typical Unit) 0.000 0.625 1.250 1.875 2.500 fCLK = 500kHz (Typical Unit) 0.000 2.500 5.000 7.500 10.000 – 0.091 – 0.091 – 0.251 – 1.028 – 3.488 180.00 71.36 – 37.57 –146.78 – 256.16 fCLK = 750kHz (Typical Unit) 0.000 3.750 7.500 11.250 15.000 – 0.106 – 0.106 – 0.264 – 0.943 – 3.206 fCLK = 1MHz (Typical Unit) 0.000 5.000 10.000 15.000 20.000 GAIN (dB) Table 2. Passband Gain and Phase VS = ±7.5V, Ratio = 100:1, TA = 25°C – 0.131 – 0.131 – 0.291 – 0.853 – 2.864 PHASE (DEG) 180.00 71.39 – 36.79 – 143.66 – 247.79 fCLK = 500kHz (Typical Unit) 0.000 1.250 2.500 3.750 5.000 – 0.176 – 0.176 – 0.645 – 1.945 – 5.032 180.00 71.34 – 36.88 – 143.93 – 248.52 180.00 71.26 – 37.65 – 146.88 – 256.58 fCLK = 750kHz (Typical Unit) 0.000 1.875 3.750 5.625 7.500 – 0.161 – 0.161 – 0.574 – 1.789 – 4.779 180.00 71.32 – 37.04 – 144.45 – 249.82 180.00 71.11 – 37.71 – 146.87 – 256.81 fCLK = 1MHz (Typical Unit) 0.000 2.500 5.000 7.500 10.000 – 0.157 – 0.157 – 0.538 – 1.666 – 4.527 180.00 71.23 – 37.28 – 145.02 – 251.13 Table 4. Passband Gain and Phase VS = ±5V, Ratio = 100:1, TA = 25°C fCLK = 500kHz (Typical Unit) 0.000 2.500 5.000 7.500 10.000 fCLK = 750kHz (Typical Unit) 0.000 3.750 7.500 11.250 15.000 fCLK = 1MHz (Typical Unit) 0.000 5.000 10.000 15.000 20.000 – 0.071 – 0.071 – 0.243 – 1.068 – 3.609 180.00 71.48 – 37.29 – 146.34 – 255.40 FREQUENCY (kHz) fCLK = 250kHz (Typical Unit) 0.000 0.625 1.250 1.875 2.500 – 0.081 – 0.081 – 0.236 – 0.981 – 3.371 180.00 71.35 – 37.52 –146.71 – 256.13 GAIN (dB) – 0.105 – 0.105 – 0.261 – 0.883 – 3.008 – 0.134 – 0.134 – 0.292 – 0.771 – 2.571 PHASE (DEG) – 0.201 – 0.201 – 0.727 – 2.075 – 5.205 Table 3. Passband Gain and Phase VS = ±5V, Ratio = 50:1, TA = 25°C FREQUENCY (kHz) fCLK = 250kHz (Typical Unit) 0.000 1.250 2.500 3.750 5.000 GAIN (dB) PHASE (DEG) GAIN (dB) PHASE (DEG) – 0.189 – 0.189 – 0.707 – 2.048 – 5.711 180.00 71.39 – 36.75 – 143.60 – 247.74 fCLK = 500kHz (Typical Unit) 0.000 1.250 2.500 3.750 5.000 – 0.159 – 0.159 – 0.603 – 1.872 – 4.926 180.00 71.35 – 36.85 – 144.00 – 248.80 180.00 71.26 – 37.62 – 146.80 – 256.57 fCLK = 750kHz (Typical Unit) 0.000 1.875 3.750 5.625 7.500 – 0.149 – 0.149 – 0.536 – 1.704 – 4.621 180.00 71.28 – 37.13 – 144.72 – 250.48 180.00 70.99 – 37.75 – 146.83 – 256.88 fCLK = 1MHz (Typical Unit) 0.000 2.500 5.000 7.500 10.000 – 0.151 – 0.151 – 0.511 – 1.581 – 4.336 180.00 71.10 – 37.52 – 145.45 – 252.01 7 LTC1164-7 U W TYPICAL PERFOR A CE CHARACTERISTICS Table 5. Passband Gain and Phase VS = Single 5V, Ratio = 50:1, TA = 25°C FREQUENCY (kHz) fCLK = 250kHz (Typical Unit) 0.000 1.250 2.500 3.750 5.000 GAIN (dB) fCLK = 500kHz (Typical Unit) 0.000 2.500 5.000 7.500 10.000 fCLK = 750kHz (Typical Unit) 0.000 3.750 7.500 11.250 15.000 fCLK = 1MHz (Typical Unit) 0.000 5.000 10.000 15.000 20.000 Table 6. Passband Gain and Phase VS = Single 5V, Ratio = 100:1, TA = 25°C – 0.085 – 0.085 – 0.252 – 1.056 – 3.562 180.00 71.54 – 37.15 – 146.12 – 255.22 FREQUENCY (kHz) fCLK = 250kHz (Typical Unit) 0.000 0.625 1.250 1.875 2.500 – 0.101 – 0.101 – 0.251 – 0.947 – 3.252 180.00 71.39 – 37.38 –146.44 – 256.02 – 0.133 – 0.133 – 0.291 – 0.826 – 2.789 – 0.162 – 0.162 – 0.307 – 0.647 – 2.201 PHASE (DEG) GAIN (dB) PHASE (DEG) – 0.283 – 0.283 – 0.799 – 2.143 – 5.271 180.00 71.35 – 37.01 – 143.96 – 248.03 fCLK = 500kHz (Typical Unit) 0.000 1.250 2.500 3.750 5.000 – 0.252 – 0.252 – 0.676 – 1.917 – 4.936 180.00 71.28 – 37.16 – 144.46 – 249.40 180.00 71.16 – 37.56 – 146.55 – 256.52 fCLK = 750kHz (Typical Unit) 0.000 1.875 3.750 5.625 7.500 – 0.231 – 0.231 – 0.603 – 1.704 – 4.535 180.00 70.94 – 37.72 – 145.55 – 251.81 180.00 70.89 – 37.78 – 146.67 – 257.06 fCLK = 1MHz (Typical Unit) 0.000 2.500 5.000 7.500 10.000 – 0.212 – 0.212 – 0.532 – 1.497 – 4.115 180.00 70.83 – 38.11 – 146.47 – 253.92 U U U PI FU CTIO S Power Supply Pins (4, 12) + – The V (pin 4) and the V (pin 12) should each be bypassed with a 0.1µF capacitor to an adequate analog ground. The filter’s power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than 1V/µs. When V + is applied before V – and V – is allowed to go above ground, a signal diode should clamp V – to prevent latch-up. Figures 2 and 3 show typical connections for dual and single supply operation. Clock Input Pin (11) Any TTL or CMOS clock source with a square-wave output and 50% duty cycle (±10%) is an adequate clock source 8 for the device. The power supply for the clock source should not be the filter’s power supply. The analog ground for the filter should be connected to clock’s ground at a single point only. Table 7 shows the clock’s low and high level threshold values for dual or single supply operation. A pulse generator can be used as a clock source provided the high level ON time is greater than 0.5µs. Sine waves are not recommended for clock input frequencies less than 100kHz, since excessively slow clock rise or fall times generate internal clock jitter (maximum clock rise or fall time ≤ 1µs). The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal path. A 1k resistor between clock source and pin 11 will slow down the rise and fall times of the clock to further reduce charge coupling (Figures 2 and 3). LTC1164-7 U U U PI FU CTIO S Table 7. Clock Source High and Low Threshold Levels POWER SUPPLY Dual Supply = ±7.5V Dual Supply = ±5V Dual Supply = ± 2.5V Single Supply = 12V Single Supply = 5V HIGH LEVEL ≥ 2.18V ≥ 1.45V ≥ 0.73V ≥ 7.80V ≥ 1.45V LOW LEVEL ≤ 0.5V ≤ 0.5V ≤ – 2.0V ≤ 6.5V ≤ 0.5V V– VIN 1 14 2 13 3 12 4 V+ 0.1µF LTC1164-7 0.1µF 1k 11 5 10 6 9 7 8 CLOCK SOURCE V+ + GND DIGITAL SUPPLY VOUT 1164-7 F02 Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 50:1 VIN V+ 0.1µF 10k 10k Ratio Input Pin (10) The DC level at this pin determines the ratio of the clock frequency to the cutoff frequency of the filter. Pin 10 at V + gives a 50:1 ratio and pin 10 at V – gives a 100:1 ratio. For single supply operation the ratio is 50:1 when pin 10 is at V + and 100:1 when pin 10 is at ground. When pin 10 is not tied to ground, it should be bypassed to analog ground with a 0.1µF capacitor. If the DC level at pin 10 is switched mechanically or electrically at slew rates greater than 1V/µs while the device is operating, a 10k resistor should be connected between pin 10 and the DC source. Filter Input Pin (2) The input pin is connected internally through a 50k resistor tied to the inverting input of an op amp. 1 14 2 13 3 12 4 11 1k 5 10 + 6 9 7 8 LTC1164-7 and 5 should be biased at 1/2 supply and should be bypassed to the analog ground plane with at least a 1µF capacitor (Figure 3). For single 5V operation at the highest fCLK of 2MHz, pins 3 and 5 should be biased at 2V. This minimizes passband gain and phase variations. Filter Output Pins (9, 6) CLOCK SOURCE V + GND DIGITAL SUPPLY + 1µF VOUT 1164-7 F03 Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 50:1 Pin 9 is the specified output of the filter; it can typically source/sink 1mA. Driving coaxial cables or resistive loads less than 20k will degrade the total harmonic distortion of the filter. When evaluating the device’s distortion an output buffer is required. A noninverting buffer, Figure 4, can be used provided that its input common-mode range is well within the filter’s output swing. Pin 6 is an intermediate filter output providing an unspecified 6th order lowpass filter. Pin 6 should not be loaded. Analog Ground Pins (3, 5) The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation, pins 3 and 5 should be connected to the analog ground plane. For single supply operation, pins 3 – 1k LT1056 + 1164-7 F04 Figure 4. Buffer for Filter Output 9 LTC1164-7 U U U PI FU CTIO S External Connection Pins (7, 14) NC Pins (1, 8, 13) Pins 7 and 14 should be connected together. In a printed circuit board the connection should be done under the IC package through a short trace surrounded by the analog ground plane. Pins 1, 8 and 13 are not connected to any internal circuit point on the device and should be preferably tied to analog ground. U W U UO APPLICATI S I FOR ATIO Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter’s output pin (9). The clock feedthrough is tested with the input pin (2) grounded and it depends on PC board layout and on the value of the power supplies. With proper layout techniques the values of the clock feedthrough are shown in Table 8. Table 8. Clock Feedthrough VS Single 5V ±5V ±7.5V 50:1 70µVRMS 100µVRMS 120µVRMS 100:1 70µVRMS 200µVRMS 500µVRMS Note: The clock feedthrough at Single 5V is imbedded in the wideband noise of the filter. The clock waveform is a square wave. Any parasitic switching transients during the rise and fall edges of the incoming clock are not part of the clock feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. The clock feedthrough, if bothersome, can be greatly reduced by adding a simple R/C lowpass network at the output of the filter pin (9). This R/C will completely eliminate any switching transients. Wideband Noise The wideband noise of the filter is the total RMS value of the device’s noise spectral density and it is used to determine the operating signal-to-noise ratio. Most of its frequency contents lie within the filter’s passband and cannot be reduced with post filtering. For instance, the 10 LTC1164-7 wideband noise at ±5V supply is 105µVRMS, 95µVRMS of which have frequency contents from DC up to the filter’s cutoff frequency. The total wideband noise (µVRMS) is nearly independent of the value of the clock. The clock feedthrough specifications are not part of the wideband noise. Speed Limitations The LT1164-7 optimizes AC performance vs power consumption. To avoid op amp slew rate limiting at maximum clock frequencies, the signal amplitude should be kept below a specified level as shown in Table 9. Table 9. Maximum VIN vs VS and Clock POWER SUPPLY ±7.5V MAXIMUM fCLK 1MHz ±5V 1MHz Single 5V 1MHz MAXIMUM VIN 2.0VRMS (fIN > 20kHz) 0.7VRMS (fIN > 250kHz) 1.4VRMS (fIN > 20kHz) 0.5VRMS (fIN > 100kHz) 0.5VRMS (fIN > 100kHz) Table 10. Transient Response of LTC Lowpass Filters LOWPASS FILTER LTC1064-3 Bessel LTC1164-5 Bessel LTC1164-6 Bessel DELAY TIME* (SEC) 0.50/fC 0.43/fC 0.43/fC RISE SETTLING OVERTIME** TIME*** SHOOT (SEC) (SEC) (%) 0.34/fC 0.80/fC 0.5 0.34/fC 0.85/fC 0 0.34/fC 1.15/fC 1 LTC1264-7 Linear Phase LTC1164-7 Linear Phase LTC1064-7 Linear Phase 1.15/fC 1.20/fC 1.20/fC 0.36/fC 0.39/fC 0.39/fC 2.05/fC 2.20/fC 2.20/fC 5 5 5 LTC1164-5 Butterworth 0.80/fC 0.48/fC 2.40/fC 11 LTC1164-6 Elliptic LTC1064-4 Elliptic LTC1064-1 Elliptic 0.85/fC 0.90/fC 0.85/fC 0.54/fC 0.54/fC 0.54/fC 4.30/fC 4.50/fC 6.50/fC 18 20 20 * To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5% LTC1164-7 U W U UO APPLICATI S I FOR ATIO Transient Response 2V/DIV If, for instance, an LTC1164-7 operating with a 100kHz clock and 1kHz cutoff frequency receives a 98kHz 10mV input signal, a 2kHz, 143µVRMS alias signal will appear at its output. When the LTC1164-7 operates with a clock-tocutoff frequency of 50:1, aliasing occurs at twice the clock frequency. Table 11 shows details. Table 11. Aliasing (fCLK = 100kHz ) 100µs/DIV INPUT = 1kHz ± 3V fCLK = 500kHz fC = 10kHz VS = ±7.5V 1164-7 F05 Figure 5. ts OUTPUT INPUT 90% 50% 10% td INPUT FREQUENCY (VIN = 1VRMS, fIN = fCLK ± fOUT) (kHz) 50:1, fCUTOFF = 2kHz OUTPUT LEVEL (Relative to Input, 0dB = 1VRMS) (dB) OUTPUT FREQUENCY (Aliased Frequency fOUT = ABS [fCLK ± fIN]) (kHz) 190 (or 210) 195 (or 205) 196 (or 204) 197(or 203) 198 (or 202) 199.5 (or 200.5) 100:1, fCUTOFF = 1kHz –76.1 – 51.9 – 36.3 – 18.4 – 3.0 – 0.2 10.0 5.0 4.0 3.0 2.0 0.5 97 (or 103) 97.5 (or 102.5) 98 (or 102) 98.5 (or 101.5) 99 (or 101) 99.5 (or 100.5) –74.2 – 53.2 – 36.9 – 19.6 – 5.2 – 0.7 3.0 2.5 2.0 1.5 1.0 0.5 tr 0.39 ±5% fCUTOFF 2.2 SETTLING TIME (ts) = ±5% f (TO 1% of OUTPUT) CUTOFF 1.2 TIME DELAY (td) = GROUP DELAY ≈ fCUTOFF (TO 50% OF OUTPUT) 1V/DIV RISE TIME (tr) = 1164-7 F06 Figure 6. 5µs/DIV Aliasing Aliasing is an inherent phenomenon of sampled data systems and it occurs when input frequencies close to the sampling frequency are applied. For the LTC1164-7 case at 100:1, an input signal whose frequency is in the range of fCLK ±3%, will be aliased back into the filter’s passband. 1164-7 F07 VS = ±7.5V fCLK = 1MHz fC = 20kHz (fCLK /fC) = 50:1 Figure 7. Eye Diagram Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC1164-7 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. J Package 14-Lead Ceramic DIP 0.200 (5.080) MAX 0.290 – 0.320 (7.366 – 8.128) 0.785 (19.939) MAX 0.005 (0.127) MIN 14 12 13 11 10 9 8 0.015 – 0.060 (0.381 – 1.524) 0.008 – 0.018 (0.203 – 0.460) 0.220 – 0.310 (5.588 – 7.874) 0.025 (0.635) RAD TYP 0° – 15° 1 0.385 ± 0.025 (9.779 ± 0.635) 0.038 – 0.068 (0.965 – 1.727) 0.100 ± 0.010 (2.540 ± 0.254) 0.014 – 0.026 (0.360 – 0.660) 2 3 4 5 6 7 0.098 (2.489) MAX 0.125 (3.175) MIN J14 0392 N Package 14-Lead Plastic DIP 0.300 – 0.325 (7.620 – 8.255) 0.045 – 0.065 (1.143 – 1.651) 0.015 (0.380) MIN 0.130 ± 0.005 (3.302 ± 0.127) ( +0.635 8.255 –0.381 ) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 0.260 ± 0.010 (6.604 ± 0.254) 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 0.770 (19.558) MAX 0.065 (1.651) TYP 0.075 ± 0.015 (1.905 ± 0.381) 0.018 ± 0.003 (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) MIN S Package 16-Lead Plastic SOL 0.398 – 0.413 (10.109 – 10.490) 0.291 – 0.299 (7.391 – 7.595) 0.005 (0.127) RAD MIN 0.010 – 0.029 × 45° (0.254 – 0.737) 16 0.093 – 0.104 (2.362 – 2.642) 15 14 13 12 11 10 9 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.394 – 0.419 (10.007 – 10.643) SEE NOTE 0.009 – 0.013 (0.229 – 0.330) SEE NOTE 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) TYP 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) TYP NOTE: PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 1 2 3 4 5 6 7 8 SOL16 0392 12 Linear Technology Corporation LT/GP 1292 10K REV 0 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1992