LINER LTC1064-7MJ

LTC1064-7
Linear Phase, 8th Order
Lowpass Filter
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FEATURES
DESCRIPTIO
■
The LTC®1064-7 is a clock-tunable monolithic 8th order
lowpass filter with linear passband phase and flat group
delay. The amplitude response approximates a maximally
flat passband while it exhibits steeper roll-off than an
equivalent 8th order Bessel filter. For instance, at twice the
cutoff frequency the filter attains 34dB attenuation (vs
12dB for Bessel), while at three times the cutoff frequency,
the filter attains 68dB attenuation (vs 30dB for Bessel).
The cutoff frequency of the LTC1064-7 is tuned via an
external TTL or CMOS clock.
■
■
■
■
■
■
■
■
Steeper Roll-Off Than 8th Order Bessel Filters
fCUTOFF up to 100kHz
Phase Equalized Filter in 14-Pin Package
Phase and Group Delay Response Fully Tested
Transient Response Exhibits 5% Overshoot and
No Ringing
Wide Dynamic Range
72dB THD or Better Throughout a 50kHz Passband
No External Components Needed
Available in 14-Pin DIP and 16-Pin SO Wide
Packages
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APPLICATIO S
■
■
■
The LTC1064-7 features wide dynamic range. With single
5V supply, the S/N + THD is 76dB. Optimum 92dB S/N is
obtained with ±7.5V supplies.
The clock-to-cutoff frequency ratio of the LTC1064-7 can
be set to 50:1 (Pin 10 to V +) or 100:1 (Pin 10 to V –).
Data Communication Filters
Time Delay Networks
Phase-Matched Filters
When the filter operates at clock-to-cutoff frequency ratio
of 50:1, the input is double-sampled to lower the risk of
aliasing.
The LTC1064-7 is pin-compatible with the LTC1064-X
series, LTC1164-7 and LTC1264-7.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Eye Diagram
80kHz Linear Phase Lowpass Filter
7.5V
14
2
13
3
12
4
LTC1064-7
11
5
10
6
9
7
8
–7.5V
CLK = 4MHz
7.5V
1V/DIV
VIN
1
VOUT
1064-7 TA01
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE fCLK LINE.
VS = ±7.5V
fCLK = 4MHz
RATIO = 50:1
1µs/DIV
1064-7 TA02
10647fb
1
LTC1064-7
W W
W
AXI U
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ABSOLUTE
RATI GS
(Note 1)
Total Supply Voltage (V + to V –) .......................... 16.5V
Power Dissipation ............................................. 400mW
Burn-In Voltage ................................................... 16.5V
Voltage at Any Input ..... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V)
Storage Temperature Range ................ – 65°C to 150°C
Operating Temperature Range
LTC1064-7C ....................................... – 40°C to 85°C
LTC1064-7M OBSOLETE .............. – 55°C to 125°C
Lead Temperature (Soldering, 10 sec)................. 300°C
U
W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
NC
1
14 RIN (A)
VIN
2
13 NC
GND
3
12 V –
V+
4
11 fCLK
GND
5
10 50/100
LP (A)
6
9
VOUT
INV (A)
7
8
NC
ORDER PART
NUMBER
LTC1064-7CN
J PACKAGE 14-LEAD CERAMIC DIP
TJMAX = 150°C, θJA = 65°C/W (J)
OBSOLETE PACKAGE
NC 1
16 RIN (A)
VIN 2
15 NC
GND 3
14 V –
V+
12 fCLK
11 50/100
NC 6
10 NC
LP (A) 7
9
INV (A) 8
LTC1064-7CJ
LTC1064-7MJ
LTC1064-7CSW
13 NC
4
GND 5
N PACKAGE
14-LEAD PLASTIC DIP
TJMAX = 110°C, θJA = 65°C/W (N)
ORDER PART
NUMBER
TOP VIEW
VOUT
SW PACKAGE
16-LEAD PLASTIC SO (WIDE)
TJMAX = 110°C, θJA = 85°C/W
Consider the N Package as an Alternate Source
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.VS = ±7.5V, RL = 10k, TA = 25°C, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz,
TTL or CMOS level (maximum clock rise and fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless
otherwise specified. The filter cutoff frequency is abbreviated as fCUTOFF or fC.
PARAMETER
Passband Gain
Gain at 0.5 fCUTOFF
Gain at 0.75 fCUTOFF
Gain at fCUTOFF
Gain at 2 fCUTOFF
Gain with fCLK = 20kHz
Gain with fCLK = 400kHz, VS = ±2.375V
Phase Factor (F )
Phase = 180° – F (f/fC)
(Note 2)
CONDITIONS
0.1Hz ≤ f ≤ 0.25 fCUTOFF
fTEST = 5kHz, (fCLK /fC) = 50:1
fTEST = 10kHz, (fCLK /fC) = 50:1
fTEST = 5kHz, (fCLK /f C) = 100:1
fTEST = 15kHz, (fCLK /fC) = 50:1
fTEST = 20kHz, (fCLK /fC) = 50:1
fTEST = 10kHz, (fCLK /fC) = 100:1
fTEST = 40kHz, (fCLK /fC) = 50:1
fTEST = 20kHz, (fCLK /fC) = 100:1
fTEST = 200Hz, (fCLK /fC) = 100:1
fTEST = 4kHz, (fCLK /fC) = 50:1
fTEST = 8kHz, (fCLK /fC) = 50:1
0.1Hz ≤ f ≤ fCUTOFF
(fCLK /fC) = 50:1
(fCLK /fC) = 100:1
(fCLK /fC) = 50:1
(fCLK /fC) = 100:1
●
●
●
●
●
●
●
●
●
●
MIN
TYP
MAX
UNITS
– 0.60
– 0.90
– 1.30
– 2.0
– 4.50
– 5.75
– 36.5
– 37.0
– 6.5
– 0.9
– 4.5
0.10
– 0.35
– 0.35
–1.0
– 3.4
– 4.5
– 34.0
– 34.5
– 4.3
– 0.3
– 3.3
0.65
0.15
1.25
– 0.35
– 2.50
– 3.75
– 31.75
– 31.75
– 3.5
0.25
– 2.00
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
422
414
430 ± 2.0
421 ± 2.5
430
421
437
429
Deg
Deg
Deg
Deg
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LTC1064-7
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±7.5V, RL = 10k, fCUTOFF = 10kHz or 20kHz, fCLK = 1MHz, TTL or
CMOS level (maximum clock rise and fall time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise
specified. The filter cutoff frequency is abbreviated as fCUTOFF or fC.
PARAMETER
Phase Nonlinearity
(Notes 2, 4)
Group Delay (td)
td = (F /360)(1/ fC)
(Note 3)
Group Delay Deviation
(Notes 3, 4)
Input Frequency Range (Table 9)
Maximum fCLK
Clock Feedthrough (f ≥ fCLK)
Wideband Noise
(1Hz ≤ f ≤ fCLK)
Input Impedance
Output DC Voltage Swing
(Note 5)
Output DC Offset
Output DC Offset TempCo
Power Supply Current
CONDITIONS
(fCLK /fC) = 50:1
(fCLK /fC) = 100:1
(fCLK /fC) = 50:1
(fCLK /fC) = 100:1
(fCLK /fC) = 50:1, f ≤ fCUTOFF
(fCLK /fC) = 100:1, f ≤ fCUTOFF
(fCLK /fC) = 50:1, f ≤ fCUTOFF
(fCLK /fC) = 100:1, f ≤ fCUTOFF
(fCLK /fC) = 50:1, f ≤ fCUTOFF
(fCLK /fC) = 100:1, f ≤ fCUTOFF
(fCLK /fC) = 50:1, f ≤ fCUTOFF
(fCLK /fC) = 100:1, f ≤ fCUTOFF
(fCLK /fC) = 50:1
(fCLK /fC) = 100:1
VS = 5V (AGND = 2V)
VS = ±5V
VS = ± 7.5V
50:1
VS = ±2.5V
VS = ±5V
VS = ± 7.5V
VS = ±2.375V
VS = ±5V
VS = ±7.5V
50:1, VS = ±5V
100:1, VS = ±5V
50:1, VS = ±5V
100:1, VS = ±5V
VS = ±2.375V, TA = 25°C
VS = ±5V, TA = 25°C
VS = ±7.5V, TA = 25°C
MIN
●
●
●
●
58.6
115.0
59.7 ± 0.5
117.0 ± 1.0
59.7
117.0
±1.0
±1.0
●
●
●
●
25
±1.0
±2.1
±3.0
<fCLK
<fCLK /2
2.0
3.5
5.0
200
95 ± 5%
105 ± 5%
115 ± 5%
40
±1.2
±3.2
±5.0
±150
±150
±200
±200
11
●
14
●
17
●
Power Supply Range
TYP
±1.0
±1.0
±2.375
MAX
± 2.0
± 2.0
60.7
119.0
± 2.0
± 2.0
70
±220
22
22
26
28
28
32
±8
UNITS
%
%
%
%
µs
µs
µs
µs
%
%
%
%
kHz
kHz
MHz
MHz
MHz
µVRMS
µVRMS
µVRMS
µVRMS
kΩ
V
V
V
mV
mV
µV/°C
µV/°C
mA
mA
mA
mA
mA
mA
V
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LTC1064-7
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input frequencies, f, are linearly phase shifted through the filter as
long as f ≤ fC; fC = cutoff frequency.
Figure 1 curve shows the typical phase response of an LTC1064-7
operating at fCLK = 1MHz, ratio = 50:1, fC = 20kHz and it closely matches
an ideal straight line. The phase shift is described by: phase shift =
180° – F (f/fC); f ≤ fC.
F is arbitrarily called the “phase factor” expressed in degrees. The phase
factor allows the calculation of the phase at a given frequency.
Example: The phase shift at 14kHz of the LTC1064-7 shown in Figure 1 is:
phase shift = 180° – 430° (14kHz/20kHz) ± nonlinearity = –121° ± 1% or
–121° ± 1.20°.
Note 3: Group delay and group delay deviation are calculated from the
measured phase factor and phase deviation specifications.
Note 4: Phase deviation and group delay deviation for LTC1064-7MJ is
±4%.
Note 5: The AC swing is typically 11VP-P, 7VP-P, 2.8VP-P, with ±7.5V, ±5V,
±2.5V Supply respectively. For more information refer to the THD + Noise
vs Input graphs.
180
fCLK = 1MHz
RATIO = 50:1
PHASE (DEG)
90
0
–90
–180
–270
–360
0
2
4
6 8 10 12 14 16 18 20
FREQUENCY (kHz)
1164-7 F01
Figure 1. Phase Response in the Passband (Note 2)
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LTC1064-7
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TYPICAL PERFOR A CE CHARACTERISTICS
Phase Factor vs fCLK
(Typical Unit)
Gain vs Frequency
10
485
485
VS = ±5V
(fCLK /fC) = 50:1
0
475
–10
–50
–60
–70
455
445
25°C
435
70°C
455
445
25°C
435
0°C
VS = ±5V
fCLK = 1MHz
TA = 25°C
425
415
0.5
100
0°C
425
415
1
10
FREQUENCY (kHz)
1.0
1.5
2.5
2.0
fCLK (MHz)
3.5
3.0
1064-7 G01
0.5
1.0
1.5
2.5
2.0
fCLK (MHz)
1064-7 G02
3.0
3.5
1064-7 G03
Phase Factor vs fCLK (Min and
Max Representative Units)
Phase Factor vs fCLK (Min and
Max Representative Units)
445
445
VS = ±5V
TA = 25°C
(fCLK /fC) = 50:1
VS = 5V
TA = 25°C
PINS 3, 5 AT 2V
(fCLK /fC) = 50:1
440
PHASE FACTOR
440
PHASE FACTOR
435
430
435
430
425
425
420
420
0.5
1.0
1.5
2.5
2.0
fCLK (MHz)
3.0
0.5
3.5
2.0
1.5
1.0
fCLK (MHz)
1064-7 G05
1064-7 G04
Passband Gain and Phase
Passband Gain and Phase
3
VS = ±5V
fCLK = 1MHz
(fCLK /fC) = 50:1
2
1
–1
120
2
60
1
0
0
– 60
–120
–2
PHASE
180
VS = ±5V
fCLK = 2MHz
(fCLK /fC) = 100:1
120
60
0
– 60
–1
GAIN
–120
–2
PHASE
–180
–3
–180
–4
–240
–4
–240
–5
–300
–5
–300
–360
8 10 12 14 16 18 20 22
FREQUENCY (kHz)
–6
–3
–6
2
4
6
1064-7 G06
2
4
6
PHASE (DEG)
GAIN
3
PHASE (DEG)
0
180
GAIN (dB)
–110
0.1
VS = ±5V
(fCLK /fC) = 100:1
465
PHASE FACTOR
PHASE FACTOR
–40
GAIN (dB)
GAIN (dB)
465
50:1
100:1
–30
–90
–100
475
70°C
–20
–80
Phase Factor vs fCLK
(Typical Unit)
–360
8 10 12 14 16 18 20 22
FREQUENCY (kHz)
1064-7 G07
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LTC1064-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Passband Gain vs Frequency and
fCLK at TA = 85°C
Passband Gain vs Frequency
and fCLK
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
2
2
GAIN (dB)
0
–1
D
A
–3
B C
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
3
1
–2
VS = ±7.5V
(fCLK /fC) = 50:1
4
E
D
A
–3
B C
100
10
FREQUENCY (kHz)
10
1
1000
Delay vs Frequency and fCLK
5
2
125
VS = SINGLE 5V
(fCLK /fC) = 50:1
4
3
2
GAIN (dB)
1
0
–1
–2
B
–1
–3
–3
–4
–4
–5
100
0
A
C D
B
10
FREQUENCY (kHz)
0
10
FREQUENCY (kHz)
100
2
VS = ±7.5V
VIN = 2VRMS
fCLK = 1MHz
(fCLK /fC) = 50:1
(100k RESISTOR
PIN 9 TO V – )
–45
–50
B
–55
–60
–50
–65
–70
–75
–55
–60
–65
–70
–75
–80
D
–85
–85
–90
–90
1
6
11
26
16
21
FREQUENCY (kHz)
31
36
–80
1
10
20
FREQUENCY (kHz)
1064-7 G14
72
VS = ±7.5V
VIN = 1VRMS
fCLK = 2.5MHz
(fCLK /fC) = 50:1
(100k RESISTOR
PIN 9 TO V – )
–45
50 C
0
62
THD + Noise vs Frequency
THD + NOISE (dB)
VS = ±5V
TA = 25°C
(fCLK /fC) = 100:1
THD + NOISE (dB)
100
22
52
32
42
FREQUENCY (kHz)
–40
–40
A. fCLK = 0.5MHz
B. fCLK = 1.5MHz
C. fCLK = 2.5MHz
D. fCLK = 3.5MHz
12
1064-7 G13
THD + Noise vs Frequency
Delay vs Frequency and fCLK
150
C
1064-7 G12
250
200
B
D
1064-7 G11
A
50
25
1
100
A. fCLK = 0.5MHz
B. fCLK = 1.5MHz
C. fCLK = 2.5MHz
D. fCLK = 3.5MHz
75
C D
–5
1
VS = ±5V
TA = 25°C
(fCLK /fC) = 50:1
A
1
–2
A
A. fCLK = 0.5MHz
B. fCLK = 1.0MHz
C. fCLK = 1.5MHz
D. fCLK = 2.0MHz
DELAY (µs)
3
A. fCLK = 0.5MHz
B. fCLK = 1.0MHz
C. fCLK = 1.5MHz
D. fCLK = 2.0MHz
100
1064-7 G10
Passband Gain vs Frequency and
fCLK at TA = 85°C
5
C D
10
FREQUENCY (kHz)
1064-7 G09
Passband Gain vs Frequency
and fCLK
VS = SINGLE 5V
TA = 25°C
(fCLK /fC) = 50:1
B
–5
100
10
FREQUENCY (kHz)
1064-7 G08
4
A
–4
1
1000
0
–1
–3
–5
–5
1
–2
E
–4
–4
GAIN (dB)
2
0
–2
A. fCLK = 0.5MHz
B. fCLK = 1.5MHz
C. fCLK = 2.5MHz
D. fCLK = 3.5MHz
3
1
–1
VS = ±5V
(fCLK /fC) = 50:1
4
GAIN (dB)
VS = ±7.5V
TA = 25°C
(fCLK /fC) = 50:1
3
GAIN (dB)
5
5
5
4
DELAY (µs)
Passband Gain vs Frequency and
fCLK at TA = 85°C
1064-7 G15
1
10
FREQUENCY (kHz)
50
1064-7 G16
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LTC1064-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
THD + Noise vs Frequency
– 40
–55
–60
–50
THD + NOISE (dB)
–50
VS = SINGLE 5V
VIN = 0.5VRMS
fCLK = 1MHz
(fCLK /fC) = 50:1
(PINS 3, 5 AT 2V)
–45
–65
–70
–75
–55
– 50
–60
–65
–70
–75
–65
–70
–75
–80
–85
–85
–85
–90
–90
1
20
10
–90
20
10
THD + Noise vs Input
THD + Noise vs Input
fIN = 1kHz
fCLK = 2MHz
(fCLK /fC) = 100:1
–45
–50
A
THD + Noise vs Input
A. VS = ±5V
B. VS = ±7.5V
–65
–70
–75
–50
B
–55
–60
–65
–70
–75
–55
–65
–70
–75
–80
–80
–85
–85
–85
1
–90
0.1
5
1
THD + Noise vs Input
48
–65
–70
–75
–80
4
3
44
POWER SUPPLY CURRENT (mA)
–60
–85
Power Supply Current vs
Power Supply Voltage
PHASE DIFFERENCE BETWEEN
ANY TWO UNITS (SAMPLE OF
50 REPRESENTATIVE UNITS)
VS ≥ ±5V
fCLK ≤ 2.5MHz
(fCLK /fC) = 50:1 OR 100:1
TA = 0°C TO 70°C
B
PHASE DIFFERENCE (DEG)
–55
A
2
1
A. PINS 3, 5 AT 2V
B. PINS 3, 5 AT 2.5V
–90
0.1
2
1064-7 G22
5
VS = SINGLE 5V
fIN = 1kHz
fCLK = 500kHz
(fCLK /fC) = 100:1
1
INPUT (VRMS)
Phase Matching vs Frequency
–40
–50
–90
0.1
5
1064-7 G21
1064-7 G20
–45
A. PINS 3, 5 AT 2V
B. PINS 3, 5 AT 2.5V
INPUT (VRMS)
INPUT (VRMS)
B
A
–60
–80
–90
0.1
VS = SINGLE 5V
fIN = 1kHz
fCLK = 1MHz
(fCLK /fC) = 50:1
–45
A
B
–60
5
–40
THD + NOISE (dB)
–55
A. VS = ±5V
B. VS = ±7.5V
THD + NOISE (dB)
–50
4
1064-7 G19
–40
fIN = 1kHz
fCLK = 1MHz
(fCLK /fC) = 50:1
(100k PIN 9
TO V –)
2
3
FREQUENCY (kHz)
1064-7 G18
–40
–45
1
FREQUENCY (kHz)
1064-7 G17
THD + NOISE (dB)
– 60
–80
FREQUENCY (kHz)
THD + NOISE (dB)
– 55
–80
1
VS = SINGLE 5V
VIN = 0.5VRMS
fCLK = 500kHz
(fCLK /fC) = 100:1
(PINS 3, 5 AT 2V)
–45
THD + NOISE (dB)
VS = ±5V
VIN = 1VRMS
fCLK = 1MHz
(fCLK /fC) = 50:1
(100k RESISTOR
PIN 9 TO V – )
–45
THD + NOISE (dB)
THD + Noise vs Frequency
THD + Noise vs Frequency
–40
–40
fCLK = 1MHz
40
36
32
28
24
–55°C
25°C
125°C
20
16
12
8
4
1
2
INPUT (VRMS)
1064-7 G23
0
0
0
0.2
0.6
0.8
0.4
FREQUENCY (fCUTOFF /FREQUENCY)
1.0
1064-7 G24
0 2
4 6 8 10 12 14 16 18 20 22 24
TOTAL POWER SUPPLY VOLTAGE (V)
1064-7 G25
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LTC1064-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Table 1. Passband Gain and Phase
VS = ±7.5V, (fCLK / fC) = 50:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 1MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
fCLK = 2MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
fCLK = 3MHz (Typical Unit)
0.000
15.000
30.000
45.000
60.000
fCLK = 4MHz (Typical Unit)
0.000
20.000
40.000
60.000
80.000
fCLK = 5MHz (Typical Unit)
0.000
25.000
50.000
75.000
100.000
GAIN (dB)
PHASE (DEG)
– 0.086
– 0.086
– 0.334
– 1.051
– 3.316
180.00
73.54
–33.60
–140.81
– 249.30
– 0.131
– 0.131
– 0.442
– 1.108
– 3.115
180.00
72.88
– 34.71
–141.99
– 250.45
– 0.156
– 0.156
– 0.459
– 0.941
– 2.508
180.00
72.54
– 35.01
– 141.95
– 250.53
– 0.121
– 0.121
– 0.292
– 0.476
– 1.539
180.00
72.12
– 35.75
– 142.92
– 252.63
– 0.045
– 0.045
– 0.006
0.185
– 0.356
180.00
70.85
– 38.25
– 146.77
– 259.27
Table 2. Passband Gain and Phase
VS = ±7.5V, (fCLK / fC) = 100:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 1MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
fCLK = 2MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
fCLK = 3MHz (Typical Unit)
0.000
7.500
15.000
22.500
30.000
GAIN (dB)
PHASE (DEG)
– 0.203
– 0.203
– 0.741
– 1.831
– 4.451
180.00
74.07
– 31.71
– 136.47
– 240.17
– 0.152
– 0.152
– 0.575
– 1.501
– 3.973
180.00
73.79
– 32.47
– 138.11
– 243.84
– 0.123
– 0.123
– 0.481
– 1.312
– 3.654
180.00
73.32
– 33.64
– 140.14
– 247.11
FREQUENCY (kHz)
fCLK = 4MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
fCLK = 5MHz (Typical Unit)
0.000
12.500
25.000
37.500
50.000
GAIN (dB)
PHASE (DEG)
– 0.116
– 0.116
– 0.436
– 1.171
– 3.353
180.00
72.49
– 35.21
– 142.33
– 250.12
– 0.097
– 0.097
– 0.351
– 0.951
– 2.999
180.00
71.00
– 38.08
– 146.51
– 256.13
Table 3. Passband Gain and Phase
VS = ±5V, (fCLK / fC) = 50:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 0.5MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
fCLK = 1MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
fCLK = 1.5MHz (Typical Unit)
0.000
7.500
15.000
22.500
30.000
fCLK = 2MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
fCLK = 2.5MHz (Typical Unit)
0.000
12.500
25.000
37.500
50.000
fCLK = 3MHz (Typical Unit)
0.000
15.000
30.000
45.000
60.000
GAIN (dB)
PHASE (DEG)
– 0.081
– 0.081
– 0.345
– 1.063
– 3.283
180.00
73.71
– 33.31
– 140.36
– 248.52
– 0.071
– 0.071
– 0.322
– 1.036
– 3.284
180.00
73.44
– 33.83
– 141.13
– 249.68
– 0.095
– 0.095
– 0.392
– 1.075
– 3.155
180.00
73.03
– 34.53
– 141.89
– 250.45
– 0.127
– 0.127
– 0.447
– 1.041
– 2.856
180.00
72.81
– 34.70
– 141.77
– 250.24
– 0.126
– 0.126
– 0.411
– 0.864
– 2.397
180.00
72.61
– 34.91
– 141.88
– 250.62
– 0.102
– 0.102
– 0.292
– 0.546
– 1.769
180.00
72.23
– 35.64
– 142.96
– 252.73
10647fb
8
LTC1064-7
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TYPICAL PERFOR A CE CHARACTERISTICS
Table 3. Passband Gain and Phase
VS = ±5V, (fCLK / fC) = 50:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 3.5MHz (Typical Unit)
0.000
17.500
35.000
52.500
70.000
GAIN (dB)
– 0.054
– 0.054
– 0.108
– 0.137
– 1.104
Table 5. Passband Gain and Phase
VS = Single 5V, (fCLK / fC) = 50:1, TA = 25°C
PHASE (DEG)
180.00
71.07
– 38.00
– 146.68
– 258.97
Table 4. Passband Gain and Phase
VS = ±5V, (fCLK / fC) = 100:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 0.5MHz (Typical Unit)
0.000
1.250
2.500
3.750
5.000
fCLK = 1MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
GAIN (dB)
PHASE (DEG)
– 0.186
– 0.186
– 0.726
– 1.805
– 4.402
180.00
74.10
– 31.65
– 136.48
– 240.33
– 0.184
– 0.184
– 0.712
– 1.785
– 4.387
180.00
74.02
– 31.80
– 136.61
– 240.43
fCLK = 1.5MHz (Typical Unit)
0.000
– 0.145
3.750
– 0.145
7.500
– 0.596
11.250
– 1.556
15.000
– 4.047
fCLK = 2MHz (Typical Unit)
0.000
– 0.116
5.000
– 0.116
10.000
– 0.494
15.000
– 1.361
20.000
– 3.761
fCLK = 2.5MHz (Typical Unit)
0.000
– 0.101
6.250
– 0.101
12.500
– 0.452
18.750
– 1.273
25.000
– 3.611
fCLK = 3MHz (Typical Unit)
0.000
– 0.105
7.500
– 0.105
15.000
– 0.445
22.500
– 1.228
30.000
– 3.509
fCLK = 3.5MHzMHz (Typical Unit)
0.000
– 0.104
8.750
– 0.104
17.500
– 0.437
26.250
– 1.188
35.000
– 3.478
180.00
73.84
– 32.32
– 137.73
– 242.95
180.00
73.64
– 32.93
– 139.03
– 245.57
180.00
73.17
– 33.93
– 140.58
– 247.80
180.00
72.36
– 35.47
– 142.70
– 250.58
180.00
70.81
– 38.39
– 146.85
– 256.10
FREQUENCY (kHz)
fCLK = 0.5MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
fCLK = 1MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
fCLK = 1.5MHz (Typical Unit)
0.000
7.500
15.000
22.500
30.000
fCLK = 2MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
GAIN (dB)
PHASE (DEG)
– 0.134
– 0.134
– 0.391
– 1.109
– 3.351
180.00
73.52
– 33.67
– 140.92
– 249.32
– 0.148
– 0.148
– 0.423
– 1.111
– 3.241
180.00
73.07
– 34.63
– 142.25
– 251.03
– 0.157
– 0.157
– 0.456
– 0.981
– 2.687
180.00
72.73
– 34.83
– 142.08
– 251.09
– 0.188
– 0.188
– 0.304
– 0.513
– 1.824
180.00
71.37
– 37.52
– 146.11
– 257.46
Table 6. Passband Gain and Phase
VS = Single 5V, (fCLK / fC) = 100:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 0.5MHz (Typical Unit)
0.000
1.250
2.500
3.750
5.000
fCLK = 1MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
fCLK = 1.5MHz (Typical Unit)
0.000
3.750
7.500
11.250
15.000
fCLK = 2MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
GAIN (dB)
PHASE (DEG)
– 0.243
– 0.243
– 0.776
– 1.861
– 4.483
180.00
73.91
– 31.98
– 136.98
– 240.90
– 0.208
– 0.208
– 0.678
– 1.679
– 4.221
180.00
73.76
– 32.47
– 137.87
– 242.65
– 0.115
– 0.115
– 0.473
– 1.314
– 3.715
180.00
73.26
– 33.73
– 140.40
– 247.66
– 0.209
– 0.209
– 0.499
– 1.281
– 3.695
180.00
71.18
– 37.85
– 146.27
– 255.38
10647fb
9
LTC1064-7
U
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PI FU CTIO S
Power Supply Pins (4, 12)
+
–
The V (Pin 4) and the V (Pin 12) should be bypassed with
a 0.1µF capacitor to an adequate analog ground. The
filter’s power supplies should be isolated from other
digital or high voltage analog supplies. A low noise linear
supply is recommended. Using a switching power supply
will lower the signal-to-noise ratio of the filter. The supply
during power-up should have a slew rate less than 1V/µs.
When V + is applied before V – and V – is allowed to go
above ground, a signal diode should clamp V – to prevent
latch-up. Figures 2 and 3 show typical connections for
dual and single supply operation.
V–
VIN
1
14
2
13
3
12
4
V+
0.1µF
LTC1064-7
5
10
6
9
7
8
Table 7. Clock Source High and Low Threshold Levels
0.1µF
200Ω
11
CLOCK SOURCE
V+
+
GND
DIGITAL SUPPLY
VOUT
VIN
13
3
12
11
200Ω
5
10
V+
6
9
7
8
4
V+
0.1µF
10k
10k
14
2
LTC1064-7
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ± 2.5V
Single Supply = 12V
Single Suppl = 5V
HIGH LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
LOW LEVEL
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
1064-7 F02
Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 50:1
1
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
level threshold values for a dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.1µs. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤ 1µs). The clock signal should be routed from the
right side of the IC package and perpendicular to it to avoid
coupling to any input or output analog signal path. A 200Ω
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
CLOCK SOURCE
+
GND
DIGITAL SUPPLY
+
1µF
VOUT
1064-7 F03
Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 50:1
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, Pin 3 should be connected to the analog
ground plane. For single supply operation pin 3 should be
biased at 1/2 supply and should be bypassed to the analog
ground plane with at least a 1µF capacitor (Figure 3). For
single 5V operation at the highest fCLK of 2MHz, Pin 3
should be biased at 2V. This minimizes passband gain and
phase variations.
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V +
gives a 50:1 ratio and Pin 10 at V – gives a 100:1 ratio. For
single supply operation the ratio is 50:1 when Pin 10 is at
V + and 100:1 when Pin 10 is at ground. When Pin 10 is not
tied to ground, it should be bypassed to analog ground
10647fb
10
LTC1064-7
U
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PI FU CTIO S
with a 0.1µF capacitor. If the DC level at Pin 10 is switched
mechanically or electrically at slew rates greater than
1V/µs while the device is operating, a 10k resistor should
be connected between Pin 10 and the DC source.
Filter Input Pin (2)
The input pin is connected internally through a 40k resistor tied to the inverting input of an op amp.
Filter Output Pins (9, 6)
Pin 9 is the specified output of the filter; it can typically
source 3mA and sink 1mA. Driving coaxial cables or
resistive loads less than 20k will degrade the total harmonic distortion of the filter. When evaluating the device’s
distortion an output buffer is required. A noninverting
buffer, Figure 4, can be used provided that its input
common mode range is well within the filter’s output
swing. Pin 6 is an intermediate filter output providing an
unspecified 6th order lowpass filter. Pin 6 should not be
loaded.
NC Pins (1, 5, 8, 13)
Pins 1, 5, 8 and 13 are not connected to any internal circuit
point on the device and should preferably be tied to analog
ground.
–
1k
+
LT1220
1064-7 F04
Figure 4. Buffer for Filter Output
W
U
UO
S I FOR ATIO
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pin (9). The clock feedthrough is tested with the
input pin (2) grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques the values of the clock feedthrough are shown
in Table 8.
Table 8. Clock Feedthrough
VS
Single 5V
±5V
±7.5V
Pins 7 and 14 should be connected together. In a printed
circuit board the connection should be done under the IC
package through a short trace surrounded by the analog
ground plane.
U
APPLICATI
External Connection Pins (7, 14)
50:1
90µVRMS
100µVRMS
120µVRMS
100:1
100µVRMS
300µVRMS
650µVRMS
Note: The clock feedthrough at single 5V is imbedded in the
wideband noise of the filter. Clock waveform is a square wave.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple R/C lowpass network at the output of
the filter pin (9). This R/C will completely eliminate any
switching transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering. For instance, the
LTC1064-7 wideband noise at ±5V supply is 105µVRMS,
95µVRMS of which have frequency contents from DC up to
the filter’s cutoff frequency. The total wideband noise
(µVRMS) is nearly independent of the value of the clock.
The clock feedthrough specifications are not part of the
wideband noise.
10647fb
11
LTC1064-7
W
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APPLICATI
S I FOR ATIO
Speed Limitations
Transient Response
Table 9. Maximum VIN vs VS and Clock
POWER SUPPLY
±7.5V
±5V
Single 5V
MAXIMUM fCLK
5.0MHz
4.5MHz
4.0MHz
≥ 3.5MHz
3.5MHz
≥ 3.0MHz
2.0MHz
MAXIMUM VIN
1.8VRMS (fIN > 80kHz)
2.3VRMS (fIN > 80kHz)
2.7VRMS (fIN > 80kHz)
1.4VRMS (fIN > 500kHz)
1.6VRMS (fIN > 80kHz)
0.7VRMS (fIN > 400kHz)
0.5VRMS (fIN > 250kHz)
2V/DIV
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
50µs/DIV
1064-7 F05
VS = ± 7.5V, fIN = 2kHz ± 3V
fCLK = 1MHz, RATIO = 50:1
Figure 5.
Table 10. Transient Response of LTC Lowpass Filters
DELAY
RISE
SETTLING
TIME*
TIME** TIME***
LOWPASS FILTER
(SEC)
(SEC)
(SEC)
LTC1064-3 Bessel
0.50/fC 0.34/fC
0.80/fC
LTC1164-5 Bessel
0.43/fC 0.34/fC
0.85/fC
LTC1164-6 Bessel
0.43/fC 0.34/fC
1.15/fC
LTC1264-7 Linear Phase
1.15/fC
0.36/fC
2.05/fC
LTC1164-7 Linear Phase
1.20/fC
0.39/fC
2.2/fC
LTC1064-7 Linear Phase
1.20/fC
0.39/fC
2.2/fC
LTC1164-5 Butterworth
0.80/fC
0.48/fC
2.4/fC
LTC1164-6 Elliptic
0.85/fC
0.54/fC
4.3/fC
LTC1064-4 Elliptic
0.90/fC
0.54/fC
4.5/fC
LTC1064-1 Elliptic
0.85/fC
0.54/fC
6.5/fC
* To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5%
OVERSHOOT
(%)
0.5
0
1
5
5
5
11
18
20
20
ts
90%
50%
10%
190 (or 210)
195 (or 205)
196 (or 204)
197 (or 203)
198 (or 202)
199.5 (or 200.5)
100:1, fCUTOFF = 1kHz
97 (or 103)
97.5 (or 102.5)
98 (or 102)
98.5 (or 101.5)
99 (or 101)
99.5 (or 100.5)
OUTPUT LEVEL
(Relative to Input,
0dB = 1VRMS)
(dB)
td
tr
0.39
±5%
fCUTOFF
2.2
SETTLING TIME (ts) =
±5%
f
(TO 1% of OUTPUT) CUTOFF
RISE TIME (tr) =
Table 11. Aliasing (fCLK = 100kHz)
INPUT FREQUENCY
(VIN = 1VRMS,
fIN = fCLK ± fOUT)
(kHz)
50:1, fCUTOFF = 2kHz
OUTPUT
INPUT
1.2
DELAY TIME (td) = GROUP DELAY ≈
fCUTOFF
(TO 50% OF OUTPUT)
OUTPUT FREQUENCY
(Aliased Frequency
fOUT = ABS [fCLK ± fIN])
(kHz)
1064-7 F06
Figure 6.
Aliasing
–76.1
– 51.9
– 36.3
– 18.4
– 3.0
– 0.2
10.0
5.0
4.0
3.0
2.0
0.5
–74.2
– 53.2
– 36.9
– 19.6
– 5.2
– 0.7
3.0
2.5
2.0
1.5
1.0
0.5
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1064-7 case
at 100:1, an input signal whose frequency is in the range
of fCLK ±3%, will be aliased back into the filter’s passband.
If, for instance, an LTC1064-7 operating with a 100kHz
clock and 1kHz cutoff frequency receives a 98kHz, 10mV
input signal, a 2kHz, 143µVRMS alias signal will appear at
its output. When the LTC1064-7 operates with a clock-tocutoff frequency of 50:1, aliasing occurs at twice the clock
frequency. Table 11 shows details.
10647fb
12
LTC1064-7
U
PACKAGE DESCRIPTIO
J Package
14-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
.005
(0.127)
MIN
.785
(19.939)
MAX
14
13
12
11
10
9
8
.220 – .310
(5.588 – 7.874)
.025
(0.635)
RAD TYP
1
2
3
4
5
6
7
.300 BSC
(7.62 BSC)
.200
(5.080)
MAX
.015 – .060
(0.381 – 1.524)
.008 – .018
(0.203 – 0.457)
0° – 15°
.045 – .065
(1.143 – 1.651)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE
OR TIN PLATE LEADS
.014 – .026
(0.360 – 0.660)
.100
(2.54)
BSC
.125
(3.175)
MIN
J14 0801
OBSOLETE PACKAGE
10647fb
13
LTC1064-7
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PACKAGE DESCRIPTIO
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.770*
(19.558)
MAX
14
13
12
11
10
9
8
1
2
3
4
5
6
7
.255 ± .015*
(6.477 ± 0.381)
.130 ± .005
(3.302 ± 0.127)
.300 – .325
(7.620 – 8.255)
.045 – .065
(1.143 – 1.651)
.020
(0.508)
MIN
.065
(1.651)
TYP
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
+0.889
8.255
–0.381
NOTE:
1. DIMENSIONS ARE
)
.120
(3.048)
MIN
.005
(0.127) .100
MIN (2.54)
BSC
.018 ± .003
(0.457 ± 0.076)
N14 1103
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
10647fb
14
LTC1064-7
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PACKAGE DESCRIPTIO
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.398 – .413
(10.109 – 10.490)
NOTE 4
16
N
15
14
13
12
11 10
9
N
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
1
.005
(0.127)
RAD MIN
.009 – .013
(0.229 – 0.330)
.291 – .299
(7.391 – 7.595)
NOTE 4
.010 – .029 × 45°
(0.254 – 0.737)
3
4
5
6
7
.093 – .104
(2.362 – 2.642)
8
.037 – .045
(0.940 – 1.143)
0° – 8° TYP
NOTE 3
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
2
.050
(1.270)
BSC
.004 – .012
(0.102 – 0.305)
.014 – .019
(0.356 – 0.482)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
S16 (WIDE) 0502
10647fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1064-7
U
TYPICAL APPLICATIO
80kHz Linear Phase Lowpass Filter
7.5V
14
2
13
3
12
4
11
LTC1064-7
5
10
6
9
7
8
–7.5V
CLK = 4MHz
7.5V
1V/DIV
VIN
1
Eye Diagram
VOUT
1064-7 TA01
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE fCLK LINE.
VS = ±7.5V
fCLK = 4MHz
RATIO = 50:1
1064-7 TA02
1µs/DIV
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1064
Universal Filter Building Block
Allows for Bandpass (Up to 50kHz) Using External Resistors
LTC1064-1/2/3/4
8th Order Low Pass Filters, FO Max = 100kHz
Elliptic, Butterworth, Bessel, Cauer
LTC1164
Universal Filter Building Block
Allows for Bandpass (Up to 20kHz) Using External Resistors
LTC1164-5/6/7
8th Order Low Pass Filters, FO Max = 20kHz
Butterworth, Bessel or Elliptic
LTC1264
Universal Filter Building Block
Allows for Bandpass (Up to 100kHz) Using External Resistors
LTC1264-7
8th Order Low Pass Filter, FO Max = 200kHz
Flat Group Delay, High Speed Lowpass Filter
LT6600-2.5
Low Noise Differential Amp and 10MHz Lowpass
55µVRMS Noise 100kHz to 10MHz 3V Supply
LT6600-10
Low Noise Differential Amp and 20MHz Lowpass
86µVRMS Noise 100kHz to 20MHz 3V Supply
10647fb
16
Linear Technology Corporation
LT/LT 0905 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1992