LTC1876 High Efficiency, 2-Phase, Dual Synchronous Step-Down Switching Controller and Step-Up Regulator DESCRIPTIO U FEATURES The LTC®1876 is a high performance triple output switching regulator. It incorporates a dual step-down switching controller that drives all N-channel synchronous power MOSFET stages. A step-up regulator with an internal 1A, 36V switch provides the third output. Step-Down Controller ■ Out-of-Phase Controllers Reduce Required Input Capacitance and Power Supply Induced Noise ■ Power Good Output Voltage Indicator ■ OPTI-LOOPTM Compensation Minimizes C OUT ■ DC Programmed Fixed Frequency 150kHz to 300kHz ■ Wide V Range: 3.5V to 36V Operation IN ■ Very Low Dropout Operation: 99% Duty Cycle ■ Adjustable Soft-Start Current Ramping ■ Latched Short-Circuit Shutdown with Defeat Option ■ Remote Output Voltage Sense and OV Protection ■ 5V and 3.3V Standby Regulators ■ Selectable Const. Freq. or Burst ModeTM Operation Step-Up Regulator ■ High Operating Switching Frequency of 1.2MHz ■ Low Internal V CESAT Switch: 400mV @ 1A, VIN = 3V ■ Wide V Range: 2.6V to 16V Operation IN ■ High Output Voltage: Up to 34V The step-down controllers minimize power loss and noise by operating the output stage of each controller out of phase. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. A RUN/SS pin for each controller provides both soft-start and an optional timed, short-circuit shutdown that can be configured to latch off one or both controllers. Current foldback provides additional short-circuit protection. In an overvoltage condition, the bottom MOSFET is latched on until VOUT returns to normal. The FCB pin can be used to inhibit Burst Mode operation or to enable regulation of a secondary output voltage. U APPLICATIO S ■ ■ ■ The step-up regulator operates at 1.2MHz, allowing the use of tiny low cost capacitors and inductors. In addition, its internal 1A switch allows high current outputs to be generated. Its current mode control scheme provides excellent line and load regulation. 3.3V Input Step-Down Converter Notebook and Palmtop Computers, PDAs Battery-Operated Digital Devices , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO VIN 5.2V TO 28V 33µF 35V ALUM 10µH + 10µF 35V CER 1µF CER M3 0.1µF 6.3µH + INTVCC AUXVIN TG2 BOOST2 BG2 4.7µF 10V M1 TG1 BOOST1 SW2 M4 VIN 10µF 20V 0.1µF SW1 LTC1876 VOUT3 12V 200mA + 6.8µH M2 BG1 AUXSW PGND PGOOD 0.01Ω 1000pF VOUT2 3.3V 5A + 56µF 4V SP 63.4k 1% 20k 1% 15k AUXSD SENSE2+ SENSE1+ SENSE2– SENSE1– VOSENSE2 VOSENSE1 ITH2 220pF AUXVFB 0.01Ω 105k 1% ITH1 RUN/SS2 SGND RUN/SS1 0.1µF 86.6k, 1% 1000pF 0.1µF 220pF 15k 10.2k 1% 20k 1% + VOUT1 5V 4A 47µF 6.3V SP M1, M2, M3, M4: FDS6680A Figure 1. High Efficiency Triple 5V/3.3V/12V Power Supply 1876 TA01 1876fa 1 LTC1876 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN)......................... 36V to –0.3V Topside Driver Voltages (BOOST1, BOOST2) ................................... 42V to –0.3V Switch Voltage (SW1, SW2) ......................... 36V to –5V INTVCC, EXTVCC, RUN/SS1, RUN/SS2, PGOOD, (BOOST1-SW1), (BOOST2-SW2), ...............7V to – 0.3V SENSE1+, SENSE2+, SENSE1–, SENSE2 – Voltages ................................... (1.1)INTVCC to – 0.3V FREQSET, STBYMD, FCB, PGOOD Voltages ..................................................7V to – 0.3V ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ... 2.7V to –0.3V Peak Output Current <10µs (TG1, TG2, BG1, BG2) ... 3A INTVCC Peak Output Current ................................ 50mA AUXVIN .................................................................. 16V to –0.3V AUXSD ..................................................................... 10V AUXSW ..................................................... 36V to –0.3V AUXVFB Voltage ....................................... 2.5V to –0.3V Current into AUXVFB ....................................................... ±1mA Operating Temperature Range (Note 2) ...–40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RUN/SS1 1 36 PGOOD SENSE1+ 2 35 TG1 SENSE1– 3 34 SW1 VOSENSE1 4 33 BOOST1 FREQSET 5 32 VIN STBYMD 6 31 BG1 FCB 7 30 EXTVCC ITH1 8 29 INTVCC SGND 9 28 PGND LTC1876EG 3.3VOUT 10 IITH2 11 27 BG2 VOSENSE2 12 25 SW2 SENSE2– 13 24 TG2 SENSE2+ 14 23 RUN/SS2 26 BOOST2 AUXSGND 15 22 AUXSD AUXVFB 16 21 AUXVIN AUXSW 17 20 AUXPGND AUXSW 18 19 AUXPGND G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V, AUXVIN = 3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.792 0.800 0.808 V –5 –50 nA 0.002 0.02 %/V 0.1 –0.1 0.5 –0.5 % % Main Control Loops VOSENSE1, 2 Regulated Feedback Voltage ITH1, 2 Voltage = 1.2V (Note 4) IVOSENSE1, 2 Feedback Current (Note 4) VREFLNREG Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 4) VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ∆ITH Voltage = 1.2V to 2V gm1, 2 Transconductance Amplifier gm ITH1, 2 = 1.2V; Sink/Source 5µA; (Note 4) gmOL1, 2 Transconductance Amplifier GBW ITH1, 2 = 1.2V; (Note 4) IQ Input DC Supply Current Normal Mode Standby Shutdown (Note 5) VIN = 15V; EXTVCC Tied to VOUT1; VOUT1 = 5V VRUN/SS1, 2 = 0V, VSTBYMD > 2V VRUN/SS1, 2 = 0V, VSTBYMD = Open VFCB Forced Continuous Threshold IFCB Forced Continuous Current VFCB = 0.85V VBINHIBIT Burst Inhibit (Constant Frequency) Threshold Measured at FCB pin ● ● ● 1.3 mmho 3 350 125 20 ● MHz 35 µA µA µA 0.76 0.800 0.84 V –0.3 –0.18 –0.1 µA 4.3 4.8 V 1876fa 2 LTC1876 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V, AUXVIN = 3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS UVLO Undervoltage Lockout VIN Ramping Down ● VOVL Overvoltage Feedback Threshold Measured at VOSENSE1, 2 ● ISENSE Sense Pins Total Source Current (Each Channel); VSENSE1–, 2 – = VSENSE1+, 2+ = 0V VSTBYMD MS Master Shutdown Threshold VSTBYMD Ramping Down VSTBYMD KA Keep-Alive Power On-Threshold VSTBYMD Ramping Up, RUNSS1, 2 = 0V DFMAX Maximum Duty Factor In Dropout 98 99.4 % IRUN/SS1, 2 Soft-Start Charge Current VRUN/SS1, 2 = 1.9V 0.5 1.2 µA VRUN/SS1, VRUN/SS2 Rising 1.0 1.5 1.9 4.1 4.5 V 2 4 µA VRUN/SS1, 2 ON RUN/SS Pin ON Threshold VRUN/SS1, 2 LT RUN/SS Pin Latchoff Arming Threshold VRUN/SS1, VRUN/SS2 Rising from 3V ISCL1, 2 RUN/SS Discharge Current Soft Short Condition VOSENSE1, 2 = 0.5V; VRUN/SS1, 2 = 4.5V ISDLHO Shutdown Latch Disable Current VOSENSE1, 2 =0.5V VSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2 = 0.7V, VSENSE1–, 2– = 5V TG1, 2 tr TG1, 2 tf TG Transition Time: Rise Time Fall Time BG1, 2 tr BG1, 2 tf TG/BG t1D MIN TYP MAX 3.5 4 V 0.84 0.86 0.88 V –85 –60 µA 0.4 0.6 V 1.5 0.5 2 UNITS V V 1.6 5 µA 75 88 mV CLOAD = 3300pF CLOAD = 3300pF 50 50 90 90 ns ns BG Transition Time: Rise Time Fall Time CLOAD = 3300pF CLOAD = 3300pF 40 40 90 80 ns ns Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 90 ns ● 62 BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver 90 ns tON(MIN) Minimum ON-Time Tested with a Square Wave (Note 7) 180 ns INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V 5.0 5.2 V VLDO INT INTVCC Load Regulation ICC = 0 to 20mA, VEXTVCC = 4V 4.8 0.2 1.0 % VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 80 160 mV VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive VLDOHYS EXTVCC Hysteresis ● 4.5 4.7 V 0.2 V Oscillator fOSC Oscillator frequency VFREQSET = Open (Note 8) 190 220 250 kHz fLOW Lowest Frequency VFREQSET = 0V 120 140 160 kHz fHIGH Highest Frequency VFREQSET = 2.4V 280 310 360 kHz IFREQSET FREQSET Input Current VFREQSET = 2.4V –2 –1 µA 1876fa 3 LTC1876 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V, AUXVIN = 3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 3.25 3.35 3.45 V 3.3V Linear Regulator V3.3OUT 3.3V Regulator Output Voltage No Load V3.3IL 3.3V Regulator Load Regulation I3.3 = 0mA to 10mA 0.5 2 % V3.3VL 3.3V Regulator Line Regulation 6V < VIN < 30V 0.05 0.2 % VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA VPG PGOOD Trip Level, Either Controller VOSENSE with Respect to Set Output Voltage VOSENSE Ramping Negative VOSENSE Ramping Positive –7.5 7.5 –9.5 9.5 % % 2.4 2.6 V 1.26 1.28 V 120 360 nA ● PGOOD Output –6 6 Aux Output AUXVINMIN AUX Minimum Operating Voltage ● AUXVFB AUX Regulated Feedback Voltage ● AUXIFB AUX Feedback Pin Bias Current ● AUXIQ AUX Input DC Supply Current Normal Mode Shutdown VAUXSD = 2.4V, Not Switching VAUXSD = 0V 4 0.01 1 mA µA AUXVLINEREG AUX Line Regulation 2.6V ≤ AUXVIN ≤ 16V 0.01 0.05 %/V AUXfOSC AUX Oscillator Frequency ● 0.8 1.2 1.6 MHz AUXDCMAX AUX Oscillator Maximum Duty Cycle ● 84 86 AUXILIMIT AUX Switch Current Limit 1 1.4 2 AUXVCESAT AUX Switch Saturation Voltage ISW = 900mA (Note 10) 330 550 mV AUXILEAKAGE AUX Switch Leakage Current VSW = 5V 0.01 1 µA AUXVAUXSD AUX Shutdown Input Voltage AUX Shutdown Upper Trip Point AUX Shutdown Lower Trip Point 0.5 V V 32 0.1 µA µA IAUXSD (Note 9) AUXSD Pin Bias Current VAUXSD = 3V VAUXSD = 0V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1876E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1876EG: TJ = TA + (PD • 95°C/W) Note 4: The LTC1876 is tested in a feedback loop that servos VITH1, 2 to a specified voltage and measures the resultant VOSENSE1, 2. 1.23 % 2.4 16 0.01 A Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peakto-peak ripple current ≥40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 8: VFREQSET pin internally tied to 1.19V reference through a large resistance. Note 9: Current limit guaranteed by design and/or correlation to static test. Note 10: 100% tested at wafer level. 1876fa 4 LTC1876 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Output Current (Figure 1) Efficiency vs Output Current and Mode (Figure 1) 100 100 Burst Mode OPERATION 90 100 FORCED CONTINUOUS MODE 50 40 CONSTANT FREQUENCY (BURST DISABLE) 30 20 90 VIN = 10V VIN = 15V 80 EFFICIENCY (%) 70 60 VIN = 20V 70 60 VIN = 15V VOUT = 5V 10 0 0.001 10 1000 5.05 400 STANDBY INTVCC AND EXTVCC SWITCH VOLTAGE (V) EXTVCC VOLTAGE DROP (mV) SUPPLY CURRENT (µA) BOTH CONTROLLERS ON 200 150 100 50 SHUTDOWN 0 5 20 15 10 25 INPUT VOLTAGE (V) 30 0 35 0 10 30 20 CURRENT (mA) 40 1876 G04 4.90 4.85 4.80 EXTVCC SWITCHOVER THRESHOLD 4.75 4.70 – 50 – 25 50 50 25 75 0 TEMPERATURE (°C) 100 125 1876 G06 Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback) 80 75 70 5.0 60 4.9 4.8 4.7 50 VSENSE (mV) VSENSE (mV) INTVCC VOLTAGE (V) 4.95 Maximum Current Sense Threshold vs Duty Factor ILOAD = 1mA INTVCC VOLTAGE 5.00 1876 G05 Internal 5V LDO Line Regulation 5.1 35 INTVCC and EXTVCC Switch Voltage vs Temperature 250 600 25 15 INPUT VOLTAGE (V) 1876 G03 EXTVCC Voltage Drop 800 5 1876 G02 VIN Supply Current vs Input Voltage and Mode (Figure 1) 0 70 50 0.1 0.01 1 OUTPUT CURRENT (A) 1876 G01 200 80 60 50 0.001 10 0.1 0.01 1 OUTPUT CURRENT (A) VOUT = 5V IOUT = 3A VIN = 7V 90 EFFICIENCY (%) EFFICIENCY (%) 80 VOUT = 5V Efficiency vs Input Voltage (Figure 1) 50 40 30 25 4.6 20 4.5 10 4.4 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35 0 0 0 1876 G07 20 40 60 DUTY FACTOR (%) 80 100 50 0 100 25 75 PERCENT ON NOMINAL OUTPUT VOLTAGE (%) 1876 G09 1876 G08 1876fa 5 LTC1876 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Current Sense Threshold vs Sense Common Mode Voltage Maximum Current Sense Threshold vs VRUN/SS (Soft-Start) 80 80 VSENSE(CM) = 1.6V 90 80 70 76 60 40 VSENSE (mV) 60 VSENSE (mV) VSENSE (mV) Current Sense Threshold vs ITH Voltage 72 68 50 40 30 20 10 20 0 64 –10 –20 0 0 1 2 3 4 5 60 6 1 3 4 2 COMMON MODE VOLTAGE (V) 0 VRUN/SS (V) 1876 G10 2.5 FCB = 0V VIN = 15V FIGURE 1 1 1.5 VITH (V) 2 2.5 SENSE Pins Total Source Current 100 VOSENSE = 0.7V 2.0 50 ISENSE (µA) –0.1 VITH (V) NORMALIZED VOUT (%) 0.5 1876 G12 VITH vs VRUN/SS –0.2 0 1876 G11 Load Regulation (Controller) 0.0 –30 5 1.5 1.0 –0.3 0 –50 0.5 –0.4 0 1 3 2 LOAD CURRENT (A) 0 4 5 0 1 2 3 4 –100 80 RUN/SS Current vs Temperature 1.8 72 50 25 0 75 TEMPERATURE (°C) 100 125 1876 G16 VOUT = 5V 1.6 33 RUN/SS CURRENT (µA) CURRENT SENSE INPUT CURRENT (µA) 74 6 1876 G15 35 76 4 VSENSE COMMON MODE VOLTAGE (V) Current Sense Pin Input Current vs Temperature 78 2 0 1876 G14 Maximum Current Sense Threshold vs Temperature VSENSE (mV) 6 VRUN/SS (V) 1876 G13 70 –50 –25 5 31 29 27 1.4 1.2 1.0 0.8 0.6 0.4 0.2 25 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 1876 G17 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1876 G18 1876fa 6 LTC1876 U W TYPICAL PERFOR A CE CHARACTERISTICS EXTVCC and Switch Resistance vs Temperature Undervoltage Lockout vs Temperature (Controller) Oscillator Frequency vs Temperature (Controller) 10 3.50 350 UNDERVOLTAGE LOCKOUT (V) 300 8 FREQUENCY (kHz) 6 4 250 VFREQSET = OPEN 200 VFREQSET = 0V 150 100 2 50 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 0 – 50 – 25 125 50 25 75 0 TEMPERATURE (°C) 100 1876 G19 SHUTDOWN PIN CURRENT (µA) SHUTDOWN LATCH THRESHOLDS (V) LATCH ARMING 3.5 LATCHOFF THRESHOLD 2.5 2.0 1.5 1.0 0.5 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 3.30 3.25 125 35 4.5 30 TA = 25°C 25 TA = 100°C 20 15 10 4.3 4.2 4.1 VIN = 3.3V 4.0 3.9 3.8 3.7 0 3.6 –50 1 2 4 5 3 SHUTDOWN PIN VOLTAGE (V) 6 VIN = 5V 50 0 TEMPERATURE (°C) Auxillary Regulator Switch Oscillator Frequency 1.35 1.6 1.4 1.30 1.2 FREQUENCY (MHz) CURRENT LI MIT (A) 1.27 100 1876 G24 1876 G23 1.28 1.24 VFB = 1.3V NOT SWITCHING 5 0 125 4.4 Current Limit for Auxillary Regulator 1.25 100 Quiescent Current for Auxillary Regulator 4.6 Feedback Pin Voltage (AUXVFB) 1.26 50 25 75 0 TEMPERATURE (°C) 1876 G21 40 1876 G22 FEEDBACK VOLTAGE (V) 3.35 Shutdown Pin Current (IAUXVFB) 4.5 3.0 3.40 1876 G20 Shutdown Latch Thresholds vs Temperature 4.0 3.45 3.20 –50 –25 125 QUIESCENT CURRENT (mA) EXTVCC SWITCH RESISTANCE (Ω) VFREQSET = 5V 1.0 0.8 0.6 1.25 1.20 1.15 0.4 1.23 1.10 0.2 1.22 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 1876 G25 0 10 20 30 40 50 60 70 DUTY CYCLE (%) 80 90 1876 G26 1.05 –50 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 1876 G28 1876fa 7 LTC1876 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Source/Capacitor Instantaneous Current (Figure 1) IIN 2A/DIV VIN 200mV/DIV VSW1 10V/DIV VSW2 10V/DIV VIN = 15V 1µs/DIV VOUT = 5V IOUT5 = IOUT3.3 = 2A Load Step (Figure 1) Load Step (Figure 1) VOUT 200mV/DIV VOUT 200mV/DIV IOUT 2A/DIV IOUT 2A/DIV 1876 G31 VIN = 15V VOUT = 5V LOAD STEP = 0A TO 3A CONTINUOUS MODE VIN = 15V 20µs/DIV VOUT = 5V LOAD STEP = 0A TO 3A Burst Mode OPERATION Constant Frequency (Burst Inhibit) Operation (Figure 1) Burst Mode Operation (Figure 1) VOUT 20mV/DIV VOUT 20mV/DIV IOUT 0.5A/DIV IOUT 0.5A/DIV VIN = 15V VOUT = 5V VFCB = OPEN IOUT = 20mA 10µs/DIV 1876 G32 1876 G30 VIN = 15V VOUT = 5V VFCB = 5V IOUT = 20mA 2µs/DIV 1876 G33 U U U PIN FUNCTIONS RUN/SS1, RUN/SS2 (Pins 1, 23): Combination of Soft-Start, Run Control Inputs and Short-Circuit Detection Timers. A capacitor to ground at each of these pins sets the ramp time to full output current. Forcing either of these pins back below 1V causes the IC to shut down the circuitry required for that particular controller. Latchoff overcurrent protection is also invoked via this pin as described in the Applications Information section. SENSE1+, SENSE2+ (Pins 2, 14): The (+) Input to each Differential Current Comparator. The ITH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. SENSE1–, SENSE2– (Pins 3, 13): The (–) Input to the Differential Current Comparators. VOSENSE1, VOSENSE2 (Pins 4, 12): Receives the remotelysensed feedback voltage for each controller from an external resistive divider across the output. FREQSET (Pin 5): Frequency Control Input to the Oscillator. This pin can be left open, tied to ground, tied to INTVCC or driven by an external voltage source. This pin can also be used with an external phase detector to build a true phase-locked loop. STBYMD (Pin 6): Control pin that determines which circuitry remains active when the controllers are shut down and/or 1876fa 8 LTC1876 U U U PIN FUNCTIONS provides a common control point to shut down both controllers. See the Operation section for details. FCB (Pin 7): Forced Continuous Control Input. This input acts on both controllers and is normally used to regulate a secondary winding. Pulling this pin below 0.8V will force continuous synchronous operation on both controllers. Do not leave this pin floating. ITH1, ITH2 (Pins 8, 11): Error Amplifier Output and Switching Regulator Compensation Point. Each associated channel’s current comparator trip point increases with this control voltage. SGND (Pin 9): Small signal ground common to both controllers, must be routed separately from high current grounds to the common (–) terminals of the COUT capacitors. 3.3VOUT (Pin 10): Output of a linear regulator capable of supplying up to 10mA DC with peak currents as high as 50mA. AUXSGND (Pin 15): Small Signal Ground of the Auxiliary Boost Regulator. AUXVFB (Pin 16): Auxiliary Boost Regulator Feedback Voltage. This pin receives the feedback voltage from an external resistive divider across the auxiliary output. AUXSW (Pins 17, 18): Switch Node Connections to Inductor for the Auxiliary Regulator. Voltage swing at these pins are from ground to (VOUT + voltage across Shottky diode). Minimize trace area at these pins to keep EMI down. TG1, TG2 (Pins 35, 24): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC – 0.5V superimposed on the switch node voltage SW. SW1, SW2 (Pins 34, 25): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST1, BOOST2 (Pins 33, 26): Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the boost and switch pins and Schottky diodes are tied between the boost and INTVCC pins. Voltage swing at the boost pins is from INTVCC to (VIN + INTVCC). BG1, BG2 (Pins 31, 27): High Current Gate Drives for Bottom (synchronous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 28): Driver Power Ground. Connects to sources of bottom (synchronous) N-channel MOSFETs, anode of the Schottky rectifier and the (–) terminal(s) of CIN. INTVCC (Pin 29): Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7µF tantalum or other, low ESR capacitor. The INTVCC regulator standby operation is determined by the STBYMD pin. AUXPGND (Pins 19, 20): The Auxiliary Power Ground Pins. Its gate drive currents are returned to these pin. EXTVCC (Pin 30): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies VCC power, bypassing the internal low dropout regulator, whenever EXTVCC is higher than 4.7V. See EXTVCC connection in Applications section. Do not exceed 7V on this pin. AUXVIN (Pin 21): Auxiliary Boost Regulator Controller Supply Pin. Must be closely decoupled to AUXPGND. VIN (Pin 32): Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. AUXSD (Pin 22): Shutdown Pin for the Auxiliary Regulator. Connect to 2.4V or more to enable the auxiliary regulator or ground to shut the auxiliary regulator off. PGOOD (Pin 36): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on either VOSENSE pin is not within 7.5% of its setpoint. 1876fa 9 LTC1876 W FUNCTIONAL DIAGRA U VIN U INTVCC DUPLICATE FOR SECOND CONTROLLER CHANNEL 1.19V BOOST 1M FREQSET DROP OUT DET CLK1 OSCILLATOR CLK2 TG TOP BOT WINDOW COMPARATOR S Q R Q INTVCC BG + – BINH + COUT PGND B + 4.5V SWITCH LOGIC VOSENSE2 0.55V CIN SW BOT VSEC 0.18µA + D1 RUN/SS1 VOSENSE1 CB FCB TOP ON PGOOD R6 DB – SHDN VOUT RSENSE FCB + FCB – I1 + – 3.3VOUT + 0.8V VREF – ++ 45k 2.4V 4.8V EXTVCC + – – EA + 5V LDO REG OV INTVCC VOSENSE VFB 0.80V 0.86V ITH INTERNAL SUPPLY SHDN RST 4(VFB) 6V STBYMD R2 R1 1.2µA SGND CSEC + – + DSEC 45k VIN 5V + 30k SENSE + – 30k SENSE SLOPE COMP VIN INTVCC I2 – 3mV 0.86V 4(VFB) – – + R5 RUN SOFT START CC CC2 RC RUN/SS CSS BOOST REGULATOR AUXVIN AUXSD L3 D5 – CC + RC AUXVFB AUXVOUT A1AUX – AUXSW R Q S Q COUTAUX Σ – R8 R7 RAMP GENERATOR + + 1.26V VREF EAAUX + 1.2MHz OSCILLATOR OSCAUX AUXPGND 1876 FD/F02 Figure 2 1876fa 10 LTC1876 U OPERATIO (Refer to Functional Diagram) Main Control Loop AUX Regulator The LTC1876 uses a constant frequency, current mode scheme to provide excellent line and load regulation for all its outputs. The step-down controllers have two of its switch drivers operating at 180 degrees out of phase from each other. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of each error amplifier EA. The VOSENSE pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VOSENSE relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The auxiliary boost regulator is completely independent from other LTC1876 circuits. It can be operated even though the LTC1876 step-down controllers are in shutdown. The operation of the boost regulator is similar to the controllers. The oscillator, OSCAUX, sets the RS latch and turns on the monolithic power switch. A voltage proportional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator, A1AUX. When this voltage exceeds the level at the negative input of A1AUX, the SR latch is reset, turning off the power switch. The level at the negative input of A1AUX is set by the error amplifier EAAUX and is simply an amplified version of the difference between the feedback voltage and the reference voltage. Hence the error amplifier sets the correct peak current level to keep the output in regulation. To protect the power switch from excessive current, a 1A minimum limit is internally set. When the switch reaches this limit, it will force the latch to reset, turning it off. Applying a voltage less than 0.5V on the shutdown pin will put the boost regulator in shutdown. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 500ns every tenth cycle to allow CB to recharge. Low Current Operation The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.2µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, the ITH pin voltage is gradually released allowing normal, full-current operation. When both RUN/SS1 and RUN/SS2 are low, all LTC1876 controller functions are shut down, and the STBYMD pin determines if the standby 5V and 3.3V regulators are kept alive. The FCB pin is a multifunction pin providing two functions: 1) to provide regulation for a secondary winding by temporarily forcing continuous PWM operation on both controllers; and 2) select between two modes of low current operation. When the FCB pin voltage is below 0.8V, the controller forces continuous PWM current operation. In this mode, the top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below VINTVCC␣ –␣ 2V but greater than 0.8V, the controller enters Burst Mode operation. Burst Mode operation sets a minimum output current level before turning off the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the ITH pin below a voltage threshold that will temporarily inhibit turn-on of both output MOSFETs until the output voltage drops slightly. There is 60mV of hysteresis in the burst comparator B tied to the ITH pin. This hysteresis produces output signals to the MOSFETs that turn them on for several 1876fa 11 LTC1876 U OPERATIO (Refer to Functional Diagram) cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. This allows the INTVCC power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in Applications Information. Constant Frequency Operation Standby Mode Pin When the FCB pin is tied to INTVCC, Burst Mode operation is disabled and the forced minimum output current requirement is removed. This provides constant frequency, discontinuous (preventing reverse inductor current) current operation over the widest possible output current range. This constant frequency operation is not as efficient as Burst Mode operation, but does provide a lower noise, constant frequency operating mode down to approximately 1% of designed maximum output current. The STBYMD pin is a three-state input that controls common circuitry within the IC as follows: When the STBYMD pin is held at ground, both controller RUN/SS pins are pulled to ground providing a single control pin to shut down both controllers. When the pin is left open, the internal RUN/SS currents are enabled to charge the RUN/SS capacitor(s), allowing the turn-on of either controller and activating necessary common internal biasing. When the STBYMD pin is taken above 2V, both internal linear regulators are turned on independent of the state of the two switching regulator controllers, providing output power to “wake-up” other circuitry. Decouple the pin with a small capacitor (0.01µF) to ground if the pin is not connected to a DC potential. Constant Current (PWM) Operation Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels— BEWARE! Frequency Setting The FREQSET pin provides frequency adjustment to the controllers’ internal oscillator from approximately 140kHz to 310kHz. This input is nominally biased through an internal resistor to the 1.19V reference, setting the oscillator frequency to approximately 220kHz. This pin can be driven from an external AC or DC signal source to control the instantaneous frequency of the oscillator. The auxillary boost regulator operates at a constant 1.2MHz frequency. INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 5V low dropout linear regulator supplies INTVCC power. If EXTVCC is taken above 4.7V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good (PGOOD) Pin The PGOOD pin is connected to an open drain of an internal MOSFET. The MOSFET turns on and pulls the pin low when both the outputs are not within ±7.5% of their nominal output levels as determined by their resistive feedback dividers. When both controller outputs meet the ±7.5% requirement, the MOSFET is turned off within 10µs and the pin is allowed to be pulled up by an external resistor to a source of up to 7V. The auxiliary regulator’s output is not monitored. Foldback Current, Short-Circuit Detection and ShortCircuit Latchoff The RUN/SS capacitors are used initially to limit the inrush current of each step-down switching regulator. After the 1876fa 12 LTC1876 U OPERATIO (Refer to Functional Diagram) controller has been started and been given adequate time to charge up the output capacitors and provide full-load current, the RUN/SS capacitor is used as a short-circuit time-out circuit. If the output voltage falls to less than 70% of its nominal output voltage, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the RUN/SS capacitor, both controllers will be shut down until the RUN/SS pin(s) voltage(s) are recycled. This builtin latchoff can be overridden by providing a >5µA pull-up at a compliance of 5V to the RUN/SS pin(s). This current shortens the soft start period but also prevents net discharge of the RUN/SS capacitor(s) during an overcurrent and/or short-circuit condition. Foldback current limiting is also activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. Even if a short is present and the shortcircuit latchoff is not enabled, a safe, low output current is provided due to internal current foldback and actual power wasted is low due to the efficient nature of the current mode switching regulator. Theory and Benefits of 2-Phase Operation The LTC1876 dual high efficiency DC/DC controller brings the considerable benefits of 2-phase operation to portable applications for the first time. Notebook computers, PDAs, handheld terminals and automotive electronics will all benefit from the lower input filtering requirement, reduced electromagnetic interference (EMI) and increased efficiency associated with 2-phase operation. Why the need for 2-phase operation? In most dual constant-frequency switching regulators, both regulators are operated in phase (i.e., single-phase operation). This means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery. These large amplitude current pulses increased the total RMS current flowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both EMI and losses in the input capacitor and battery. With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of phase. This effectively interleaves the current pulses coming from the switches, greatly reducing the overlap time where they add together. The result is a significant reduction in total RMS input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for EMI and improves real world operating efficiency. Figure 3 compares the input waveforms for a representative single-phase dual switching regulator to the LTC1876 2-phase dual switching regulator. An actual measurement of the RMS input current under these conditions shows that 2-phase operation dropped the input current from 2.53ARMS to 1.55ARMS. While this is an impressive reduction in itself, remember that the power losses are proportional to IRMS2, meaning that the actual power wasted is reduced by a factor of 2.66. The reduced input ripple voltage also means less power is lost in the input power 5V SWITCH 20V/DIV 5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV INPUT VOLTAGE 500mV/DIV IIN(MEAS) = 2.53ARMS (a) Single-Phase 1876 F03a IIN(MEAS) = 1.55ARMS 1876 F03b (b) 2-Phase Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1876 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency 1876fa 13 LTC1876 U OPERATIO (Refer to Functional Diagram) path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements in both conducted and radiated EMI also directly accrue as a result of the reduced RMS input current and voltage. the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. 3.0 SINGLE PHASE DUAL CONTROLLER 2.5 INPUT RMS CURRENT (A) Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative duty cycles which, in turn, are dependent upon the input voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how the RMS input current varies for single-phase and 2-phase operation for 3.3V and 5V regulators over a wide input voltage range. 2.0 1.5 2-PHASE DUAL CONTROLLER 1.0 0.5 It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but in fact extend over a wide region. A good rule of thumb for most applications is that 2-phase operation will reduce 0 VO1 = 5V/3A VO2 = 3.3V/3A 0 10 20 30 INPUT VOLTAGE (V) 40 1876 F04 Figure 4. RMS Input Current Comparison U W U U APPLICATIO S I FOR ATIO RSENSE Selection For Output Current RSENSE is chosen based on the required output current. The LTC1876 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1(INTVCC). The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. Allowing a margin for variations in the LTC1876 and external component values yields: RSENSE = 50mV IMAX 2.5 FREQSET PIN VOLTAGE (V) Figure 1 on the first page is a basic LTC1876 application circuit. For the step-down regulators, the external component selection is driven by the load requirement, and begins with the selection of RSENSE. Once RSENSE is known, L can be chosen. Next, the power MOSFETs and D1 are selected. Finally, CIN and COUT are selected . The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). For the step-up regulator, its component selection is much simpler. A 4.7µH or 10µH inductor that can handle at least 1A without saturating will work well with most design. A Shottky diode is recommended and a MBR0520 from ON Semiconductor is a very good choice. 2.0 1.5 1.0 0.5 0 120 170 220 270 OPERATING FREQUENCY (kHz) 320 1876 F05 Figure 5. FREQSET Pin Voltage vs Frequency 1876fa 14 LTC1876 U W U U APPLICATIO S I FOR ATIO Selection of Operating Frequency The LTC1876 uses a constant frequency architecture with the frequency determined by an internal oscillator capacitor. This internal capacitor is charged by a fixed current plus an additional current that is proportional to the voltage applied to the FREQSET pin. A graph for the voltage applied to the FREQSET pin vs frequency is given in Figure 5. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 310kHz. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN or VOUT: ∆IL = V 1 VOUT 1 – OUT (f)(L) VIN Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL=0.3(IMAX). Remember, the maximum ∆IL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ®cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for each controller with the LTC1876: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); Kool Mµ is a registered trademark of Magnetics, Inc. 1876fa 15 LTC1876 U U W U APPLICATIO S I FOR ATIO then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1876 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle = VIN – VOUT VIN The MOSFET power dissipations at maximum output current are given by: ( ) (1+ δ)RDS(ON) + 2 k(VIN ) (IMAX )(C RSS )( f) PMAIN = VOUT IMAX VIN PSYNC = VIN – VOUT IMAX VIN 2 ( ) (1+ δ)RDS(ON) 2 where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diode D1 shown in Figure 1 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the deadtime and requiring a reverse recovery period that could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN Selection The selection of CIN is simplified by the multiphase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula below to determine the maximum RMS current requirement. Increasing the output current, drawn from the other out-of-phase controller, will actually decrease the RMS ripple current from this maximum value (see Figure 4). The out-of-phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. The type of input capacitor, value and ESR rating have efficiency effects that need to be considered in the selection process. The capacitance value chosen should be sufficient to store adequate charge to keep high peak battery currents down. 20µF to 40µF is usually sufficient for a 25W output supply operating at 200kHz. The ESR of the capacitor is important for capacitor power dissipation as well as overall battery efficiency. All of the power (RMS ripple current • ESR) not only heats up the capacitor but wastes power from the battery. 1876fa 16 LTC1876 U W U U APPLICATIO S I FOR ATIO Medium voltage (20V to 35V) ceramic, tantalum, OS-CON and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramic voltage coefficients are very high and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface-mount applicability; electrolytics’ higher ESR and dryout possibility require several to be used. Multiphase systems allow the lowest amount of capacitance overall. As little as one 22µF or two to three 10µF ceramic capacitors are an ideal choice in a 20W to 35W power supply due to their extremely low ESR. Even though the capacitance at 20V is substantially below their rating at zero-bias, very low ESR loss makes ceramics an ideal candidate for highest efficiency battery operated systems. Also consider parallel ceramic and high quality electrolytic capacitors as an effective means of achieving ESR and bulk capacitance goals. In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ IMAX [V ( V OUT IN − VOUT )] 1/ 2 VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The benefit of the LTC1876 multiphase controllers can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switch on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller design. Remember that protection fuse resistance, battery resistance and PC board trace resistance losses are also reduced due to the reduced peak currents in a multiphase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The drains of the two top MOSFETS should be placed within 1cm of each other and share a common CIN(s). Separating the drains and CIN may produce undesirable voltage and current resonances at VIN. For the boost regulator, the ripple requirement for the input capacitor is less stringent. If the supply to the regulator is obtained from one of the LTC1876 step-down outputs, a 1µF to 4.7µF ceramic capacitor is sufficient. However, if the step-down output is within close proximity (< 1cm) to the boost supply input, there is no need for the capacitor. COUT Selection The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. For the step-down regulators, the output ripple (∆VOUT) is determined by: 1 ∆VOUT ≈ ∆IL ESR + 8fC OUT Where f = operating frequency, COUT = output capacitance, and ∆L= ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. With ∆IL = 0.4IOUT(MAX) the output ripple will typically be less than 50mV at max VIN assuming: COUT Recommended ESR < 2 RSENSE and COUT > 1/(8fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not significantly 1876fa 17 LTC1876 U W U U APPLICATIO S I FOR ATIO discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. For the boost regulator, the output ripple (∆VOUT) is determined by: 1.5IOUT ∆VOUT ≈ IPK ESR + fC OUT Since the boost regulator is operating at high frequency, the second term will be small even with a small value of COUT. Hence, all efforts can be concentrated on finding a low ESR capacitor. A ceramic capacitor can be used for the output capacitor. KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Pansonic SP and Sprague 595D series. For high value of ceramic capacitors, Taiyo Yuden has a series of them. Select the X5R or X7R series as these retain the capacitance over wide voltage and temperature range. Consult manufacturers for other specific recommendations. INTVCC Regulator Manufacturers such as Nichicon, United Chemicon and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR) (size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. INTVCC powers the drivers and internal circuitry within the LTC1876 stepdown controllers. The INTVCC pin regulator can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7µF tantalum, 10µF special polymer, or low ESR type electrolytic capacitor. A 1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly recommended. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between channels. In surface mount applications multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have lower storage capacity per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1876 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional external loading of the INTVCC and 3.3V linear regulators also needs to be taken into account for the power dissipation calculations. The total INTVCC current can be supplied by either the 5V internal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC current is supplied by the internal 5V linear regulator. Power dissipation for the IC in this case is highest: (VIN)(IINTVCC), and overall efficiency is lowered. The gate charge current is dependent on 1876fa 18 LTC1876 U W U U APPLICATIO S I FOR ATIO operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the Electrical Characteristics. For example, the LTC1876 VIN current is limited to less than 24mA from a 24V supply when not using the EXTVCC pin as follows: TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C Use of the EXTVCC input pin reduces the junction temperature to: TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C Dissipation should be calculated and added for current drawn from the internal 3.3V linear regulator. To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. EXTVCC Connection The LTC1876 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V, the internal regulator is turned off and the switch closes, connecting the EXTVCC pin to the INTVCC pin thereby supplying internal power. The switch remains closed as long as the voltage applied to EXTVCC remains above 4.5V. This allows the MOSFET driver and control power to be derived from the output during normal operation (4.7V < VOUT < 7V) and from the internal regulator when the output is out of regulation (start-up, short-circuit). If more current is required through the EXTVCC switch than is specified, an external Schottky diode can be added between the EXTVCC and INTVCC pins. Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC␣ <␣ VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of ((Duty Cycle)/efficiency). For 5V regulators this supply means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC. Make sure the voltage applied to the EXTVCC does not exceed 7V. 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC Connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC Connected to the output of the boost regulator. If the LTC1876 auxillary boost regulator is set up for output voltage between 4.7V and 7V, the EXTVCC can be connected to this output. 4. EXTVCC Connected to an Output-Derived Boost Network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. This can be done with either the inductive boost winding as shown in Figure 6a or the capacitive charge pump shown in Figure 6b. The charge pump has the advantage of simple magnetics. 5. EXTVCC Connected to an External supply. If an external supply is available in the 5V to 7V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. VIN OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V + CIN VSEC VIN + N-CH LTC1876 1µF TG1 RSENSE VOUT EXTVCC SW FCB BG1 T1 1:N R6 + R5 COUT N-CH SGND PGND 1876 F06a Figure 6a. Secondary Output Loop and EXTVCC Connection 1876fa 19 LTC1876 U U W U APPLICATIO S I FOR ATIO + VIN 1µF + CIN BAT85 VIN 0.22µF BAT85 N-CH LTC1876 RSENSE VOUT EXTVCC L1 SW R2 VOUT = 0.8V 1 + R1 BAT85 VN2222LL TG1 the internal precision 0.8V voltage reference by the error amplifier. The output voltage is given by the equation: + COUT BG1 N-CH PGND 1876 F06b Figure 6b. Capacitive Charge Pump for EXTVCC Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the functional diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency. Output Voltage The LTC1876 output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor as shown in Figure 2. For the step-down controller, the resultant feedback signal is compared with For the auxillary boost regulator, the resultant feedback signal is compared with the internal precision 1.26V voltage reference by the error amplifier. The output voltage is given by the equation: R8 VOUTAUX = 1.26V 1 + R7 SENSE+/SENSE– Pins The common mode input range of the current comparator SENSE pins is from 0V to (1.1)INTVCC. Continuous linear operation is guaranteed throughout this range allowing output voltage setting from 0.8V to 7.7V, depending upon the voltage applied to EXTVCC. A differential NPN input stage is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This requires that current either be sourced or sunk from the SENSE pins depending on the output voltage. If the output voltage is below 2.4V current will flow out of both SENSE pins to the main output. The output can be easily preloaded by the VOUT resistive divider to compensate for the current comparator’s negative input bias current. The maximum current flowing out of each pair of SENSE pins is: ISENSE+ + ISENSE– = (2.4V – VOUT)/24k Since VOSENSE is servoed to the 0.8V reference voltage, we can choose R1 in Figure 2 to have a maximum value to absorb this current. 0.8V R1(MAX) = 24k 2.4V – VOUT for VOUT < 2.4V Regulating an output voltage of 1.8V, the minimum value of R1 should be 32k. Note that for an output voltage above 2.4V, R1 has no maximum value since the SENSE pins load the output. 1876fa 20 LTC1876 U U W U APPLICATIO S I FOR ATIO Soft-Start/Run Function Fault Conditions: Overcurrent Latchoff The RUN/SS1 and RUN/SS2 pins are multipurpose pins that provide a soft-start function and a means to shut down the LTC1876 step-down controllers. Soft-start reduces the input power source’s surge currents by gradually increasing the controller’s current limit (proportional to VITH). This pin can also be used for power supply sequencing. The RUN/SS pins also provide the ability to latch off the controller(s) when an overcurrent condition is detected. The RUN/SS capacitor, CSS, is used initially to turn on and limit the inrush current of the controller. After the controller has been started and been given adequate time to charge up the output capacitor and provide full load current, the RUN/SS capacitor is used for a short-circuit timer. If the regulator’s output voltage falls to less than 70% of its nominal value after CSS reaches 4.1V, CSS begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period as determined by the size of the CSS and the specified discharge current, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by: An internal 1.2µA current source charges up the CSS capacitor. When the voltage on RUN/SS1 (RUN/SS2) reaches 1.5V, the particular controller is permitted to start operating. As the voltage on RUN/SS increases from 1.3V to 3.0V, the internal current limit is increased from 25mV/ RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.2s/µF to reach full current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: t DELAY = ( ) ( TLO2 ≅ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS) ) 3V − 1.5V C SS = 1.25s / µF C SS 1.2µA By pulling both RUN/SS pins below 1.0V and/or pulling the STBYMD pin below 0.2V, the controllers are put into low current shutdown (IQ = 20µA). The RUN/SS pins can be driven directly from logic as shown in Figure 7. Diode D1 in Figure 7 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. Each RUN/SS pin has an internal 6V Zener clamp (See Functional Diagram). VIN 3.3V OR 5V INTVCC RUN/SS RSS* D1 RSS* RUN/SS CSS CSS *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF (a) Figure 7. RUN/SS Pin Interfacing = 2.7 • 106 (CSS) If the overload occurs after start-up the voltage on CSS will begin discharging from the zener clamp voltage: 1.5V C SS = 1.25s / µF C SS 1.2µA tIRAMP = TLO1 ≅ [CSS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA) (b) 1876 F07 If an overload occurs on one channel, it will also latch off the other channel. This built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the RUN/SS pin as shown in Figure 7. This resistance shortens the softstart period and prevents the discharge of the RUN/SS capacitor during an over current condition. Tying this pullup resistor to VIN as in Figure 7a, defeats overcurrent latchoff. Diode-connecting this pull-up resistor to INTVCC, as in Figure 7b, eliminates any extra supply current during controller shutdown while eliminating the INTVCC loading from preventing controller start-up. Why should you defeat overcurrent latchoff? During the prototype stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. Defeating this feature will easily allow troubleshooting of the circuit and PC layout. The internal shortcircuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. After the design is complete, a decision can be made whether to enable the latchoff feature. 1876fa 21 LTC1876 U W U U APPLICATIO S I FOR ATIO The value of the soft-start capacitor CSS may need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT) (10 –4) (RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. Fault Conditions: Current Limit and Current Foldback The LTC1876 step-down controllers current comparator has a maximum sense voltage of 75mV resulting in a maximum MOSFET current of 75mV/RSENSE. The maximum value of current limit generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the highest power dissipation in the top MOSFET. The controllers include current foldback to help further limit load current when the output is shorted to ground. The foldback circuit is active even when the overload shutdown latch described above is overridden. If the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 75mV to 25mV. Under short-circuit conditions with very low duty cycles, the step-down regulators will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The shortcircuit ripple current is determined by the minimum ontime tON(MIN) (less than 200ns), the input voltage and inductor value: ∆IL(SC) = tON(MIN) (VIN/L) The resulting short-circuit current is: ISC = 25mV 1 + ∆IL(SC) RSENSE 2 to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The output of this comparator is only latched by the overvoltage condition itself and will therefore allow a switching regulator system having a poor PC layout to function while the design is being debugged. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. The Standby Mode (STBYMD) Pin Function The Standby Mode (STBYMD) pin provides several choices for start-up and standby operational modes. If the pin is pulled to ground, the RUN/SS pins for both controllers are internally pulled to ground, preventing start-up and thereby providing a single control pin for turning off both controllers at once. If the pin is left open or decoupled with a capacitor to ground, the RUN/SS pins are each internally provided with a starting current enabling external control for turning on each controller independently. If the pin is provided with a current of >3µA at a voltage greater than 2V, both internal linear regulators (INTVCC and 3.3V) will be on even when both controllers are shut down. In this mode, the onboard 3.3V and 5V linear regulators can provide power to keep-alive functions such as a keyboard controller. This pin can also be used as a latching “on” and/ or latching “off” power switch if so designed. Fault Conditions: Overvoltage Protection (Crowbar) Frequency of Operation The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the step-down regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse The LTC1876 stepdown controllers have an internal voltage controlled oscillator. The frequency of this oscillator can be varied over a 2 to 1 range. The pin is internally selfbiased at 1.19V, resulting in a free-running frequency of 1876fa 22 LTC1876 U W U U APPLICATIO S I FOR ATIO approximately 220kHz. The FREQSET pin can be grounded to lower this frequency to approximately 140kHz or tied to the INTVCC pin to yield approximately 310kHz. The FREQSET pin may be driven with a voltage from 0 to INTVCC to fix or modulate the oscillator frequency as shown in Figure 5. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the step down controller is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum ontime limit and care should be taken to ensure that. tON(MIN) < VOUT VIN (f) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for each controller is generally less than 200ns. However, as the peak sense voltage decreases the minimum on-time gradually increases up to about 300ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. FCB Pin Operation The FCB pin can be used to regulate a secondary winding or as a logic level input. Continuous operation is forced when the FCB pin drops below 0.8V. During continuous mode, current flows continuously in the transformer primary. The secondary winding(s) draw current only when the bottom, synchronous switch is on. When primary load currents are low and/or the VIN/VOUT ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous operation will support secondary windings providing there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. The secondary output voltage VSEC is normally set as shown in Figure 6a by the turns ratio N of the transformer: VSEC ≅ (N + 1) VOUT However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VSEC will droop. An external resistive divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN): R6 VSEC(MIN) ≈ 0.8V 1 + R5 If VSEC drops below this level, the FCB voltage forces temporary continuous switching operation until VSEC is again above its minimum. In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.18µA internal current source pulling the pin high. Include this current when choosing resistor values R5 and R6. The following table summarizes the possible states available on the FCB pin: Table 1 FCB Pin Condition 0V to 0.75V Forced Continuous (Current Reversal Allowed—Burst Inhibited) 0.85V < VFB < 4.3V Minimum Peak Current Induces Burst Mode Operation No Current Reversal Allowed Feedback Resistors Regulating a Secondary Winding >4.8V Burst Mode Operation Disabled Constant Frequency Mode Enabled No Current Reversal Allowed No Minimum Peak Current Remember that both controllers are temporarily forced into continuous mode when the FCB pin falls below 0.8V. 1876fa 23 LTC1876 U W U U APPLICATIO S I FOR ATIO Voltage Positioning Voltage positioning can be used to minimize peak-to-peak output voltage excursions under worst-case transient loading conditions. The open loop DC gain of the control loop is reduced depending upon the maximum load step specifications. Voltage positioning can be easily added to the LTC1876 by loading the ITH pin with a resistive divider having a Thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2V (see Figure 8). The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The maximum output voltage deviation can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. A complete explanation is included in Design Solutions 10. (See: www.linear-tech.com) INTVCC RT2 ITH RT1 RC LTC1876 CC 1876 F08 Figure 8. Active Voltage Positioning Applied to the LTC1876 Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1876 circuits: 1) LTC1876 VIN current (including loading on the 3.3V internal regulator), 2) INTVCC regulator current, 3) I2R losses, 4) topside MOSFET transition losses. 1. The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the 3.3V linear regulator output. VIN current typically results in a small (<0.1%) loss. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG =f(QT+QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode the average output current flows through L and RSENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and RESR = 40mΩ (sum of both input and output capacitance losses), then the total resistance is 130mΩ. This results in losses ranging from 3% to 13% as the output current increases from 1A to 5A for a 5V output, or a 4% to 20% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but 1876fa 24 LTC1876 U W U U APPLICATIO S I FOR ATIO quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the topside MOSFET(s), and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20µF to 40µF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. The LTC1876 step-down controllers 2-phase architecture typically halves this input capacitance requirement over competing solutions. Other losses including Schottky conduction losses during deadtime and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTILOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full-load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. 1876fa 25 LTC1876 U U W U APPLICATIO S I FOR ATIO Low VIN Applications TO SENSE1+ AND SENSE1– INPUT SUPPLY In applications where the input supply is low (<5V), the LTC1876 auxiliary regulator can be used to step-up the input to provide the gate drive to the external MOSFETs as shown in Figure 9. Shown in the Typical Application section of the data sheet is a circuit (3.3VIN Dual-Phase High Efficiency Power Supply) with input supply of 3.3V. The boost section of the LTC1876 is set up to generate 5V and is used to provide the gate drive to the external MOSFETs. The circuit provides dual outputs, a 2.5V/15A and 1.8V/15A. Both drawing power directly from VIN. INPUT SUPPLY L1 VIN RC L1 RS1 L2 RS2 ITH1 ITH2 CC EXTERNAL MOSFETs LTC1876 VOSENSE1 VOSENSE2 R1 VOUT + SGND TO SENSE2+ AND SENSE2– R2 1876 F10 Figure 10. Single Output Configuration Auxiliary Regulator’s Inductor Value Calculation Since the current limit for the auxiliary regulator is internally set at 1A, it makes the selection of components easier. For the boost regulator, the duty cycle is given by: AUXVIN AUXSW LTC1876 BOOST SECTION VIN D1 + EXTERNAL MOSFETs Duty Cycle = 1– COUT AUXVFB SGND LTC1876 STEP-DOWN SECTION R8 R7 1876 F09 Figure 9. Generating the Gate Drive for Low Input Supply Applications Single Output/High Current Applications In applications that demand current much higher than a single stage can supply (>20A), the LTC1876 can be configured as a single output converter. Figure 10 shows the block diagram of the configuration. Note that the compensation pins (ITH1 and ITH2) of the two channels are connected together, saving a set of passive components. In addition, the output voltage sense pins (VOSENSE1 and VOSENSE2) are shorted together, using only one resistor divider to set the output voltage. Although the output current requirement is high, the input capacitors ripple current requirement is not much different compared to the dual outputs circuit. This is attributed to the fact that the current is shared between two channels and an out-of-phase architecture is implemented for the controllers (See Theory and Benefits of 2-Phase Operation). VIN VOUT Since energy is only transferred to the output capacitor(s) during the off-time, the maximum output current that can be supplied by the regulator without losing regulation is: IOUT = 0.5(2 • IPK – ∆IL)(1 – Duty Cycle) where IPK = peak inductor current and is internally set at 1A. ∆IL = inductor’s ripple current With the required ripple current determined, the value of the inductor is: L= (VIN • Duty Cycle ) (f • ∆IL ) where f = operating frequency (1.2MHz) In most cases, a larger value of inductance is used. This is done to account for component variation. It also lowers the inductor ripple current and results in lower core losses. In addition, lower ripple also translates into lower ESR losses in the output capacitors and smaller output voltage ripple. 1876fa 26 LTC1876 U W U U APPLICATIO S I FOR ATIO Once the value of L is known, select an inductor that can handle at least 1A without saturating. In addition, ensure that the inductor has a low DCR (copper wire resistance) to minimize I2R power losses. Auxiliary Regulator’s Capacitor Selection Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have extremely low ESR and are available in very small packages. X5R dielectrics are preferred, followed by X7R, as these materials retain the capacitance over wide voltage and temperature ranges. A 4.7µF to 10µF output capacitor is sufficient for most applications, but systems with very low output current may need only a 1µF or 2.2µF output capacitor. Solid tantalum or OS-CON capacitors can be used, but they will occupy more board area than a ceramic and will have a higher ESR. Always use a capacitor with a sufficient voltage rating. Ceramic capacitors also make a good choice for the input decoupling capacitor, and should be placed as close as possible to the AUXVIN pin. A 1µF to 4.7µF input capacitor is sufficient for most applications. Table 2 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts. Table 2. Ceramic Capacitor Manufacturers Taiyo Yuden (408) 573-4150 www.t-yuden.com AVX (803) 448-9411 www.avxcorp.com Murata (714) 852-2001 www.murata.com between VOUT3 and AUXVFB as shown in Figure 11. The frequency of the zero is determined by the following equation. fZ = 1 2π • R8 • C 3 By choosing the appropriate values for the resistor and capacitor, the zero frequency can be designed to slightly improve the phase margin of the overall converter. The typical target value for the zero frequency is between 50kHz to 150kHz. VOUT3 LTC1876 R8 C3 AUXVFB R7 1876 F11 Figure 11. Adding a Phase Lead Zero Auxiliary Regulator’s Diode Selection A Schottky diode is recommended for use with the auxiliary regulator. The ON Semiconductor MBR0520 is a very good choice. Where the input to output voltage differential exceeds 20V, use the MBR0530 (a 30V diode). These diodes are rated to handle an average forward current of 0.5A. In applications where the average forward current of the diode exceeds 0.5A, a Microsemi UPS5817 rated at 1A is recommended. Driving AUXSD Above 10V The decision to use either low ESR (ceramic) capacitors or higher ESR (tantalum or OS-CON) capacitors can affect the stability of the overall system. The ESR of any capacitor, along with the capacitance itself, contributes a zero to the system. For the tantalum and OS-CON capacitors, this zero is located at a lower frequency due to the higher value of the ESR, while the zero of a ceramic capacitor is a much higher frequency and can generally be ignored. A phase lead zero can be intentionally introduced by placing a capacitor (C3) in parallel with the resistor (R8) The maximum voltage allowed on the AUXSD pin is 10V. In some applications if the applied voltage on this pin is going to exceed 10V, then a series resistor can be connected to this pin. The value for this resistor is given by: RSERIES = (VAUXSD – 10) (60 • 10–6 ) By placing this series resistor, it ensures that the voltage seen by the pin will not exceed 10V. 1876fa 27 LTC1876 U U W U APPLICATIO S I FOR ATIO Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery, and double-battery. Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 12 is the most straight forward approach to protect a DC/DC converter from the ravages of an automotive battery line. The series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC1876 step-down controllers have a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V Design Example As a design example for one channel, assume VIN = 12V (nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A, and f = 300kHz, RSENSE can immediately be calculated: RSENSE = 50mV/5A = 0.01Ω Tie the FREQSET pin to the INTVCC pin for 300kHz operation. Assume a 4.7µH inductor and check the actual value of the ripple current. The following equation is used: ∆IL = VOUT VOUT 1– (f)(L) VIN The highest value of the ripple current occurs at the maximum input voltage: ∆IL = 1.8V 1.8V 1– = 1.17A 300kHz(4.7µH) 22V The ripple current is 23% of maximum output current, which is below the 30% guideline. This means that a 3.3µH inductor can be used. Increasing the ripple current will also help ensure that the minimum on-time of 200ns is not violated. The minimum on-time occurs at maximum VIN: tON(MIN) = VOUT VIN(MAX)f = 1.8V = 273ns 22V(300kHz) Since the output voltage is below 2.4V the output resistive divider will need to be sized to not only set the output voltage but also to absorb the SENSE pins current. VIN LTC1876 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 1876 F09 Figure 12. Automotive Application Protection 0.8V R1(MAX) = 24k 2.4V – VOUT 0.8V = 24k = 32k 2.4V – 1.8V 1876fa 28 LTC1876 U W U U APPLICATIO S I FOR ATIO Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. Since the required output current is 300mA, the ripple current of the inductor is calculated to be 0.57A. The power dissipation on the top side MOSFET can be easily estimated. Choosing a Siliconix Si4412DY results in; RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input voltage with T(estimated) = 50°C: Hence the required inductor is: ()[ ] 2 (0.042Ω) + 1.7(22V) (5A)(100pF )(300kHz) PMAIN = 1.8V 2 5 1 + (0.005)(50°C – 25°C ) 22V = 220mW A short-circuit to ground will result in a folded back current of: ISC 25mV 1 200ns(22V) = + = 3.2A 0.01Ω 2 3.3µH with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is: ( ) (1.1)(0.042Ω) 22V – 1.8V 3.2A 22V = 434mW PSYNC = 2 L= (VIN • Duty Cycle ) (f • ∆IL ) With the boost regulator operating at 1.2MHz, L = 4.24µH A 10µH inductor is selected for the circuit for lower ripple inductor current. Since the output current is only 300mA, a 0.5A MBR0520 Schottky is selected. The completed circuit along with its efficiency curve is shown in Figure 13 and Figure 14 respectively. L3 10µH VIN3 5V CIN3 2.2µF AUXVIN AUXSW COUT3 4.7µF 1876 F13 90 VIN = 5V 85 VIN = 3.3V 80 75 70 65 Assume the requirements are VIN = 5V, VOUT = 12V and IOUTMAX = 300mA. The duty cycle is given by: 55 VOUT + Figure 13. Design Example Schematic 60 Duty Cycle = 1 – R7 13.3k C1: TAIYO YUDEN X5R LMK212BJ225MG C2: TAIYO YUDEN X5R EMK316BJ475ML D1: ON SEMICONDUCTOR MBR0520 L1: SUMIDA CR43-100 *OPTIONAL Design Example for Auxiliary Regulator VIN C3* 10pF AUXSD AUXVFB SGND EFFICIENCY (%) VORIPPLE = RESR(∆IL) = 0.02Ω(1.67A) = 33mVP–P R8 113k VOUT3 12V 300mA LTC1876 SHDN which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: D1 50 0 100 200 300 LOAD CURRENT (mA) 400 1876 F14 = 0.58 Figure 14. Efficiency Curve for Design Example 1876fa 29 LTC1876 U U W U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1876. These items are also illustrated graphically in the layout diagram of Figure 15. The Figure 16 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in your layout: R2 3 R1 4 5 7 INTVCC 8 3.3V 10 11 12 R3 R4 13 14 15 R7 16 17 R8 18 VOUT3 TG1 SENSE1 – SW1 VOSENSE1 BOOST1 FREQSET VIN STBYMD BG1 EXTVCC FCB LTC1876 INTVCC ITH1 SGND PGND 3.3VOUT BG2 ITH2 BOOST2 VOSENSE2 SW2 SENSE2 – TG2 SENSE2 + RUN/SS2 AUXSGND AUXSD AUXVFB AUXVIN AUXSW AUXPGND AUXSW AUXPGND VPULL-UP (<7V) L1 35 3 4 RSENSE 1 VOUT1 2 34 CB1 33 M1 D1 M2 32 COUT1 31 RIN 30 CIN CVIN 29 CINTVCC 28 VIN + 9 SENSE1 + 36 + 6 PGOOD + 2 RUN/SS1 2. Is the ground of the step-down controller kept separate from the ground of the step-up regulator? The regulator ground should join the controller ground at the combined COUT (–) plates. Within the controller circuitry, are the signal and power grounds kept separate? The controller + 1 1. Are the top N-channel MOSFETs M1 and M3 located within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. COUT2 27 26 M3 M4 25 1 24 L2 23 22 D2 CB2 3 RSENSE 2 VOUT2 4 SHUTDOWN 21 20 CAUXIN 19 D3 L3 COUT3 1876 F15 Figure 15. LTC1876 Recommended Printed Circuit Layout Diagram 1876fa 30 LTC1876 U W U U APPLICATIO S I FOR ATIO signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) plates. Within the regulator circuitry, are the signal and power grounds kept separate? The regulator signal ground pin must return to the CAUXIN (–) plates. the (–) plates of the COUT3 (–) plates by placing the capacitors next to each other and away from the D3 loop described above. 3. Does the path formed by the top N-Channel MOSFET Schottky diode (D1, D2) and the CIN capacitor have short leads and PC trace lengths? The output capacitor (–) plates should be connected as close as possible to the (–) plates of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. Also, the path formed by the AUXSW pins, Schottky diode (D3) and the COUT3 capacitor should have short leads and PC trace lengths. The CAUXIN capacitor (–) plates should be connected as close as possible to 5. Do the LTC1876 VOSENSE and AUXVFB pins resistive dividers connect to the (+) plates of its respective COUT? The resistive divider must be connected between the (+) plate of COUT and signal ground and a small VOSENSE decoupling capacitor should be as close as possible to the LTC1876 SGND pin. A feedforward capacitor across R8 can be connected to enhance the transient response of the boost regulator. The R2, R4 and R8 connections should not be along the high current input feeds from the input capacitor(s). SW1 4. If the input supply to the boost regulator is obtain from one of the other outputs, is this connection short (< 1cm)? L1 D1 RSENSE1 COUT1 VOUT1 + RL1 VIN RIN CIN + SW2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH. D2 L2 RSENSE2 COUT2 VOUT2 + RL2 1876 F16 Figure 16. Branch Current Waveforms 1876fa 31 LTC1876 U W U U APPLICATIO S I FOR ATIO 6. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE– should be as close as possible to the IC. 7. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 8. Keep the switching nodes (SW1, SW2, AUXSW), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposites channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC1876 and occupy minimum PC trace area. 9. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. PC Board Layout Debugging Start with one regulator on at a time. It is best to first start with one of the step-down regulator and it is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold—typically 10% to 20% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for their individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. Short-circuit testing can be performed to verify proper overcurrent latchoff, or 5µA can be provided to the RUN/SS pin(s) by resistors from VIN or INTVCC (depending upon the STBYMD pin programming), to prevent the short-circuit latchoff from occurring. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN and monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. 1876fa 32 LTC1876 U W U U APPLICATIO S I FOR ATIO An embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor—don’t worry, the regulator will still maintain control of the output voltage. U TYPICAL APPLICATIO S Low Voltage 3.3V to 1.8V, 2.5V and 5V Power Supply 0.1µF 2 42.5k 1% 1000pF 20k 1% 3 4 0.01µF 5 0.01µF 6 220pF 7 8 6.8k 470pF 9 220pF 3.3VOUT 10 470pF 11 6.8k 12 20k 1% 25k 1% 13 1000pF 14 16 17 31.6k VOUT3 5V 400mA PGOOD SENSE1 + TG1 SENSE1 – SW1 VOSENSE1 BOOST1 FREQSET VIN STBYMD BG1 FCB EXTVCC LTC1876 ITH1 INTVCC SGND PGND 3.3VOUT BG2 BOOST2 ITH2 VOSENSE2 SW2 SENSE2 – TG2 100k 36 35 L1 2µH PGOOD SENSE2 + RUN/SS2 AUXSD AUXSGND AUXVFB AUXVIN AUXSW AUXPGND AUXSW AUXPGND 3 4 34 0.1µF 33 M1 M2 10Ω 31 + 33µF 6.3V, SP 30 D3 29 1µF D4 4.7µF 0.1µF + + 47µF 6.3V SP 27 26 M3 M4 1 24 L2 2µH 23 3 VOUT2 1.8V 5A 2 RSENSE 0.008Ω 4 SHUTDOWN 21 20 D2 0.1µF 25 22 D1 47µF 6.3V SP 32 28 VOUT1 2.5V 4A 1 RSENSE 2 0.008Ω 0.1µF 15 10k RUN/SS1 + 1 VIN 3.3V 1µF D5 18 10µF 16V ×5R + 10µF 19 M1, M2, M3, M4: FDS6912A L1, L2: SUMIDA CEP123-2RO L3: SUMIDA CDRH5D18 D1, D2: MBRM140T3 D3, D4: BAT54A D5: MBR0520 L3, 5.4µH 20V 1876 TA02 1876fa 33 LTC1876 U TYPICAL APPLICATIO S 3.3VIN Dual-Phase High Efficiency Power Supply 100pF 1 PGOOD RUN/SS1 36 VPULL-UP (<7V) 100k 17.4k 1% 1000pF 8.25k 1% 2 SENSE1 + 3 SENSE1 – 4 0.01µF 5 0.01µF 6 100pF 7 8 47k 6800pF 9 100pF 3.3V 10 11 47k 6800pF 12 13 8.06k 1% 10k 1% 1000pF 14 15 16 10.2k 1% 30.9k 1% 17 18 1µF 6.3V + TG1 SW1 VOSENSE1 BOOST1 FREQSET VIN BG1 STBYMD EXTVCC FCB LTC1876 INTVCC ITH1 SGND PGND 3.3VOUT ITH2 BG2 BOOST2 VOSENSE2 SW2 SENSE2 – TG2 L1 0.9µH 35 3 VOUT1 2.5V 15A 1 RSENSE 2 0.003Ω 34 33 4 M2 ×2 M1 ×2 0.47µF C4 1µF 6.3V D1 32 VIN 3.3V 31 + 1µF 6.3V COUT1 220µF, 4V, ×3 30 28 10Ω D4 29 2.2µF 6.3V + 1µF 6.3V + CIN 330µF 6V, ×3 10µF 6.3V + COUT2 330µF, 2.5V, ×3 27 M3 ×2 26 M4 ×2 D2 0.47µF 25 C26 1µF 6.3V 24 0.1µF SENSE2 + RUN/SS2 AUXSGND AUXSD AUXVFB AUXVIN AUXSW AUXPGND AUXSW AUXPGND 1 23 22 SHUTDOWN L2 3 0.9µH VOUT2 1.8V 15A 2 RSENSE 0.003Ω 4 21 20 1µF 6.3V 19 D3 L3, 47µH 10µF 10V 1876 TA04 D1, D2: MBRS340T3 D3: CMDSH-3 D4: BAT54A L1, L2: SUMIDA CEP134-OR9 L3: TOKO FSLB2520-470K M1, M2, M3, M4: FDS7764A 1876fa 34 LTC1876 U PACKAGE DESCRIPTIO G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 7.8 – 8.2 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.42 ±0.03 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RECOMMENDED SOLDER PAD LAYOUT 5.00 – 5.60** (.197 – .221) 2.0 (.079) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.55 – 0.95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) 0.05 (.002) G36 SSOP 0802 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 1876fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC1876 U TYPICAL APPLICATION High Efficiency Triple 5V/ 3.3V/12V Power Supply 0.1µF 2 63.4k 1% 1000pF 3 20k 1% 4 0.01µF 5 0.01µF 220pF INTVCC 7 8 470pF 9 220pF 3.3V 470pF 10 11 6.8k 12 20k 1% 105k 1% 13 1000pF 14 16 86.6k VOUT3 12V 200mA 17 D5 18 10µF 20V SENSE1 – SW1 VOSENSE1 BOOST1 FREQSET VIN STBYMD BG1 L1 4.6µH 35 34 33 M1 0.1µF EXTVCC LTC1876 INTVCC ITH1 SGND PGND BG2 3.3VOUT ITH2 BOOST2 VOSENSE2 SW2 SENSE2 – TG2 SENSE2 + RUN/SS2 AUXSGND AUXSD 47µF 6.3V SP VIN 5.2V TO 28V 31 30 4.7µF 10V D3 29 10µF 35V 1µF D4 0.1µF + 33µF 35V 56µF 4V SP 27 26 D2 0.1µF 25 M3 AUXVFB AUXVIN AUXSW AUXPGND AUXSW AUXPGND + M4 RSENSE 1 0.008Ω 2 24 23 22 VOUT1 3.3V 5A D1 32 28 4 M2 10Ω FCB 3 1 RSENSE 2 0.008Ω 0.1µF 15 10.2k TG1 VPULL-UP (<7V) + 6.8k SENSE1 + 100k 36 + 6 PGOOD RUN/SS1 + 1 L2 3 4.6µH VOUT2 5V 5A 4 SHUTDOWN 21 20 19 M1, M2, M3, M4: FDS6912A L1, L2: SUMIDA CEP123-4R6 L3: TOKO A920CY-100M D1, D2: MBRM140T3 D3, D4: BAT54A D5: CMDSH-3 L3, 10µH 1876 TA03 RELATED PARTS PART NUMBER LTC1625/LTC1775 DESCRIPTION COMMENTS TM No RSENSE Current Mode Synchronous Step-Down Controllers Burst Mode Operation, GN-16 LTC1628/LTC1628-PG High Efficiency, Dual, 2 Phase Synchronous Step-Down Controllers Constant Frequency, Standby, 5V and 3.3V LDO LTC1708-PG Dual, 2 Phase Synchronous Controller with Mobile VID Control 36V Input; VOUT1 for CPU Core Voltage; VOUT2 for Memory, Chipset I/O LTC1709 2 Phase, 5-Bit Adustable, High Efficiency, Synchronous Step-Down Controller Constant Frequency, VID, up to 42A LTC1735 High Efficiency Synchronous Step-Down Switching Regulator Output Fault Protection, GN-16 LTC1736 High Efficiency Synchronous Controller with Mobile VID Control Output Fault Protection, G-24 LTC1772 SOT-23 Step-Down Controller 2.5V ≤ VIN ≤ 9.8V; IOUT Up to 4.5A; 550kHz Operation for Smallest PCB Area LTC1778 No RSENSE Wide Input Range Synchronous Step-Down Controller Up to 97% Efficiency; 4V␣ ≤ VIN ≤ 36V 0.8V ≤ VOUT ≤ (0.9)(VIN); Input up to 20A LTC3713 Low Input Voltage Synchronous Step-Down Controller 1.5V ≤ VIN, No RSENSE, Standard 5V-Logic Level MOSFETs LTC3714 No RSENSE DC/DC Controller for Mobile Pentium Processors Supports up to 25A; Sense Resistor Optional LTC3716 2-Phase DC/DC Controller for Mobile Pentium Processors Small, Low Profile Design; Supports up to 30A LTC3728 Dual, 2-Phase 550kHz Synchronous Step-Down Controller Phase-Lockable from 250kHz to 550kHz, 5mm × 5mm QFN and SSOP-28, 3.5V ≤ VIN ≤ 36V Adaptive Power and No RSENSE are trademarks of Linear Technology Corporation. 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com 1876fa LT/TP 1002 1K REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2000