Final Electrical Specifications LTC3719 2-Phase, 5-Bit VID, Current Mode, High Efficiency, Synchronous Step-Down Switching Regulator ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Output Stages Operate Antiphase Reducing Input and Output Capacitance Requirements and Power Supply Induced Noise Dual Input Supply Capability for Load Sharing 5-Bit AMD (Hammer) CPU VID Code: VOUT = 0.8V to 1.55V ±1% Output Voltage Accuracy True Remote Sensing Differential Amplifier Power Good Output Voltage Monitor Supports Active Voltage Positioning Current Mode Control Ensures Current Sharing OPTI-LOOP® Compensation Minimizes COUT Three Operational Modes: PWM, Burst and Cycle Skip Programmable Fixed Frequency: 150kHz to 300kHz Wide VIN Range: 4V to 36V Operation Adjustable Soft-Start Current Ramping Internal Current Foldback and Short-Circuit Shutdown Overvoltage Soft Latch Eliminates Nuisance Trips Available in 36-Lead Narrow (0.209) SSOP Package U APPLICATIO S ■ December 2001 U FEATURES AMD (Sledgehammer and Clawhammer) CPU Supply , LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation. The LTC®3719 is a 2-phase, VID programmable, synchronous step-down switching regulator controller that drives two N-channel external power MOSFET stages in a fixed frequency architecture. The 2-phase controller drives its two output stages out of phase at frequencies up to 300kHz to minimize the RMS ripple currents in both input and output capacitors. The 2-phase technique effectively multiplies the fundamental frequency by two, improving transient response while operating each channel at an optimum frequency for efficiency. Thermal design is also simplified. An operating mode select pin (FCB) can be used to regulate a secondary winding or select among three modes including Burst Mode® operation for highest efficiency. An internal differential amplifier provides true remote sensing of the regulated supply’s positive and negative output terminals as required in high current applications. The RUN/SS pin provides soft-start and optional timed, short-circuit shutdown. Current foldback limits MOSFET dissipation during short-circuit conditions when the overcurrent latchoff is disabled. OPTI-LOOP compensation allows the transient response to be optimized for a wide range of output capacitors and ESR values. U TYPICAL APPLICATIO VIN FCB RUN/SS 220pF 3.3k ITH LTC3719 SGND PGOOD 5 VID BITS TG1 VID0–VID4 EAIN ATTENOUT S BOOST1 0.47µF VIN 5V TO 28V 0.002Ω 1µH SW1 S D1 BG1 PGND SENSE1 + SENSE1 – TG2 BOOST2 ATTENIN BG2 VDIFFOUT INTVCC VOS – SENSE2 + VOS + SENSE2 – VDD_CORE 0.8V TO 1.55V 45A 0.002Ω 0.47µF 1µH SW2 D2 + 0.1µF 10µF 35V ×6 10µF + COUT 270µF 2V ×4 3716 F01 Figure 1. High Current Dual Phase Step-Down Converter 3719i Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LTC3719 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN).........................36V to – 0.3V Topside Driver Voltages (BOOST1,2) .........42V to – 0.3V Switch Voltage (SW1, 2) .............................36V to – 5 V SENSE1+, SENSE2 +, SENSE1–, SENSE2 – Voltages ................... (1.1)INTVCC to – 0.3V EAIN, VOS+, VOS–, EXTVCC, INTVCC, RUN/SS, VBIAS, ATTENIN, ATTENOUT, PGOOD, NO_CPU, VID0–VID4, Voltages ...............................7V to – 0.3V Boosted Driver Voltage (BOOST-SW) ..........7V to – 0.3V PLLFLTR, PLLIN, VDIFFOUT, FCB Voltages ................................... INTVCC to – 0.3V ITH Voltage ................................................2.7V to – 0.3V Peak Output Current <1µs(TG1, 2, BG1, 2) ................ 3A INTVCC RMS Output Current ................................ 50mA Operating Ambient Temperature Range (Note 2) .............................................. – 40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RUN/SS 1 36 PGOOD SENSE1 + 2 35 TG1 SENSE1 – 3 34 SW1 LTC3719EG EAIN 4 33 BOOST1 PLLFLTR 5 32 VIN PLLIN 6 31 BG1 FCB 7 30 EXTVCC ITH 8 29 INTVCC SGND 9 28 PGND VDIFFOUT 10 27 BG2 VOS – 11 26 BOOST2 VOS + 12 25 SW2 SENSE2 – 13 24 TG2 SENSE2 + 14 23 ATTENIN ATTENOUT 15 22 VBIAS NO_CPU 16 21 VID4 VID0 17 20 VID3 VID1 18 19 VID2 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 85°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VBIAS = 5V, VRUN/SS = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ● 0.594 0.600 0.606 ● 62 75 88 mV –5 – 50 nA 0.1 – 0.1 0.5 – 0.5 % % 0.002 0.02 %/V Main Control Loop VEAIN Regulated Feedback Voltage VSENSEMAX Maximum Current Sense Threshold ITH Voltage = 1.2V; Measured at VEAIN (Note 4) IINEAIN Feedback Current (Note 4) VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop, ∆ITH Voltage: 1.2V to 0.7V Measured in Servo Loop, ∆ITH Voltage: 1.2V to 2V VREFLNREG Reference Voltage Line Regulation VFCB Forced Continuous Threshold IFCB Forced Continuous Current VBINHIBIT Burst Inhibit (Constant Frequency) Threshold Measured at FCB pin VOVL Output Overvoltage Threshold Measured at VEAIN UVLO Undervoltage Lockout VIN Ramping Down gm Transconductance Amplifier gm ITH = 1.2V, Sink/Source 5µA (Note 4) gmOL Transconductance Amplifier Gain ITH = 1.2V, (gm • ZL; No Ext Load) (Note 4) ● ● VIN = 3.6V to 30V (Note 4) ● ● 0.57 V 0.6 0.63 V – 0.17 –1 µA 4.3 4.8 V 0.64 0.66 0.68 V 3 3.33 4 V 3 mmho 1.5 V/mV 3719i 2 LTC3719 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VBIAS = 5V, VRUN/SS = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS IQ Input DC Supply Current Normal Mode Shutdown (Note 5) MIN IRUN/SS Soft-Start Charge Current VRUN/SS = 1.9V – 0.5 –1.2 VRUN/SS RUN/SS Pin ON Threshold VRUN/SS Rising 1.0 1.5 1.9 VRUN/SSLO RUN/SS Pin Latchoff Arming VRUN/SS Rising from 3V 4.1 4.5 V ISCL RUN/SS Discharge Current Soft Short Condition VEAIN = 0.5V, VRUN/SS = 4.5V 2 4 µA ISDLHO Shutdown Latch Disable Current VEAIN = 0.5V 1.6 5 µA ISENSE Total Sense Pins Source Current Each Channel: VSENSE1 –, 2 – = VSENSE1+, 2 + = 0V – 85 – 60 µA DFMAX Maximum Duty Factor In Dropout 98 99.5 % TG1, 2 tr TG1, 2 tf Top Gate Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 30 40 90 90 ns ns BG1, 2 tr BG1, 2 tf Bottom Gate Transition Time: Rise Time Fall Time (Note 6) CLOAD = 3300pF CLOAD = 3300pF 30 20 90 90 ns ns TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver (Note 6) 90 ns BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver (Note 6) 90 ns tON(MIN) Minimum On-Time Tested with a Square Wave (Note 7) 180 ns VRUN/SS = 0V 0.5 TYP MAX 1.2 20 40 UNITS mA µA µA V Internal VCC Regulator VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V VLDO INT INTVCC Load Regulation ICC = 0 to 20mA, VEXTVCC = 4V VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive VLDOHYS EXTVCC Switchover Hysteresis ICC = 20mA, EXTVCC Ramping Negative 4.8 ● 4.5 5.0 5.2 V 0.2 1.0 % 80 160 mV 4.7 V 0.2 V VID Parameters VBIAS Operating Supply Voltage Range 2.7 5.5 RATTEN Resistance Between ATTENIN and ATTENOUT Pins ATTENERR Resistive Divider Error RPULLUP VID0 to VID4 Pull-Up Resistance VIDTHLOW VID0 to VID4 Logic Threshold Low VIDTHHIGH VID0 to VID4 Logic Threshold High VIDLEAK VID0 to VID4 Leakage VBIAS < VID0–VID4 < 7V ±1 µA VNO_CPU NO_CPU Maximum Output Voltage INO_CPU = 2mA 0.4 V 10 ● – 0.35 (Note 8) V kΩ 0.25 40 % kΩ 0.4 1.6 V V 3719i 3 LTC3719 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VBIAS = 5V, VRUN/SS = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator and Phase-Locked Loop fNOM Nominal Frequency VPLLFLTR = 1.2V 190 220 250 kHz fLOW Lowest Frequency VPLLFLTR = 0V 120 140 160 kHz fHIGH Highest Frequency VPLLFLTR ≥ 2.4V 280 310 360 kHz RPLLIN PLLIN Input Resistance IPLLFLTR Phase Detector Output Current Sinking Capability Sourcing Capability RRELPHS fPLLIN < fOSC fPLLIN > fOSC Controller 2-Controller 1 Phase 50 kΩ – 15 15 µA µA 180 Deg PGOOD Output VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 IPGOOD PGOOD Leakage Current VPGOOD = 5V VPG PGOOD Trip Level, Either Controller VEAIN with Respect to Set Output Voltage VEAIN Ramping Negative VEAIN Ramping Positive 0.3 V ±1 µA –8 8 – 10 10 – 12 12 % % 0.995 1 1.005 V/V Differential Amplifier/Op Amp Gain Block ADA Differential Amplifier Gain VAMPMD = 0V CMRRDA Common Mode Rejection Ratio 0V < VCM < 5V; VAMPMD = 0V RIN Input Resistance Measured at VOS + Input; VAMPMD = 0V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3719 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3719EG: TJ = TA + (PD • 85°C/W) Note 4: The LTC3719 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VEAIN. 46 55 dB 80 kΩ Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current ≥ 40% IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 8: Each built-in pull-up resistor attached to the VID inputs also has a series diode to allow input voltages higher than the VIDVCC supply without damage or clamping (see the Applications Information section). 3719i 4 LTC3719 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Load Current (3 Operating Modes) (Figure 13) 100 100 100 80 80 90 70 50 EFFICIENCY (%) FORCED CONTINUOUS MODE 60 CONSTANT FREQUENCY (BURST DISABLED) 40 20 10 0 0.01 0.1 10 1 LOAD CURRENT (A) VIN = 8V 60 VIN = 12V VIN = 20V 40 1 10 LOAD CURRENT (A) 0.1 50 100 600 400 200 200 150 100 50 SHUTDOWN 0 0 20 15 10 25 INPUT VOLTAGE (V) 30 35 0 10 30 20 CURRENT (mA) 40 50 4.95 4.90 4.85 4.80 EXTVCC SWITCHOVER THRESHOLD 4.75 4.70 – 50 – 25 50 25 75 0 TEMPERATURE (°C) 100 125 3719 G06 Maximum Current Sense Threshold vs Percent of Nominal Output Voltage (Foldback) Maximum Current Sense Threshold vs Duty Factor Internal 5V LDO Line Reg INTVCC VOLTAGE 5.00 3719 G05 3719 G04 75 5.1 20 5.05 INTVCC AND EXTVCC SWITCH VOLTAGE (V) EXTVCC VOLTAGE DROP (mV) 800 15 10 INPUT VOLTAGE (V) INTVCC and EXTVCC Switch Voltage vs Temperature 250 ON 5 3719 G03 EXTVCC Voltage Drop 1000 SUPPLY CURRENT (µA) 60 3719 G02 Supply Current vs Input Voltage and Mode 5 70 0 100 3719 G01 0 80 VOUT = 1.6V VEXTVCC = 0V FREQ = 200kHz VFCB = 0V 20 VIN = 5V VOUT = 1.6V FREQ = 200kHz EFFICIENCY (%) VIN = 5V 30 80 ILOAD = 1mA 70 5.0 60 4.8 4.7 50 VSENSE (mV) 4.9 VSENSE (mV) INTVCC VOLTAGE (V) IOUT = 20A VOUT = 1.6V Burst Mode OPERATION 90 EFFICIENCY (%) Efficiency vs Input Voltage (Figure 13) Efficiency vs Load Current (Figure 13) 25 4.6 50 40 30 20 4.5 10 0 4.4 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35 3719 G07 0 20 40 60 DUTY FACTOR (%) 80 100 3719 G08 0 50 100 0 25 75 PERCENT OF NOMINAL OUTPUT VOLTAGE (%) 3719 G09 3719i 5 LTC3719 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Current Sense Threshold vs VRUN/SS (Soft-Start) 80 90 80 VSENSE(CM) = 1.6V 80 70 76 40 60 VSENSE (mV) VSENSE (mV) 60 VSENSE (mV) Current Sense Threshold vs ITH Voltage Maximum Current Sense Threshold vs Sense Common Mode Voltage 72 68 50 40 30 20 10 20 0 64 –10 –20 0 0 1 2 3 5 4 60 6 0 VRUN/SS (V) 3719 G10 FCB = 0V VIN = 15V FIGURE 1 1 1.5 VITH (V) 2 2.5 SENSE Pins Total Source Current 100 VOSENSE = 0.7V 2.0 50 ISENSE (µA) –0.1 –0.2 0.5 3719 G12 VITH vs VRUN/SS (Soft-Start) 2.5 VITH (V) NORMALIZED VOUT (%) 0 3719 G11 Load Regulation 0.0 –30 2 1 COMMON MODE VOLTAGE (V) 1.5 1.0 –0.3 0 –50 0.5 –0.4 0 5 15 10 LOAD CURRENT (A) 20 0 25 0 1 2 3 4 5 6 1 2 VSENSE COMMON MODE VOLTAGE (V) 3719 G14 Maximum Current Sense Threshold vs Temperature 3719 G15 RUN/SS Current vs Temperature Soft-Start Up (Figure 13) 1.8 80 1.6 RUN/SS CURRENT (µA) 78 VSENSE (mV) 0 VRUN/SS (V) 3719 G13 76 74 72 VITH 1V/DIV 1.4 1.2 VOUT 1V/DIV 1.0 VRUN/SS 2V/DIV 0.8 0.6 0.4 100ms/DIV 0.2 70 –50 –100 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3719 G16 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 3718 G18 125 3719 G17 3719i 6 LTC3719 U W TYPICAL PERFOR A CE CHARACTERISTICS Load Step (Figure 13) VIN = 15V, VOUT = 1.25V, SLEW RATE = 30A/µs VCC 50mV/DIV VOUT(AC) 20mV/DIV VIN = 15V, VOUT = 1.6V, IL = 200mARMS VOUT(AC) 20mV/DIV IL1 1A/DIV ICC 4A/DIV 2µs/DIV 3719 G25 10 VOUT = 1.6V 3719 G26 Oscillator Frequency vs Temperature EXTVCC Switch Resistance vs Temperature –12 R9, R21 = 0.01Ω FCB = INTVCC R9, R21 = 0.01Ω 10µs/DIV 3719 G19 Current Sense Pin Input Current vs Temperature 350 –10 –9 –8 50 25 0 75 TEMPERATURE (°C) 100 125 300 8 FREQUENCY (kHz) EXTVCC SWITCH RESISTANCE (Ω) VPLLFLTR = 5V –11 6 4 200 VPLLFLTR = 0V 150 100 50 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 0 – 50 – 25 50 25 75 0 TEMPERATURE (°C) 100 125 3719 G22 3719 G21 Undervoltage Lockout vs Temperature VRUN/SS Shutdown Latch Thresholds vs Temperature 4.5 SHUTDOWN LATCH THRESHOLDS (V) 3.50 3.45 3.40 3.35 3.30 3.25 3.20 –50 –25 250 2 3719 G20 UNDERVOLTAGE LOCKOUT (V) –7 –50 –25 IL2 1A/DIV FCB = OPEN 25µs/DIV VIN = 15V, VOUT = 1.6V, IL = 400mARMS IL1 1A/DIV IL2 1A/DIV FCB = 0V CURRENT SENSE INPUT CURRENT (µA) Constant Frequency Mode (Figure 13) Burst Mode Operation (Figure 13) 50 25 75 0 TEMPERATURE (°C) 100 125 3719 G23 LATCH ARMING 4.0 3.5 3.0 LATCHOFF THRESHOLD 2.5 2.0 1.5 1.0 0.5 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 3719 G24 3719i 7 LTC3719 U U U PI FU CTIO S RUN/SS (Pin 1): Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output. Forcing this pin below 0.8V causes the IC to shut down all internal circuitry. All functions are disabled in shutdown. SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to Each Differential Current Comparator. The ITH pin voltage and built-in offsets between SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold. SENSE1–, SENSE2– (Pins 3,13): The (–) Input to the Differential Current Comparators. EAIN (Pin 4): Input to the error amplifier that compares the feedback voltage to the internal 0.6V reference voltage. This pin is normally connected to a resistive divider from the output of the differential amplifier (DIFFOUT). PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. Do not apply voltage to this pin prior to application of VIN. PLLIN (Pin 6): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. FCB (Pin 7): Forced Continuous Control Input. This input acts on both output stages and can be used to regulate a secondary winding. Pulling this pin below 0.6V will force continuous synchronous operation. Do not leave this pin floating without a decoupling capacitor. ITH (Pin 8): Error Amplifier Output and Switching Regulator Compensation Point. Both current comparator’s thresholds increase with this control voltage. The normal voltage range of this pin is from 0V to 2.4V SGND (Pin 9): Signal Ground. This pin is common to both controllers. Route separately to the PGND pin. VDIFFOUT (Pin 10): Output of a Differential Amplifier. This pin provides true remote output voltage sensing. VDIFFOUT normally drives an external resistive divider that sets the output voltage. VOS–, VOS+ (Pins 11, 12): Inputs to an Operational Amplifier. Internal precision resistors configure it as a differential amplifier whose output is VDIFFOUT. ATTENOUT (Pin 15): Voltage Feedback Signal Resistively Divided According to the VID Programming Code. NO_CPU (Pin 16): Open-Drain Logic Output. NO_CPU is pulled to ground if VID0 to VID3 are all high. VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic Input Pins. VBIAS (Pin 22): Supply Pin for the VID Control Circuit. ATTENIN (Pin 23): The Input to the VID Controlled Resistive Divider. TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top N-Channel MOSFETS. These are the outputs of floating drivers with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. SW2, SW1 (Pins 25, 34): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies to the Topside Floating Drivers. External capacitors are connected between the BOOST and SW pins, and Schottky diodes are connected between the BOOST and INTVCC pins. BG2, BG1 (Pins 27, 31): High Current Gate Drives for Bottom N-Channel MOSFETS. Voltage swing at these pins is from ground to INTVCC. PGND (Pin 28): Driver Power Ground. Connect to sources of bottom N-channel MOSFETS and the (–) terminals of CIN. INTVCC (Pin 29): Output of the Internal 5V Linear Low Dropout Regulator and the EXTVCC Switch. The driver and control circuits are powered from this voltage source. Decouple to power ground with a 1µF ceramic capacitor placed directly adjacent to the IC and minimum of 4.7µF additional tantalum or other low ESR capacitor. EXTVCC (Pin 30): External Power Input to an Internal Switch. This switch closes and supplies INTVCC, bypassing the internal low dropout regulator whenever EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 7V on this pin and ensure VEXTVCC ≤ VINTVCC. 3719i 8 LTC3719 U U U PI FU CTIO S VIN (Pin 32): Main Supply Pin. Should be closely decoupled to the IC’s signal ground pin. PGOOD (Pin 36): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the EAIN pin is not within ±10% of its set point. W FU CTIO AL DIAGRA U U PLLIN PHASE DET fIN 50k INTVCC RLP PLLFLTR DUPLICATE FOR SECOND CONTROLLER CHANNEL CLK1 CLP OSCILLATOR BOOST CLK2 TO SECOND CHANNEL PGOOD – DROP OUT DET 0.66V + S Q R Q BOT TOP ON SWITCH LOGIC + CIN INTVCC B BG COUT PGND + 40k 0.55V + SW BOT 0.54V CB FCB – + DB D1 EAIN VOS – TG TOP VIN – 40k SHDN L 1 RSENSE VOUT 2 – A1 VOS + + 40k 40k I1 – + DIFFOUT – ++ – – 4.5V 0.18µA SLOPE COMP + – 30k SENSE 45k 45k 2.4V + – FCB – EA + VREF 0.60V OV 4.8V – EXTVCC 5V + 5V LDO REG 0.60V EAIN + – SHDN RST 5VFB 6V + ATTENIN VFB 0.66V CC 1.2µA INTVCC RUN SOFTSTART INTERNAL SUPPLY SGND 4 + 30k SENSE + – FCB VIN INTVCC I2 0.86V 5VFB 3V 3 ITH RUN/SS CC2 RC CSS 10k 5-BIT VID DECODER ATTENOUT TYPICAL ALL VID PINS 40k R1 NO_CPU VID0 VID1 VID2 VID3 VID4 VBIAS 3719 FBD 3719i 9 LTC3719 U OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC3719 uses a constant frequency, current mode step-down architecture with the two output stages operating 180 degrees out of phase. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator, I1, resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of error amplifier EA. The EAIN pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases, it causes a slight decrease in VEAIN relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which normally is recharged during each off cycle through an external diode when the top MOSFET turns off. As VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 500ns every tenth cycle to allow CB to recharge. The main control loop is shut down by pulling the RUN/ SS pin low. Releasing RUN/SS allows an internal 1.2µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, the ITH pin voltage is gradually released allowing normal, full-current operation. Low Current Operation The FCB pin is a multifunction pin providing two functions: 1) to provide regulation for a secondary winding by temporarily forcing continuous PWM operation on both controllers; and 2) select between two modes of low current operation. When the FCB pin voltage is below 0.6V, the controller forces continuous PWM current mode operation. In this mode, the top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below VINTVCC␣ –␣ 2V but greater than 0.6V, the controller enters Burst Mode operation. Burst Mode operation sets a minimum output current level before inhibiting the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low currents, force the ITH pin below a voltage threshold that will temporarily inhibit turn-on of both output MOSFETs until the output voltage drops. There is 60mV of hysteresis in the burst comparator B tied to the ITH pin. This hysteresis produces output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. Constant Frequency Operation When the FCB pin is tied to INTVCC, Burst Mode operation is disabled and a forced minimum peak output current requirement is removed. This provides constant frequency, discontinuous (preventing reverse inductor current) current operation over the widest possible output current range. This constant frequency operation is not as efficient as Burst Mode operation, but does provide a lower noise, constant frequency operating mode down to approximately 1% of designed maximum output current. Continuous Current (PWM) Operation Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels— BEWARE! 3719i 10 LTC3719 U OPERATIO (Refer to Functional Diagram) Frequency Synchronization The phase-locked loop allows the internal oscillator to be synchronized to an external source via the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator that operates over a 140kHz to 310kHz range corresponding to a DC voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When PLLIN is left open, the PLLFLTR pin goes low, forcing the oscillator to minimum frequency. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by two and power loss is proportional to the RMS current squared. A two stage, single output voltage implementation can reduce input path power loss by 75% and radically reduce the required RMS current rating of the input capacitor(s). INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most of the IC circuitry is derived from INTVCC. When the EXTVCC pin is left open, an internal 5V low dropout regulator supplies INTVCC power. If the EXTVCC pin is taken above 4.8V, the 5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. This allows the INTVCC power to be derived from a high efficiency external source such as the output of the regulator itself or a secondary winding, as described in the Applications Information section. An external Schottky diode can be used to minimize the voltage drop from EXTVCC to INTVCC in applications requiring greater than the specified INTVCC current. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability. Differential Amplifier This controller includes a true unity-gain differential amplifier. Sensing both VOUT + and VOUT – benefits regulation in high current applications and/or applications having electrical interconnection losses. The amplifier is a unity-gain stable, 2MHz gain-bandwidth, >120dB openloop gain design. The amplifier has an output slew rate of 5V/µs and is capable of driving capacitive loads with an output RMS current typically up to 25mA. The amplifier is not capable of sinking current and therefore must be resistively loaded to do so. Output Overvoltage Protection An overvoltage comparator, 0V, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Power Good (PGOOD) The PGOOD pin is connected to the drain of an internal MOSFET. The MOSFET turns on when the output voltage is not within ±10% of its nominal output level as determined by the feedback divider. When the output is within ±10% of its nominal value, the MOSFET is turned off within 10µs and the PGOOD pin should be pulled up by an external resistor to a source of up to 7V. Short-Circuit Detection The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full-load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage the RUN/SS capacitor begins discharging assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overidden by providing a current >5µA at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. 3719i 11 LTC3719 U W U U APPLICATIO S I FOR ATIO plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to PhaseLocked Loop and Frequency Synchronization for additional information. A graph for the voltage applied to the PLLFLTR pin vs frequency is given in Figure␣ 2. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 310kHz. 2.5 PLLFLTR PIN VOLTAGE (V) The basic LTC3719 application circuit is shown in Figure␣ 1 on the first page. External component selection begins with the selection of the inductors based on ripple current requirements and continues with the current sensing resistors using the calculated peak inductor current and/or maximum current limit. Next, the power MOSFETs, D1 and D2 are selected. The operating frequency and the inductor are chosen based mainly on the amount of ripple current. Finally, CIN is selected for its ability to handle the input ripple current (that PolyPhase TM operation minimizes) and COUT is chosen with low enough ESR to meet the output ripple voltage and load step specifications (also minimized with PolyPhase). Current mode architecture provides inherent current sharing between output stages. The circuit shown in Figure␣ 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). Current mode control allows the ability to connect the two output stages to two different input power supply rails. A heavy output load can take some power from each input supply according to the selection of the RSENSE resistors. 2.0 1.5 1.0 0.5 0 120 170 220 270 OPERATING FREQUENCY (kHz) RSENSE Selection For Output Current RSENSE1,2 are chosen based on the required peak output current. The LTC3719 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1(INTVCC). The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. Assuming a common input power source for each output stage and allowing a margin for variations in the LTC3719 and external component values yields: RSENSE = 2(50mV/IMAX) Operating Frequency The LTC3719 uses a constant frequency, phase-lockable architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current 320 3719 F02 Figure 2. Operating Frequency vs VPLLFLTR Inductor Value Calculation and Output Ripple Current The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because MOSFET gate charge and transition losses increase directly with frequency. In addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. PolyPhase is a registered trademark of Linear Technology Corporation. 3719i 12 LTC3719 U W U U APPLICATIO S I FOR ATIO The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT: ∆IL = VOUT VOUT 1− f •L VIN Inductor Core Selection where f is the individual output stage operating frequency. In a 2-phase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 3 shows the net ripple current seen by the output capacitors for 1- and 2-phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations, simplifying the design process. Accepting larger values of ∆IL allows the use of low inductances, but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is 1.0 1-PHASE 2-PHASE 0.9 0.8 0.7 0.6 VO/fL ∆IO(P-P) ∆IL = 0.4(IOUT)/2, where IOUT is the total load current. Remember, the maximum ∆IL occurs at the maximum input voltage. The individual inductor ripple currents are determined by the inductor, input and output voltages. 0.5 0.4 Once the values for L1 and L2 are known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductor type selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly. 0.3 Power MOSFET, D1 and D2 Selection 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 3719 F03 Figure 3. Normalized Output Ripple Current vs Duty Factor [IRMS ≈ 0.3 (∆IO(P–P))] Two external power MOSFETs must be selected for each output stage with the LTC3719: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. Kool Mµ is a registered trademark of Magnetics, Inc. 3719i 13 LTC3719 U U W U APPLICATIO S I FOR ATIO The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sublogic-level threshold MOSFETs (VGS(TH) < 1V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. which peak at the highest input voltage. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actual provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC3719 is operating in continuous mode the duty factors for the top and bottom MOSFETs of each output stage are given by: The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. Main Switch Duty Cycle = VOUT VIN V –V Synchronous Switch Duty Cycle = IN OUT VIN The MOSFET power dissipations at maximum output current are given by: 2 PMAIN = VOUT IMAX (1 + δ )RDS(ON) + VIN 2 2 I k( VIN ) MAX (CRSS )( f) 2 2 PSYNC = VIN – VOUT IMAX (1 + δ )RDS(ON) 2 VIN where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses but the topside N-channel equation includes an additional term for transition losses, The Schottky diodes, D1 and D2 shown in Figure 1 conduct during the dead-time between the conduction of the two large power MOSFETs. This helps prevent the body diode of the bottom MOSFET from turning on, storing charge during the dead-time, and requiring a reverse recovery period which would reduce efficiency. A 1A to 3A Schottky (depending on output current) diode is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a closed form equation can be found in Application Note 77. Figure 4 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple 3719i 14 LTC3719 U W U U APPLICATIO S I FOR ATIO current can be achieved when the input voltage is twice the output voltage. In the graph of Figure 4, the 2-phase local maximum input RMS capacitor currents are reached when: The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirements. The steady state output ripple (∆VOUT) is determined by: VOUT 2k − 1 = VIN 4 where k = 1, 2 These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-phase implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the 0.5 DC LOAD CURRENT RMS INPUT RIPPLE CURRNET 0.6 0.4 1-PHASE 2-PHASE 0.3 0.2 0.1 0 0.1 0.2 reduction of the input ripple current in a 2-phase system. The required amount of input capacitance is further reduced by the factor, 2, due to the effective increase in the frequency of the current pulses. 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 3719 F04 Figure 4. Normalized RMS Input Ripple Current vs Duty Factor for 1 and 2 Output Stages 1 ∆VOUT ≈ ∆IRIPPLE ESR + 16 fCOUT Where f = operating frequency of each stage, COUT = output capacitance and ∆IRIPPLE = combined inductor ripple currents. The output ripple varies with input voltage since ∆IL is a function of input voltage. The output ripple will be less than 50mV at max VIN with ∆IL = 0.4IOUT(MAX)/2 assuming: COUT required ESR < 4(RSENSE) and COUT > 1/(16f)(RSENSE) The emergence of very low ESR capacitors in small, surface mount packages makes very physically small implementations possible. The ability to externally compensate the switching regulator loop using the I TH pin(OPTI-LOOP compensation) allows a much wider selection of output capacitor types. OPTI-LOOP compensation effectively removes constraints on output capacitor ESR. The impedance characteristics of each capacitor type are significantly different than an ideal capacitor and therefore require accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat 3719i 15 LTC3719 U W U U APPLICATIO S I FOR ATIO higher price. An additional ceramic capacitor in parallel with OS-CON type capacitors is recommended to reduce the inductance effects. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON, POSCAPs, Panasonic SP caps, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. A combination of capacitors will often result in maximizing performance and minimizing overall cost and size. INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. The INTVCC regulator powers the drivers and internal circuitry of the LTC3719. The INTVCC pin regulator can supply up to 50mA peak and must be bypassed to power ground with a minimum of 4.7µF tantalum or electrolytic capacitor. An additional 1µF ceramic capacitor placed very close to the IC is recommended due to the extremely high instantaneous currents required by the MOSFET gate drivers. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3719 to be exceeded. The supply current is dominated by the gate charge supply current, in addition to the current drawn from the differential amplifier output. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The supply current can either be supplied by the internal 5V regulator or via the EXTVCC pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC load current is supplied by the internal 5V linear regulator. Power dissipation for the IC is higher in this case by (IIN)(VIN – INTVCC) and efficiency is lowered. The junction temperature can be estimated by using the equations given in Note 1 of the Electrical Characteristics. For example, the LTC3719 VIN current is limited to less than 24mA from a 24V supply: TJ = 70°C + (24mA)(24V)(85°C/W) = 119°C Use of the EXTVCC pin reduces the junction temperature␣ to: TJ = 70°C + (24mA)(5V)(85°C/W) = 80.2°C The input supply current should be measured while the controller is operating in continuous mode at maximum VIN and the power dissipation calculated in order to prevent the maximum junction temperature from being exceeded. EXTVCC Connection The LTC3719 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. When the voltage applied to EXTVCC rises above 4.7V, the internal regulator is turned off and an internal switch closes, connecting the EXTVCC pin to the INTVCC pin thereby supplying internal and MOSFET gate driving power to the IC. The switch remains closed as long as the voltage applied to EXTVCC remains above 4.5V. This allows the MOSFET driver and control power to be derived from the output during normal operation (4.7V < VEXTVCC < 7V) and from the internal regulator when the output is out of regulation (start-up, short-circuit). Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN + 0.3V when using the application circuits shown. If an external voltage source is applied to the EXTVCC pin when the VIN supply is not present, a diode can be placed in series with the LTC3719’s VIN pin and a Schottky diode between the EXTVCC and the VIN pin, to prevent current from backfeeding VIN. 3719i 16 LTC3719 U W U U APPLICATIO S I FOR ATIO Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by the ratio: (Duty Factor)/(Efficiency). For 5V regulators this means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional supply circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5V regulator resulting in a significant efficiency penalty at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. 4. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an outputderived voltage which has been boosted to greater than Topside MOSFET Driver Supply (CB,DB) (Refer to Functional Diagram) External bootstrap capacitors CB1 and CB2 connected to the BOOST1 and BOOST2 pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from INTVCC when the SW pin is low. When the topside MOSFET turns on, the driver places the CB voltage across the gatesource of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin rises to VIN + VINTVCC. The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of DB must be greater than VIN(MAX). The final arbiter when defining the best gate drive amplitude level will be the input supply current. If a change is made that decreases input current, the efficiency has improved. If the input current does not change then the efficiency has not changed either. + OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V + VIN 1N4148 + EXTVCC T1 BG1 3 4 VOUT SW1 COUT BG1 + BAT85 BAT85 VN2222LL 1 RSENSE 2 L1 3 4 VOUT + COUT N-CH N-CH R5 0.22µF EXTVCC 1 RSENSE 2 R6 N-CH LTC3719 1µF N-CH SW1 BAT85 TG1 VSEC TG1 LTC3719 + VIN CIN VIN CIN VIN FCB 4.7V but less than 7V. This can be done with either the inductive boost winding as shown in Figure 5a or the capacitive charge pump shown in Figure 5b. The charge pump has the advantage of simple magnetics. PGND PGND 3716 F05a Figure 5a. Secondary Output Loop with EXTVCC Connection 3716 F05b Figure 5b. Capacitive Charge Pump for EXTVCC 3719i 17 LTC3719 U W U U APPLICATIO S I FOR ATIO Output Voltage Table 1. VID Output Voltage Programming CODE VID4 VID3 VID2 VID1 VID0 OUTPUT 00000 GND GND GND GND GND 1.550 00001 GND GND GND GND Float 1.525 00010 GND GND GND Float GND 1.500 00011 GND GND GND Float Float 1.475 00100 GND GND Float GND GND 1.450 00101 GND GND Float GND Float 1.425 00110 GND GND Float Float GND 1.400 00111 GND GND Float Float Float 1.375 01000 GND Float GND GND GND 1.350 The output voltage is digitally programmed as defined in Table 1 using the VID0 to VID4 logic input pins. The VID logic inputs program a precision, 0.25% internal feedback resistive divider. The LTC3719 has an output voltage range of 0.8V to 1.55V in 25mV steps. 01001 GND Float GND GND Float 1.325 01010 GND Float GND Float GND 1.300 Between the ATTENOUT pin and ground is a variable resistor, R1, whose value is controlled by the five VID input pins (VID0 to VID4). Another resistor, R2, between the ATTENIN and the ATTENOUT pins completes the resistive divider. The output voltage is thus set by the ratio of (R1␣ +␣ R2) to R1. The LTC3719 has a true remote voltage sense capablity. The sensing connections should be returned from the load back to the differential amplifier’s inputs through a common, tightly coupled pair of PC traces. The differential amplifier corrects for DC drops in both the power and ground paths. The differential amplifier output signal is divided down and compared with the internal precision 0.6V voltage reference by the error amplifier. Output Voltage Programming Each VID digital input is pulled up by a 40k resistor in series with a diode from VBIAS. Therefore, it must be grounded to get a digital low input, and can be either floated or connected to VBIAS to get a digital high input. The series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than VBIAS. The digital inputs accept CMOS voltage levels. VBIAS is the supply voltage for the VID section. It is normally connected to INTVCC but can be driven from other sources. If it is driven from another source, that source must be in the range of 2.7V to 5.5V and must be alive prior to enabling the LTC3719. 01011 GND Float GND Float Float 1.275 01100 GND Float Float GND GND 1.250 01101 GND Float Float GND Float 1.225 01110 GND Float Float Float GND 1.200 01111 GND Float Float Float Float 1.175 10000 Float GND GND GND GND 1.150 10001 Float GND GND GND Float 1.125 10010 Float GND GND Float GND 1.100 10011 Float GND GND Float Float 1.075 10100 Float GND Float GND GND 1.050 10101 Float GND Float GND Float 1.025 10110 Float GND Float Float GND 1.000 10111 Float GND Float Float Float 0.975 11000 Float Float GND GND GND 0.950 11001 Float Float GND GND Float 0.925 11010 Float Float GND Float GND 0.900 11011 Float Float GND Float Float 0.875 11100 Float Float Float GND GND 0.850 11101 Float Float Float GND Float 0.825 11110 Float Float Float Float GND 0.800 11111 Float Float Float Float Float Shutdown 3719i 18 LTC3719 U W U U APPLICATIO S I FOR ATIO Soft-Start/Run Function The RUN/SS pin provides three functions: 1) Run/Shutdown, 2) soft-start and 3) a defeatable short-circuit latchoff timer. Soft-start reduces the input power sources’ surge currents by gradually increasing the controller’s current limit ITH(MAX). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the RUN/ SS pin will prevent the overcurrent latch from operating. The following explanation describes how the functions operate. An internal 1.2µA current source charges up the soft-start capacitor, CSS. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.4s/µF to reach full current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: tDELAY = 1.5V CSS = (1.25s /µF ) CSS 1.2µA The time for the output current to ramp up is then: tIRAMP = 3V − 1.5V CSS = (1.25s /µF ) CSS 1.2µA By pulling the RUN/SS pin below 0.8V the LTC3719 is put into low current shutdown (IQ < 40µA). The RUN/SS pins can be driven directly from logic as shown in Figure 6. Diode D1 in Figure 6 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. The RUN/SS pin has an internal 6V zener clamp (see Functional Diagram). INTVCC VIN 3.3V OR 5V D1 RUN/SS RSS* RSS* D1* RUN/SS CSS CSS *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF 3719 F06 Figure 6. RUN/SS Pin Interfacing Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor, CSS, is used initially to limit the inrush current of both controllers. After the controllers have been started and been given adequate time to charge up the output capacitors and provide full load current, the RUN/ SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 70% of its nominal value after CSS reaches 4.1V, CSS begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period as determined by the size of the CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by: tLO1 ≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS) If the overload occurs after start-up, the voltage on CSS will continue charging and will provide additional time before latching off: tLO2 ≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor, RSS, to the RUN/SS pin as shown in Figure 6. This resistance shortens the soft-start period and prevents the discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit 3719i 19 LTC3719 U W U U APPLICATIO S I FOR ATIO condition. When deriving the 5µA current from VIN as in the figure, current latchoff is always defeated. The diode connecting this pull-up resistor to INTVCC, as in Figure␣ 6, eliminates any extra supply current during shutdown while eliminating the INTVCC loading from preventing controller start-up. Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal short-circuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. The value of the soft-start capacitor CSS may need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range, ∆fH, is equal to the capture range, ∆fC: ∆fH = ∆fC = ±0.5 fO (150kHz-300kHz) The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLFLTR pin. A simplified block diagram is shown in Figure 7. 2.4V PHASE DETECTOR RLP 10k CLP EXTERNAL OSC PLLFLTR PLLIN 50k DIGITAL PHASE/ FREQUENCY DETECTOR CSS > (COUT )(VOUT)(10-4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. Phase-Locked Loop and Frequency Synchronization The LTC3719 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ±50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 220kHz. The nominal operating frequency range of the LTC3719 is 140kHz to 310kHz. The phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the OSC 3719 F07 Figure 7. Phase-Locked Loop Block Diagram If the external frequency (fPLLIN) is greater than the oscillator frequency f0SC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than f0SC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The LTC3719 PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. 3719i 20 LTC3719 U W U U APPLICATIO S I FOR ATIO The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP is 0.01µF to 0.1µF. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC3719 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN ( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3719 will begin to skip cycles resulting in variable frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the LTC3719 is generally less than 200ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger ripple current and voltage ripple. If an application can operate close to the minimum on-time limit, an inductor must be chosen that has a low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current of each phase equal to or greater than 15% of IOUT(MAX) at VIN(MAX). FCB Pin Operation The FCB pin can be used to regulate a secondary winding or as a logic level input. Continuous operation is forced when the FCB pin drops below 0.6V. During continuous mode, current flows continuously in the transformer primary. The secondary winding(s) supply current only when the bottom, synchronous switch is on. When primary load currents are low and/or the VIN/VOUT ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous operation will support secondary windings providing there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary winding(s). With the loop in continuous mode, the auxiliary output(s) may nominally be loaded without regard to the primary output load. The secondary output voltage VSEC is normally set as shown in Figure 5a by the turns ratio N of the transformer: VSEC ≅ (N + 1) VOUT However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VSEC will droop. An external resistive divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN): R6 VSEC(MIN) ≈ 0.6 V 1 + R5 where R5 and R6 are shown in Figure 5a. If VSEC drops below this level, the FCB voltage forces temporary continuous switching operation until VSEC is again above its minimum. In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.18µA internal current source pulling the pin high. Include this current when choosing resistor values R5 and R6. 3719i 21 LTC3719 U U W U APPLICATIO S I FOR ATIO The following table summarizes the possible states available on the FCB pin: Table 2 Efficiency Considerations FCB Pin Condition 0V to 0.55V Forced Continuous (Current Reversal Allowed—Burst Inhibited) 0.65V < VFCB < 4.3V (typ) Minimum Peak Current Induces Burst Mode Operation No Current Reversal Allowed Feedback Resistors Regulating a Secondary Winding >4.8V Burst Mode Operation Disabled Constant Frequency Mode Enabled No Current Reversal Allowed No Minimum Peak Current Active Voltage Positioning Active voltage positioning can be used to minimize peakto-peak output voltage excursion under worst-case transient loading conditions. The open-loop DC gain of the control loop is reduced depending upon the maximum load step specifications. Active voltage positioning can easily be added to the LTC3719 by loading the ITH pin with a resistive divider having a Thevenin equivalent voltage source equal to the midpoint operating voltage of the error amplifier, or 1.2V (see Figure 8). INTVCC RT2 ITH RT1 RC explanation is included in Design Solutions 10 or the LTC1736 data sheet. (See www.linear-tech.com) LTC3719 CC 3719 F08 Figure 8. Active Voltage Positioning Applied to the LTC3719 The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The worst-case peak-to-peak output voltage deviation due to transient loading can theoretically be reduced to half or alternatively the amount of output capacitance can be reduced for a particular application. A complete The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3719 circuits: 1) I2R losses, 2) Topside MOSFET transition losses, 3) INTVCC regulator current and 4) LTC3719 VIN current (including loading on the differential amplifier output). 1) I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode the average output current flows through L and RSENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, and RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A per output stage for a 5V output, or a 3% to 12% loss per output stage for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 3719i 22 LTC3719 U W U U APPLICATIO S I FOR ATIO 2) Transition losses apply only to the topside MOSFET(s), and are significant only when operating at high input voltages (typically 12V or greater). Transition losses can be estimated from: IO(MAX) Transition Loss = (1.7)VIN2 CRSS f 2 3) INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = (QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by the ratio (Duty Factor)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 4) The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the differential amplifier output. VIN current typically results in a small (<0.1%) loss. Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and input fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and a very low ESR at the switching frequency. A 50W supply will typically require a minimum of 200µF to 300µF of output capacitance having a maximum of 10mΩ to 20mΩ of ESR. The LTC3719 2-phase architecture typically halves the input and output capacitance requirements over competing solutions. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD(ESR), where ESR is the effective series resistance of COUT (∆ILOAD) also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time, and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon first because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of <2µs will 3719i 23 LTC3719 U W U U APPLICATIO S I FOR ATIO produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the Ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. Design Example As a design example, assume VIN = 5V (nominal), VIN␣ =␣ 5.5V (max), VOUT = 1.2V, IMAX = 20A, TA = 70°C and f␣ =␣ 300kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the FREQSET pin to the INTVCC pin for 300kHz operation. The minimum inductance for 30% ripple current is: L≥ ≥ VOUT VOUT 1− f( ∆L) VIN 1.2V 1.2V 1− (300kHz)(30%)(10A) 5.5V ≥ 1.04µH A 1µH inductor will produce 31% ripple current. The peak inductor current will be the maximum DC value plus one half the ripple current, or 11.5A. The minimum on-time occurs at maximum VIN: tON(MIN) = The RSENSE resistors value can be calculated by using the maximum current sense voltage specification with some accomodation for tolerances: RSENSE = 50mV ≈ 0.004Ω 11.5A The power dissipation on the topside MOSFET can be easily estimated. Using a Siliconix Si4420DY for example; RDS(ON) = 0.013Ω, CRSS = 300pF. At maximum input voltage with TJ (estimated) = 110°C at an elevated ambient temperature: [ ] 1.2V 2 10) 1 + (0.005)(110°C − 25°C) ( 5.5V PMAIN = 0.013Ω + 1.7(5.5V ) (10 A )(300pF ) 2 (300kHz) = 0.45W The worst-case power disipated by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50°C junction temperature rise is: 5.5V − 1.2V 2 2(10 A ) (1.48)(0.013Ω) 5.5V = 1.5W PSYNC = A short-circuit to ground will result in a folded back current of about: ISC = 25mV 1 200ns(5.5V ) + = 6.8 A 0.004Ω 2 1µH The worst-case power disipated by the synchronous MOSFET under short-circuit conditions at elevated ambient temperature and estimated 50°C junction temperature rise is: 5.5V − 1.2V 2 6.8 A ) (1.48)(0.013Ω) ( 5.5V = 696mW PSYNC = VOUT 1.2V = = 0.73µs VIN f (5.5V )(300kHz) 3719i 24 LTC3719 U W U U APPLICATIO S I FOR ATIO which is less than normal, full-load conditions. Incidentally, since the load no longer dissipates power in the shorted condition, total system power dissipation is decreased by over 99%. The duty factor for this application is: DF = VO 1.2V = = 0.24 VIN 5V Using Figure 4, the RMS ripple current will be: 2) Does the LTC3719 VOS+ pin connect to the point of load? Does the LTC3719 VOS– pin connect to the load return? 3) Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The filter capacitors between SENSE + and SENSE – pin pairs should be as close as possible to the LTC3719. Ensure accurate current sensing with Kelvin connections at the current sense resistor. See Figure 9. IINRMS = (20A)(0.25) = 5ARMS PADS OF SENSE RESISTOR An input capacitor(s) with a 5ARMS ripple current rating is required. TRACE TO OUTPUT CAP (+) TRACE TO INDUCTOR The output capacitor ripple current is calculated by using the inductor ripple already calculated for each inductor and multiplying by the factor obtained from Figure␣ 3 along with the calculated duty factor. The output ripple in continuous mode will be highest at the maximum input voltage since the duty factor is < 50%. The maximum output current ripple is: VOUT (0.5) at 24% D F fL 1.2V ∆ICOUTMAX = 0.5 (300kHz)(1.0µH) ∆ICOUT = = 2AP-P VOUTRIPPLE = 20mΩ(2AP-P ) = 40mVP-P PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3719. Check the following in your layout: 1) Are the signal and power grounds separate? The signal ground traces should return to Pin 9 first. Connect Pin 9 to Pin 28 through a wide and straight trace. Then the signal ground joins the power ground plane beside Pin 28. It is recommended that the Pin 28 return to the (–) plates of CIN. 3719 F09 SENSE + SENSE – Figure 9. Proper Current Sense Connections 4) Does the (+) plate of CIN connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the AC current to the MOSFETs. Keep the input current path formed by the input capacitor, top and bottom MOSFETs, and the Schottky diode on the same side of the PC board in a tight loop to minimize conducted and radiated EMI. 5) Is the INTVCC 1µF ceramic decoupling capacitor connected closely between INTVCC and the PGND pin? This capacitor carries the MOSFET driver peak currents. A small value is recommended to allow placement immediately adjacent to the IC. 6) Keep the switching nodes, SW1 (SW2), away from sensitive small-signal nodes. Ideally the switch nodes should be placed at the furthest point from the LTC3719. 7) Use a low impedance source such as a logic gate to drive the PLLIN pin and keep the lead as short as possible. 3719i 25 LTC3719 U W U U APPLICATIO S I FOR ATIO The diagram in Figure 10 illustrates all branch currents in a 2-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high-switching-current paths to a small physical size. High electric and magnetic fields will radiate from these “loops” just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the “noise” generated by a switching regulator. The ground terminations of the sychronous MOSFETs and Schottky diodes should return to the negative plate(s) SW1 of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the negative plate(s) of the input capacitor(s) should be used to tie in the IC power ground pin (PGND) and the signal ground pin (SGND). This technique keeps inherent signals generated by high current pulses from taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. L1 RSENSE1 D1 VIN VOUT RIN CIN + + SW2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH. L2 COUT RL RSENSE2 D2 3719 F10 Figure 10. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator 3719i 26 LTC3719 U U W U APPLICATIO S I FOR ATIO Simplified Visual Explanation of How a 2-Phase Controller Reduces Both Input and Output RMS Ripple Current requirement is thus reduced theoretically by a factor of four! Ceramic input capacitors with their unbeatably low ESR characteristics can be used. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 11 graphically illustrates the principle. Figure 4 illustrates the RMS input current drawn from the input capacitance vs the duty cycle as determined by the ratio of input and output voltage. The peak input RMS current level of the single phase system is reduced by 50% in a 2-phase solution due to the current splitting between the two stages. The worst-case RMS ripple current for a single stage design peaks at an input voltage of twice the output voltage. The worst-case RMS ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. When the RMS current is calculated, higher effective duty factor results and the peak current levels are divided as long as the currents in each stage are balanced. Refer to Application Note 19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figures 3 and 4 illustrate how the input and output currents are reduced by using an additional phase. The input current peaks drop in half and the frequency is doubled for this 2-phase converter. The input capacity The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge current term from the stage that has its bottom MOSFET on subtracts current from the (VIN – VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current is: An interesting result of the 2-phase solution is that the VIN which produces worst-case ripple current for the input capacitor, VOUT = VIN/2, in the single phase design produces zero input current ripple in the 2-phase design. ∆IRIPPLE = where D is duty factor. SINGLE PHASE SW V 2VOUT 1 − 2D (1 − D) fL 1 − 2D + 1 DUAL PHASE SW1 V SW2 V ICIN IL1 ICOUT IL2 ICIN ICOUT RIPPLE 3719 F11 Figure 11. Single and 2-Phase Current Waveforms 3719i 27 LTC3719 U W U U APPLICATIO S I FOR ATIO The input and output ripple frequency is increased by the number of stages used, reducing the output capacity requirements. When VIN is approximately equal to 2(VOUT) as illustrated in Figures 3 and 4, very low input and output ripple currents result. Figure 12 shows a typical application using LTC3719 to power the AMD CPU core. The input can vary from 7V to 24V, the output voltage can be programmed from 0.8V to 1.55V with a maximum current of 45A. This power supply receives three input signals to generate different output voltage offsets based on the operation conditions. 3719i 28 PWRGD SYNC VID4 VID3 VID2 VID1 VID0 ENABLE C31 0.1µF R19 2.7k Q9 (OPT) 2N7002 R20 10k C25 27pF C21 27pF INTVCC R24 OPT C32 1nF RUN/SS C17 1nF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SENSE2 + SENSE2 – VOS+ VOS– VDIFFOUT SGND ITH PHASMD PLLIN PLLFLTR EAIN SENSE1– SENSE1+ AMPMD TG2 SW2 BOOST2 BG2 PGND INTVCC EXTVCC BG1 VIN BOOST1 SW1 TG1 CLKOUT VID2 VID3 VID4 VBIAS ATTENIN TG2 SW2 BOOST2 BG2 PGND INTVCC EXTVCC BG1 VIN BOOST1 SW1 TG1 PGOOD LTC1629-6 RUN/SS VID1 VID0 NO_CPU ATTENOUT SENSE2 + SENSE2 – VOS+ VOS– VDIFFOUT SGND ITH FCB PLLIN PLLFLTR EAIN SENSE1– SENSE1+ RUN/SS LTC3719 15 16 17 18 19 20 21 22 23 24 25 26 27 28 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CLK1 + C26 2.2µF + C23 0.1µF R12 10Ω C11 2.2µF INTVCC C7 0.1µF C29 0.47µF C27 10µF C18 0.1µF C15 0.47µF C12 10µF Q3 1 2 3 Q4 5 6 7 8 1 2 3 5 6 7 8 Q1 D4 MBRS340T3 C13 0.47µF 1 2 3 Q2 5 6 7 8 1 2 3 5 6 7 8 L2 1µH D6 BAT54A C22 0.47µF 1 2 3 Q8 5 6 7 8 1 2 3 Q7 5 6 7 8 R14 10Ω D7 MBRS340T3 C28 0.47µF 1 2 3 Q6 5 6 7 8 1 2 3 Q5 5 6 7 8 L4 1µH 10Ω 10Ω 10Ω 10Ω 10Ω 4 3 R18 10Ω 1 0.002Ω 2 1 3719 F12 10Ω 4 R17 4 0.002Ω 3 3 R7 1 1 0.002Ω 2 2 D5 MBRS340T3 L3 1µH C19 0.47µF 10Ω R5 4 0.002Ω 3 2 D2 MBRS340T3 L1 1µH C2 0.47µF CIN1: EIGHT 10µF 16V CERAMIC CAPACITORS COUT1: TEN 22µF 6.3V CERAMIC CAPACITORS L1 TO L4: SUMIDA CEPH125-1R0MC-H Q1, Q3, Q5, Q7: TWO IRF7811W OR TWO Si7448DP Q2, Q4, Q6, Q8: THREE IRF7822 OR THREE Si7448DP D3 BAT54A C5 0.47µF R1 10Ω Figure 12. 4-Phase 12V Input, 0.8V to 1.55V/80A Max Power Supply for Server Applications C20 1nF 18 17 16 15 14 13 12 11 10 9 C10 220pF 7 6 5 4 3 2 1 8 C14 470pF CLK1 C3 1nF R6 1.5k C9 2200pF R23 OPT C6 1nF R4 10k C1 0.1µF RUN/SS C4 0.01µF D1 BAT54 C30 0.47µF C24 0.47µF C16 0.47µF C8 0.47µF + COUT1 CIN1 R8 50Ω R9 50Ω COREFB_L COREFB_H GND VDD_CORE+ GND 12VIN LTC3719 TYPICAL APPLICATIO 3719i 29 U 30 PWRGD VID4 VID3 VID2 VID1 VID0 ENABLE C1 0.1µF Q9 (OPT) 2N7002 C17 1nF VDIFFOUT SGND ITH FCB PLLIN PLLFLTR EAIN 18 17 16 15 14 13 VID1 VID0 NO_CPU ATTENOUT SENSE2 + SENSE2 – VOS– 12 VOS+ 11 10 + SENSE1– SENSE1 RUN/SS VID2 VID3 VID4 VBIAS ATTENIN TG2 SW2 BOOST2 BG2 PGND INTVCC EXTVCC BG1 VIN BOOST1 SW1 TG1 PGOOD LTC3719 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 + R12 10Ω C11 2.2µF INTVCC C7 1µF C18 0.1µF C15 0.47µF C12 10µF D3 BAT54A C5 0.47µF 5 6 7 8 Q4 Si7448DP 1 2 3 ×3 D4 UPS840 C13 0.47µF 5 6 7 8 Q2 Si7448DP 1 2 3 ×3 5 6 7 8 Q1 Si7448DP 1 2 3 ×2 5 6 7 8 Q3 Si7448DP 1 2 3 ×2 R1 10Ω L2 0.8µH 4 3 D2 UPS840 L1 0.8µH C2 0.47µF 1 10Ω R7 0.002Ω 2 R5 0.002Ω 10Ω 2 1 10Ω 4 3 10Ω C16 0.47µF C8 0.47µF GND 12VIN + COUT1 R8 50Ω R9 50Ω COREFB_L COREFB_H GND VDD_CORE+ CIN1: SIX 10µF 16V CERAMIC CAPACITORS COUT1: TEN 22µF 6.3V CERAMIC CAPACITORS L1, L2: SUMIDA CEP125-1R0MC-H CIN1 Figure 13. 2-Phase 12V Input, 0.8V to 1.55V/45A Max Power Supply for AMD Hammer CPUs with Active Voltage Positioning (AVP) INTVCC R24 107k 9 C10 220pF 7 6 5 4 3 2 1 8 C14 470pF CLK1 C3 1nF R6 2.2k C9 4.7nF R23 48.7k D1 BAT54 RUN/SS LTC3719 TYPICAL APPLICATIO 3719i U LTC3719 U PACKAGE DESCRIPTIO G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.67 – 12.93* (.499 – .509) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 7.65 – 7.90 (.301 – .311) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 5.20 – 5.38** (.205 – .212) 1.73 – 1.99 (.068 – .078) 0° – 8° .13 – .22 (.005 – .009) .55 – .95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) .65 (.0256) BSC .25 – .38 (.010 – .015) .05 – .21 (.002 – .008) G36 SSOP 0501 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 3719i 31 LTC3719 RELATED PARTS PART NUMBER LTC1436A-PLL LTC1438/LTC1439 LTC1438-ADJ LTC1538-AUX LTC1539 LTC1628/LTC1628-PG LTC1629/LTC1629-PG LTC1702/LTC1703 LTC1708-PG DESCRIPTION High Efficiency Low Noise Synchronous Step-Down Switching Regulator Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulators Dual Synchronous Controller with Auxiliary Regulator Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator PolyPhase High Efficiency Controller Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator with 5-Bit VID and Power Good Indication LTC1709-7 2-Phase High Efficiency Controller with 5-Bit Mobile VID and Power Good Indication (0.9V ≤ VOUT ≤ 2V) LTC1709-8/LTC1709-9 2-Phase High Efficiency Controller with 5-Bit VID and Power Good Indication LTC1735 High Efficiency Synchronous Step-Down Controller LTC1736 High Efficiency Synchronous Step-Down Controller with 5-Bit VID LT1769 2A Monolithic Battery Charger LTC1778 No RSENSETM Synchronous Current Mode Step-Down Controller LTC1929/LTC1929-PG 2-Phase High Efficiency Controller LTC1960 Dual Battery Charger/Selector with SPI Interface LTC3716 2-Phase High Efficiency Controller with 5-Bit VID and Power Good Indication LTC3717/LTC3831 DDR Memory Termination Regulators (VTT Supply) Adaptive Power and No RSENSE are a trademarks of Linear Technology Corporation. COMMENTS Adaptive PowerTM Mode, 24-Pin SSOP POR, Auxiliary Regulator POR, External Feedback Divider Auxiliary Regulator, 5V Standby 5V Standby, POR, Low Battery, Aux Regulator Constant Frequency, Standby, 5V and 3.3V LDOs Expandable Up to 12 Phases, G-28, Up to 120A 500kHz, 25MHz GBW, Error Amplifer 1.3V ≤ VOUT ≤ 3.5V, Current Mode Ensures Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V Burst Mode Operation and Cycle Skip Low Current Modes, 3.5V ≤ VIN ≤ 36V VID Tables VRM 8.4 and VRM9.0, IOUT ≤ 40A Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection, 3.5V ≤ VIN ≤ 36V Output Fault Protection, Power Good, GN-24, 3.5V ≤ VIN ≤ 36V, 0.925V ≤ VOUT ≤ 2V CC/CV Switching DC/DC Converter, 5% Charge Accuracy, Adapter Current Limit for Maximum Charge Current No Sense Resistor Required, 4V ≤ VIN ≤ 36V, 0.8V ≤ VIN ≤ VIN, GN16 Adjustable Output Up to 40A, G-28 Extends Run Time by 10%, Reduces Charging Time by 50%, 36-Lead SSOP 0.6V ≤ VOUT ≤ 1.75V, IOUT ≤ 40A Precision Regulation, Up to 20A, Small PCB Area 3719i 32 Linear Technology Corporation LT/TP 1201 1.5K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001