LTC3778 Wide Operating Range, No RSENSETM Step-Down Controller U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®3778 is a synchronous step-down switching regulator controller for computer memory, automobile and other DC/DC power supplies. The controller uses a valley current control architecture to deliver very low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. Wide VIN Range: 4V to 36V Sense Resistor Optional True Current Mode Control 2% to 90% Duty Cycle at 200kHz tON(MIN) ≤ 100ns Stable with Ceramic COUT Dual N-Channel MOSFET Synchronous Drive Power Good Output Voltage Monitor ±1% 0.6V Reference Adjustable Current Limit Adjustable Switching Frequency Programmable Soft-Start Output Overvoltage Protection Optional Short-Circuit Shutdown Timer Micropower Shutdown: IQ ≤ 30µA Available in a 1mm 20-Lead TSSOP Package Discontinuous mode operation provides high efficiency operation at light loads. A forced continuous control pin reduces noise and RF interference, and can assist secondary winding regulation when the main output is lightly loaded. SENSE+ and SENSE– pins provide true Kelvin sensing across the optional sense resistor or the sychronous MOSFET. Fault protection is provided by internal foldback current limiting, an output overvoltage comparator, optional shortcircuit shutdown timer and input undervoltage lockout. Soft-start capability for supply sequencing is accomplished using an external timing capacitor. The regulator current limit level is user programmable. Wide supply range allows operation from 4V to 36V at the input and from 0.6V up to (0.9)VIN at the output. U APPLICATIO S ■ ■ ■ ■ Notebook and Palmtop Computers, PDAs Battery Chargers Distributed Power Systems DDR Memory Power Supply Automobile DC Power Supply , LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. U ■ TYPICAL APPLICATIO RON 1.4M Efficiency vs Load Current ION RUN/SS M1 Si4884 TG CC 500pF SW ITH RC 20k VIN 5V TO 28V VIN CB 0.22µF BOOST INTVCC DRVCC BG SENSE + SENSE – PGOOD + DB CMDSH-3 LTC3778 SGND L1 1.8µH M2 Si4874 + CVCC 4.7µF CIN 10µF 35V VOUT ×3 2.5V COUT 10A 180µF 4V ×2 D1 B340A VIN = 5V 90 VIN = 25V 80 70 R2 40.2k PGND VFB 100 EFFICIENCY (%) CSS 0.1µF 60 0.01 R1 12.7k 1 0.1 LOAD CURRENT (A) 10 3778 F01b 3778 F01a Figure 1. High Efficiency Step-Down Converter 3778f 1 LTC3778 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN, ION)..................36V to – 0.3V Boosted Topside Driver Supply Voltage (BOOST) ................................................... 42V to – 0.3V SENSE+, SW Voltage.................................... 36V to – 5V DRVCC, EXTVCC, (BOOST – SW), FCB, RUN/SS, PGOOD Voltages .................... 7V to – 0.3V VON, VRNG Voltages ................... INTVCC + 0.3V to – 0.3V ITH, VFB Voltages...................................... 2.7V to – 0.3V TG, BG, INTVCC Peak Currents .................................. 2A TG, BG, INTVCC RMS Currents ............................ 50mA Operating Ambient Temperature Range (Note 4) ................................... – 40°C to 85°C Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RUN/SS 1 20 BOOST VON 2 19 TG PGOOD 3 18 SW VRNG 4 17 SENSE + ITH 5 16 SENSE – FCB 6 SGND 7 15 PGND 14 BG ION 8 13 DRVCC VFB 9 12 INTVCC EXTVCC 10 LTC3778EF 11 V IN F PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125°C, θJA = 110°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 900 15 2000 30 µA µA 0.600 0.606 V Main Control Loop IQ Input DC Supply Current Normal Shutdown Supply Current VFB Feedback Reference Voltage ITH = 1.2V (Note 3) ∆VFB(LINEREG) Feedback Voltage Line Regulation VIN = 4V to 30V, ITH = 1.2V (Note 3) 0.002 ∆VFB(LOADREG) Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 3) – 0.05 – 0.3 % IFB Feedback Pin Input Current –5 ±100 nA gm(EA) Error Amplifier Transconductance mS VFCB Forced Continuous Threshold IFCB Forced Continuous Pin Current VFCB = 0.6V tON On-Time ION = 60µA, VON = 1.5V ION = 60µA, VON = 0V tON(MIN) Minimum On-Time ION = 180µA, VON = 0V tOFF(MIN) Minimum Off-Time ION = 60µA, VON = 1.5V VSENSE(MAX) Maximum Current Sense Threshold VSENSE– – VSENSE+ VRNG = 1V, VFB = 0.56V VRNG = 0V, VFB = 0.56V VRNG = INTVCC, VFB = 0.56V VSENSE(MIN) Minimum Current Sense Threshold VSENSE+ – VSENSE– VRNG = 1V, VFB = 0.64V VRNG = 0V, VFB = 0.64V VRNG = INTVCC, VFB = 0.64V ∆VFB(OV) Output Overvoltage Fault Threshold 7.5 10 12.5 % ∆VFB(UV) Output Undervoltage Fault Threshold 340 400 460 mV ITH = 1.2V (Note 3) ● 0.594 %/V ● 1.4 1.7 2 ● 0.57 0.6 0.63 V –1 –2 µA 250 110 300 ns ns 50 100 ns 200 ● ● ● 113 79 158 250 400 ns 133 93 186 153 107 214 mV mV mV 67 47 93 mV mV mV 3778f 2 LTC3778 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX VRUN/SS(ON) RUN Pin Start Threshold 0.8 1.5 2 V VRUN/SS(LE) RUN Pin Latchoff Enable Threshold VRUN/SS(LT) RUN Pin Latchoff Threshold RUN/SS Pin Rising 4 4.5 V RUN/SS Pin Falling 3.5 4.2 V IRUN/SS(C) Soft-Start Charge Current – 1.2 –3 µA IRUN/SS(D) Soft-Start Discharge Current VIN(UVLO) Undervoltage Lockout Threshold VIN Falling ● 1.8 3 µA 3.4 3.9 V VIN(UVLOR) Undervoltage Lockout Threshold VIN Rising ● 3.5 4 V TG RUP TG Driver Pull-Up On Resistance TG High TG RDOWN TG Driver Pull-Down On Resistance TG Low 2 3 Ω 2 3 Ω BG RUP BG Driver Pull-Up On Resistance BG High 3 4 Ω BG RDOWN BG Driver Pull-Down On Resistance TG tr TG Rise Time BG Low 1 2 CLOAD = 3300pF 20 ns TG tf TG Fall Time CLOAD = 3300pF 20 ns BG tr BG Rise Time CLOAD = 3300pF 20 ns BG tf BG Fall Time CLOAD = 3300pF 20 ns ● – 0.5 0.8 UNITS Ω Internal VCC Regulator VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V ∆VLDO(LOADREG) Internal VCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 4V VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, VEXTVCC Rising ∆VEXTVCC EXTVCC Switch Drop Voltage ICC = 20mA, VEXTVCC = 5V ∆VEXTVCC(HYS) EXTVCC Switchover Hysteresis ● ● 4.7 4.5 5 5.3 V – 0.1 ±2 % 4.7 150 V 300 200 mV mV PGOOD Output ∆VFBH PGOOD Upper Threshold VFB Rising 7.5 10 12.5 % ∆VFBL PGOOD Lower Threshold VFB Falling – 7.5 – 10 – 12.5 % ∆VFB(HYS) PGOOD Hysteresis VFB Returning 1 2.5 % VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3778E: TJ = TA + (PD • 110°C/W) Note 3: The LTC3778 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 4: The LTC3778E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. 3778f 3 LTC3778 U W TYPICAL PERFOR A CE CHARACTERISTICS Transient Response (Discontinuous Mode) Transient Response Start-Up RUN/SS 2V/DIV VOUT 50mV/DIV VOUT 50mV/DIV VOUT 1V/DIV IL 5A/DIV IL 5A/DIV 20µs/DIV LOAD STEP 0A TO 10A VIN = 15V VOUT = 2.5V FCB = 0V FIGURE 1 CIRCUIT 20µs/DIV LOAD STEP 1A TO 10A VIN = 15V VOUT = 2.5V FCB = INTVCC FIGURE 1 CIRCUIT 3778 G01 Efficiency vs Load Current 100 DISCONTINUOUS MODE CONTINUOUS MODE 70 0.1 0.01 1 LOAD CURRENT (A) ILOAD = 1A 90 ILOAD = 10A 80 0 10 2.5 FIGURE 1 CIRCUIT 5 10 15 20 INPUT VOLTAGE (V) 25 ∆VOUT (%) ITH VOLTAGE (V) 8 10 3778 G06 15 20 3778 G05 300 CONTINUOUS MODE 1.0 0 DISCONTINUOUS MODE 10 5 LOAD CURRENT (A) 15 3778 G07 VRNG = 200 2V 1.4V 1V 0.7V 0.5V 100 0 –100 –200 0 25 Current Sense Threshold vs ITH Voltage 1.5 0.5 6 4 LOAD CURRENT (A) 10 5 INPUT VOLTAGE (V) FIGURE 1 CIRCUIT VRNG = 1V –0.3 2 200 30 2.0 0 IOUT = 0A 240 ITH Voltage vs Load Current –0.1 –0.4 260 3778 G04 Load Regulation –0.2 IOUT = 10A 220 3778 G03 0 FCB = 0V FIGURE 1 CIRCUIT 280 CURRENT SENSE THRESHOLD (mV) 50 0.001 300 FCB = 5V FIGURE 1 CIRCUIT 85 VIN = 10V VOUT = 2.5V EXTVCC = 5V FIGURE 1 CIRCUIT 60 Frequency vs Input Voltage FREQUENCY (kHz) 80 3778 G19 VIN = 15V VOUT = 2.5V RLOAD = 0.125Ω 95 EFFICIENCY (%) 90 50ms/DIV 3778 G02 Efficiency vs Input Voltage 100 EFFICIENCY (%) IL 5A/DIV 0 0.5 1.0 1.5 2.0 ITH VOLTAGE (V) 2.5 3.0 3778 G08 3778f 4 LTC3778 U W TYPICAL PERFOR A CE CHARACTERISTICS On-Time vs ION Current On-Time vs VON Voltage 10k VVON = 0V 1000 On-Time vs Temperature 300 IION = 30µA 250 ON-TIME (ns) ON-TIME (ns) ON-TIME (ns) 800 1k 600 400 100 0 10 10 ION CURRENT (µA) 1 100 2 1 VON VOLTAGE (V) 0 100 75 50 25 0 0.15 0.30 VFB (V) 0.45 300 250 200 150 100 50 0 0.60 0.5 0.75 1.0 1.25 1.5 VRNG VOLTAGE (V) 1.75 120 110 50 25 0 75 TEMPERATURE (°C) 75 50 25 0 1.5 100 125 3778 G11 2 2.5 3 RUN/SS VOLTAGE (V) 3.5 3778 G23 Error Amplifier gm vs Temperature 2.0 1.8 0.61 gm (mS) FEEDBACK REFERENCE VOLTAGE (V) 130 VRNG = 1V 100 2.0 0.62 140 125 125 Feedback Reference Voltage vs Temperature VRNG = 1V 100 –50 –25 150 3778 G10 3778 G09 Maximum Current Sense Threshold vs Temperature 100 Maximum Current Sense Threshold vs RUN/SS Voltage MAXIMUM CURRENT SENSE THRESHOLD (mV) MAXIMUM CURRENT SENSE THRESHOLD (mV) MAXIMUM CURRENT SENSE THRESHOLD (mV) 125 50 25 75 0 TEMPERATURE (°C) 3778 G22 Maximum Current Sense Threshold vs VRNG Voltage VRNG = 1V 0 0 –50 –25 3 3778 G21 Current Limit Foldback MAXIMUM CURRENT SENSE THRESHOLD (mV) 150 50 3778 G20 150 200 100 200 150 IION = 30µA VON = 0V 0.60 1.6 1.4 0.59 1.2 0.58 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 3778 G12 1.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3778 G13 3778f 5 LTC3778 U W TYPICAL PERFOR A CE CHARACTERISTICS Input and Shutdown Currents vs Input Voltage 60 EXTVCC OPEN 600 30 400 20 200 –0.1 ∆INTVCC (%) 40 SHUTDOWN SHUTDOWN CURRENT (µA) INPUT CURRENT (µA) 50 800 10 0 EXTVCC SWITCH RESISTANCE (Ω) 1200 1000 EXTVCC Switch Resistance vs Temperature INTVCC Load Regulation –0.2 –0.3 10 –0.4 0 –0.5 8 6 4 2 EXTVCC = 5V 0 0 5 20 15 25 10 INPUT VOLTAGE (V) 30 35 10 30 40 20 INTVCC LOAD CURRENT (mA) 0 3778 G24 –0.25 2 RUN/SS PIN CURRENT (µA) FCB PIN CURRENT (µA) 3 –0.50 –0.75 –1.00 –1.25 100 PULL-DOWN CURRENT 0 PULL-UP CURRENT –1 –2 –50 125 –25 50 25 0 75 TEMPERATURE (°C) 125 3778 G16 UNDERVOLTAGE LOCKOUT THRESHOLD (V) RUN/SS THRESHOLD (V) 100 Undervoltage Lockout Threshold vs Temperature 5.0 4.5 LATCHOFF ENABLE 4.0 3.5 LATCHOFF THRESHOLD 75 0 25 50 TEMPERATURE (°C) 125 1 RUN/SS Latchoff Thresholds vs Temperature –25 100 3778 G14 3778 G15 3.0 –50 50 25 0 75 TEMPERATURE (°C) RUN/SS Pin Current vs Temperature 0 50 25 75 0 TEMPERATURE (°C) 0 –50 –25 3778 G25 FCB Pin Current vs Temperature –1.50 –50 –25 50 100 125 3778 G17 4.0 3.5 3.0 2.5 2.0 –50 –25 75 0 25 50 TEMPERATURE (C) 100 125 3778 G18 3778f 6 LTC3778 U U U PI FU CTIO S RUN/SS (Pin 1): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/µF) and the time delay for overcurrent latchoff (see Applications Information). Forcing this pin below 0.8V shuts down the device. VON (Pin 2): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT. The comparator input defaults to 0.7V when the pin is grounded, 2.4V when the pin is tied to INTVCC. PGOOD (Pin 3): Power Good Output. Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. VRNG (Pin 4): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The nominal sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to INTVCC. ITH (Pin 5): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). FCB (Pin 6): Forced Continuous Input. Tie this pin to ground to force continuous synchronous operation at low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. and shuts down the internal regulator so that controller power is drawn from EXTVCC. Do not exceed 7V at this pin and ensure that EXTVCC < VIN. VIN (Pin 11): Main Input Supply. Decouple this pin to SGND with an RC filter (1Ω, 0.1µF). INTVCC (Pin 12): Internal 5V Regulator Output. The internal control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 1µF low ESR tantalum or ceramic capacitor. DRVCC (Pin 13): Voltage Supply to Bottom Gate Driver. Normally connected to the INTVCC pin through a decoupling RC filter (1Ω, 0.1µF). Decouple this pin to power ground with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. Do not exceed 7V at this pin. BG (Pin 14): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and DRVCC. PGND (Pin 15): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET or to the bottom of the sense resistor when used, the (–) terminal of CVCC and the (–) terminal of CIN. SENSE – (Pin 16): Current Sense Comparator Input. The (–) input to the current comparator is used to accurately Kelvin sense the bottom side of the sense resistor or MOSFET. SENSE + (Pin 17): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (See Applications Information). SGND (Pin 7): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. SW (Pin 18): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below ground up to VIN. ION (Pin 8): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. TG (Pin 19): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to DRVCC superimposed on the switch node voltage SW. VFB (Pin 9): Error Amplifier Feedback Input. This pin connects the error amplifier input to an external resistive divider from VOUT. BOOST (Pin 20): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below DRVCC up to VIN + DRVCC. EXTVCC (Pin 10): External VCC Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to INTVCC 3778f 7 LTC3778 W FU CTIO AL DIAGRA U U RON VOUT VIN 2 VON 2.4V 0.7V 8 ION 6 FCB 11 VIN 10 EXTVCC + 4.7V CIN + 1µA – 0.6V REF 0.6V 5V REG 12 F tON = BOOST 20 VVON (10pF) IION R S Q TG 19 FCNT SENSE+ 17 SWITCH LOGIC IREV SHDN 1.4V 4 VOUT + COUT 13 BG 14 OV VRNG L1 DB SENSE – 16 DRVCC – – M1 18 + ICMP CB SW ON 20k + INTVCC + – × (0.5~2) M2 CVCC RSENSE (OPTIONAL)* PGND 0.7V 15 3 3.3µA PGOOD 1 240k + 1V Q2 Q4 0.54V UV Q6 ITHB R2 – VFB 9 Q3 Q1 R1 + Q5 SGND 7 OV + – 0.8V – ×5.3 SS + RUN SHDN/ LATCH-OFF + – RC SENSE+ BG 6V – + 0.6V 5 ITH 0.66V SW 1.2µA EA 0.6V – CC1 0.4V 1 RUN/SS CSS M2 SENSE– PGND *CONNECTION W/O SENSE RESISTOR 1778 FD 3778f 8 LTC3778 U OPERATIO Main Control Loop The LTC3778 is a current mode controller for DC/DC step-down converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the SENSE– and SENSE+ pins. The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this voltage by comparing the feedback signal VFB from the output voltage with an internal 0.6V reference. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. At low load currents, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV which then shuts off M2, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Discontinuous mode operation is disabled by comparator F when the FCB pin is brought below 0.6V, forcing continuous synchronous operation. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN and VOUT. The nominal frequency can be adjusted with an external resistor RON. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on and held on until the overvoltage condition clears. Foldback current limiting is provided if the output is shorted to ground. As VFB drops, the buffered current threshold voltage ITHB is pulled down by clamp Q3 to a 1V level set by Q4 and Q6. This reduces the inductor valley current level to one sixth of its maximum value as VFB approaches 0V. Pulling the RUN/SS pin low forces the controller into its shutdown state, turning off both M1 and M2. Releasing the pin allows an internal 1.2µA current source to charge up an external soft-start capacitor CSS. When this voltage reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately 0.6V below the RUN/SS voltage. As CSS continues to charge, the soft-start current limit is removed. EXTVCC/INTVCC/DRVCC Power Power for the top and bottom MOSFET drivers is derived from DRVCC and most of the internal controller circuitry is powered from the INTVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is recharged from DRVCC through an external Schottky diode DB when the top MOSFET is turned off. When the EXTVCC pin is grounded, an internal 5V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC rises above 4.7V, the internal regulator is turned off, and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source connected to EXTVCC, such as an external 5V supply or a secondary output from the converter, to provide the INTVCC power. Voltages up to 7V can be applied to DRVCC for additional gate drive. If the input voltage is low and INTVCC drops below 3.5V, undervoltage lockout circuitry prevents the power switches from turning on. 3778f 9 LTC3778 U W U U APPLICATIO S I FOR ATIO The basic LTC3778 application circuit is shown in Figure 1. External component selection is primarily determined by the maximum load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC3778 can use either a sense resistor or the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across a sense resistance that appears between the SENSE – and SENSE + pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately (0.133)VRNG. The current mode control loop will not allow the inductor current valleys to exceed (0.133)VRNG/RSENSE. In practice, one should allow some margin for variations in the LTC3778 and external component values and a good guide for selecting the sense resistance is: RSENSE = VRNG 10 • IOUT (MAX) An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.33 times this nominal value. Connecting the SENSE + and SENSE – Pins The LTC3778 can be used with or without a sense resistor. When using a sense resistor, it is placed between the source of the bottom MOSFET, M2, and PGND. Connect the SENSE + and SENSE – pins to the top and bottom of the sense resistor. Using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the bottom MOSFET as the current sense element by simply connecting the SENSE + pin to the SW pin and SENSE – pin to PGND. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed below. Power MOSFET Selection The LTC3778 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V INTVCC and DRVCC supplies. Consequently, logic-level threshold MOSFETs must be used in LTC3778 applications. If the input voltage or DRVCC voltage is expected to drop below 5V, then sublogic level threshold MOSFETs should be considered. When the bottom MOSFET is used as the current sense element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25°C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON)(MAX) = RSENSE ρT 3778f 10 LTC3778 U W U U APPLICATIO S I FOR ATIO The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/°C as shown in Figure 2. For a maximum junction temperature of 100°C, using a value ρT = 1.3 is reasonable. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. ρT NORMALIZED ON-RESISTANCE 2.0 The operating frequency of LTC3778 applications is determined implicitly by the one-shot timer that controls the on-time tON of the top MOSFET switch. The on-time is set by the current into the ION pin and the voltage at the VON pin according to: 1.5 1.0 0.5 tON = 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3778 F02 Figure 2. RDS(ON) vs. Temperature The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC3778 is operating in continuous mode, the duty cycles for the MOSFETs are: VOUT VIN V –V = IN OUT VIN D TOP = DBOT VVON (10pF ) IION The resulting power dissipation in the MOSFETs at maximum output current are: PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX) + k VIN2 IOUT(MAX) CRSS f PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX) Both MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are largest at high input voltages. The constant k = 1.7A–1 can be used to estimate the amount of transition loss. The bottom MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: f= VOUT [Hz] (VVON ) RON (10pF ) To hold frequency constant during output voltage changes, tie the VON pin to VOUT. The VON pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.7V, the input to the one-shot is clamped at 0.7V. Similarly, if the pin is tied above 2.4V, the input is clamped at 2.4V. If output is above 2.4V, use a resistive divider from VOUT to VON pin. Because the voltage at the ION pin is about 0.7V, the current into this pin is not exactly inversely proportional to VIN, especially in applications with lower input voltages. To correct for this error, an additional resistor RON2 connected from the ION pin to the 5V INTVCC supply will further stabilize the frequency. RON2 = 5V RON 0.7V Changes in the load current magnitude will also cause frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the 3778f 11 LTC3778 U W U U APPLICATIO S I FOR ATIO load current increases. By lengthening the on-time slightly as current increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from the ITH pin to the VON pin and VOUT. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about 25% of the voltage change at the ITH pin to the VON pin as shown in Figure 3a. Place capacitance on the VON pin to filter out the ITH variations at the switching frequency. The resistor load on ITH reduces the DC gain of the error amp and degrades load regulation, which can be avoided by using the PNP emitter follower of Figure 3b. RVON1 30k VON VOUT CVON 0.01µF RVON2 100k LTC3778 RC ITH CC 3778 F03a (3a) RVON1 3k VOUT 10k CVON 0.01µF RVON2 10k INTVCC VON LTC3778 RC Q1 2N5087 ITH CC 3778 F03b (3b) Figure 3. Correcting Frequency Shift with Load Current Changes Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V V ∆IL = OUT 1 − OUT VIN f L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: VOUT VOUT L= 1 − f ∆IL(MAX) VIN(MAX) Once the value for L is known, the type of inductor must be selected. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko. Schottky Diode D1 Selection The Schottky diode D1 shown in Figure 1 conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. CIN and COUT Selection The input capacitance CIN is required to filter the square wave current at the drain of the top MOSFET. Use a low ESR capacitor sized to handle the maximum RMS current. IRMS ≅ IOUT (MAX) VOUT VIN VIN –1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX) / 2. This simple worst-case condition is 3778f 12 LTC3778 U W U U APPLICATIO S I FOR ATIO commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ∆VOUT is approximately bounded by: 1 ∆VOUT ≤ ∆IL ESR + 8fC OUT Since ∆IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, POSCAP aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. When necessary, adding a small 5µF to 50µF aluminum electrolytic capacitor with an ESR in the range of 0.5Ω to 2Ω dampens input voltage transients. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from DRVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + DRVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications a 0.1µF to 0.47µF, X5R or X7R dielectric ceramic capacitor is adequate. Discontinuous Mode Operation and FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which inductor current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and will vary with changes in VIN. Tying the FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. In addition to providing a logic input to force continuous operation, the FCB pin provides a means to maintain a flyback winding output when the primary is operating in discontinuous mode. The secondary output VOUT2 is normally set as shown in Figure 4 by the turns ratio N of the transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then VOUT2 will droop. An external resistor divider from VOUT2 to the FCB pin sets a minimum voltage VOUT2(MIN) below which continuous operation is forced until VOUT2 has risen above its minimum. R4 VOUT 2(MIN) = 0.8V 1 + R3 3778f 13 LTC3778 U W U U APPLICATIO S I FOR ATIO VIN + CIN VIN 1N4148 OPTIONAL EXTVCC CONNECTION 5V < VOUT2 < 7V TG • + LTC3778 EXTVCC SW R4 T1 1:N FCB R3 • + VOUT2 CSEC 1µF VOUT1 COUT BG SGND PGND 3778 F04 Figure 4. Secondary Output Loop and EXTVCC Connection Fault Conditions: Current Limit and Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3778, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX) (RDS(ON) 1 + ∆IL ρT )* 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the lowest VIN at the highest ambient temperature. Note that it is important to check for selfconsistency between the assumed MOSFET junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. *Use RSENSE value here if a sense resistor is connected between SENSE+ and SENSE– . 14 To further limit current in the event of a short circuit to ground, the LTC3778 includes foldback current limiting. If the output falls by more than 50%, then the maximum sense voltage is progressively lowered to about one sixth of its full value. Minimum Off-time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3778 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON INTVCC Regulator An internal P-channel low dropout regulator produces the 5V supply that powers the drivers and internal circuitry within the LTC3778. The INTVCC pin can supply up to 50mA RMS and must be bypassed to ground with a minimum of 4.7µF tantalum or other low ESR capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and high frequency of operation may cause the LTC3778 to exceed its maximum junction temperature rating or RMS current rating. Most of the supply current drives the MOSFET gates unless an external EXTVCC source is used. In continuous mode operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics. For example, the LTC3778EF is limited to less than 15mA from a 30V supply: TJ = 70°C + (15mA)(30V)(110°C/W) = 120°C For larger currents, consider using an external supply with the DRVCC pin. 3778f LTC3778 U W U U APPLICATIO S I FOR ATIO EXTVCC Connection Soft-Start and Latchoff with the RUN/SS Pin The EXTVCC pin can be used to provide MOSFET gate drive and control power from the output or another external source during normal operation. Whenever the EXTVCC pin is above 4.7V the internal 5V regulator is shut off and an internal 50mA P-channel switch connects the EXTVCC pin to INTVCC. INTVCC power is supplied from EXTVCC until this pin drops below 4.5V. Do not apply more than 7V to the EXTVCC pin and ensure that EXTVCC ≤ VIN. The following list summarizes the possible connections for EXTVCC: The RUN/SS pin provides a means to shut down the LTC3778 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 0.8V puts the LTC3778 into a low quiescent current shutdown (IQ < 30µA). Releasing the pin allows an internal 1.2µA current source to charge up the external timing capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about: 1. EXTVCC grounded. INTVCC is always powered from the internal 5V regulator. 2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive requirements (typically 5V) can improve overall efficiency. 3. EXTVCC connected to an output derived boost network. The low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7V. The system will start-up using the internal linear regulator until the boosted output supply is available. External Gate Drive Buffers The LTC3778 drivers are adequate for driving up to about 60nC into MOSFET switches with RMS currents of 50mA. Applications with larger MOSFET switches or operating at frequencies requiring greater RMS currents will benefit from using external gate drive buffers such as the LTC1693. Alternately, the external buffer circuit shown in Figure 5 can be used. Note that the bipolar devices reduce the signal swing at the MOSFET gate, and benefit from an increased EXTVCC voltage of about 6V. DRVCC BOOST 10Ω TG Q1 FMMT619 GATE OF M1 Q2 FMMT720 SW 10Ω BG Q3 FMMT619 GATE OF M2 Q4 FMMT720 PGND Figure 5. Optional External Gate Driver 3778 F05 tDELAY = ( ) 1.5V C SS = 1.3s/µF C SS 1.2µA When the voltage on RUN/SS reaches 1.5V, the LTC3778 begins operating with a clamp on ITH of approximately 0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH is raised until its full 2.4V range is available. This takes an additional 1.3s/µF, during which the load current is folded back until the output reaches 50% of its final value. The pin can be driven from logic as shown in Figure 6. Diode D1 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. After the controller has been started and given adequate time to charge up the output capacitor, CSS is used as a short-circuit timer. After the RUN/SS pin charges above 4V, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. A 1.8µA current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 4V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: CSS > COUT VOUT RSENSE (10 – 4 [F/V s]) Generally 0.1µF is more than sufficient. 3778f 15 LTC3778 U W U U APPLICATIO S I FOR ATIO Overcurrent latchoff operation is not always needed or desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff operation can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current greater than 5µA to the RUN/SS pin. The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period. Using a resistor to V IN as shown in Figure 6a is simple, but slightly increases shutdown current. Connecting a resistor to INTV CC as shown in Figure 6b eliminates the additional shutdown current, but requires a diode to isolate CSS . Any pull-up network must be able to maintain RUN/SS above the 4V maximum latch-off threshold and overcome the 4µA maximum discharge current. INTVCC RSS* VIN 3.3V OR 5V D1 RUN/SS RSS* D2* RUN/SS 2N7002 CSS CSS 3778 F06 *OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF (6a) (6b) Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3778 circuits: DC I2R losses. These arise from the resistances of the 1. sense resistor, MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 15mW to 1.5W as the output current varies from 1A to 10A for a 1.5V output. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f 3. INTVCC current. This is the sum of the MOSFET driver and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high efficiency source, such as an output derived boost network or alternate supply if available. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. 3778f 16 LTC3778 U W U U APPLICATIO S I FOR ATIO During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 7 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Linear Technology Application Note 76. As a design example, take a supply with the following specifications: VIN = 7V to 28V (15V nominal), VOUT = 2.5V ±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate the timing resistor with VON = VOUT: ( 1 )( 250kHz 10pF ) = 400kΩ and choose the inductor for about 40% ripple current at the maximum VIN: L= ( 2.5V 1− = 2.3µH 28V 250kHz 0.4 10A 2.5V )( )( ) Selecting a standard value of 1.8µH results in a maximum ripple current of: ∆IL = ( 2.5V 1– = 5.1A 28V 250kHz 1.8µH 2.5V )( ) Next, choose the synchronous MOSFET switch. Choosing a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX), θJA = 40°C/W) yields a nominal sense voltage of: VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV Tying VRNG to 1.1V will set the current sense voltage range for a nominal value of 110mV with current limit occurring at 146mV. To check if the current limit is acceptable, assume a junction temperature of about 80°C above a 70°C ambient with ρ150°C = 1.5: (1.5)(0.010Ω) ( ) 146mV + 1 5.1A = 12A 2 and double check the assumed TJ in the MOSFET: PBOT = Design Example RON = ILIMIT ≥ ( ) (1.5)(0.010Ω) = 1.97 W 28V – 2 .5V 12A 28V 2 TJ = 70°C + (1.97W)(40°C/W) = 149°C Because the top MOSFET is on for such a short time, an Si4884 RDS(ON)(MAX) = 0.0165Ω, CRSS = 100pF will be sufficient. Checking its power dissipation at current limit with ρ100°C = 1.4: ( ) (1.4)(0.0165Ω) + 2 (1.7)(28V) (12A)(100pF )(250kHz) PTOP = 2.5V 12A 28V 2 = 0.30W + 0.40W = 0.7 W TJ = 70°C + (0.7W)(40°C/W) = 98°C The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. CIN is chosen for an RMS current rating of about 5A at 85°C. The output capacitors are chosen for a low ESR of 0.013Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: ∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (5.1A) (0.013Ω) = 66mV However, a 0A to 10A load step will cause an output change of up to: ∆VOUT(STEP) = ∆ILOAD (ESR) = (10A) (0.013Ω) = 130mV An optional 22µF ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 7. 3778f 17 LTC3778 U W U U APPLICATIO S I FOR ATIO 1 2 R3 11k R4 39k CC1 500pF RPG 100k 3 4 RC 20k 5 6 CC2 100pF CON, 0.01µF R1 12.7k 7 8 9 RON 400k R2 40.2k 10 LTC3778 20 RUN/SS BOOST VON TG PGOOD SW 19 CB 0.22µF 18 VRNG SENSE + 17 ITH SENSE – 16 FCB DB CMDSH-3 M1 Si4884 + PGND SGND BG ION DRVCC VFB INTVCC EXTVCC VIN VIN 5V TO 28V CIN 10µF 35V ×3 VOUT 2.5V 10A L1, 1.8µH 15 M2 Si4874 D1 B340A COUT1-2 180µF 4V ×2 COUT3 22µF 6.3V X7R 14 13 + CSS 0.1µF CVCC 4.7µF 12 11 RF 1Ω CF 0.1µF 3778 F07 CIN: UNITED CHEMICON THCR60EIHI06ZT COUT1-2: CORNELL DUBILIER ESRE181E04B L1: SUMIDA CEP125-1R8MC-H Figure 7. Design Example: 2.5V/10A at 250kHz Active Voltage Positioning Active voltage positioning (also termed load “deregulation” or droop) describes a technique where the output voltage varies with load in a controlled manner. It is useful in applications where rapid load steps are the main cause of error in the output voltage. By positioning the output voltage at or above the regulation point at zero load, and below the regulation point at full load, one can use more of the error budget for the load step. This allows one to reduce the number of output capacitors by relaxing the ESR requirement. For example, in a 20A application, six 0.015Ω capacitors are required in parallel to keep the output voltage within a 100mV tolerance: 1 ±20A 0.015Ω = ±50mV = 100mV 6 ( ) Using active voltage positioning, the same specification can be met with only three capacitors. In this case, the load step will cause an output voltage change of: ∆VOUT (STEP) 18 1 = 20A 0.015Ω = 100mV 3 ( ) ( ) By positioning the output voltage at the regulation point at no load, it will drop 100mV below the regulation point after the load step. However, when the load disappears or the output is stepped from 20A to 0A, the 100mV is recovered. This way, a total of 100mV change is observed on VOUT in all conditions, whereas a total of ±100mV or 200mV is seen on VOUT without voltage positioning while using only three output capacitors. Implementing active voltage positioning requires setting a precise gain between the sensed current and the output voltage. Because of the variability of MOSFET on-resistance, it is prudent to use a sense resistor with active voltage positioning. In order to minimize power lost in this resistor, a low value of 0.002Ω is chosen. The nominal sense voltage will now be: VSNS(NOM) = (0.002Ω)(20A) = 40mV To maintain a reasonable current limit, the voltage on the VRNG pin is reduced to 0.5V by connecting it to a resistor divider from INTVCC, corresponding to a 50mV nominal sense voltage. Next, the gain of the LTC3778 error amplifier must be determined. The change in ITH voltage for a corresponding change in the output current is: 3778f LTC3778 U W U U APPLICATIO S I FOR ATIO 12V ∆ITH = RSENSE ∆IOUT VRNG ( )( )( ) = 24 0.002Ω 20A = 0.96V The corresponding change in the output voltage is determined by the gain of the error amplifier and feedback divider. The LTC3778 error amplifier has a transconductance gm that is constant over both temperature and a wide ± 40mV input range. Thus, by connecting a load resistance RVP to the ITH pin, the error amplifier gain can be precisely set for accurate voltage positioning. 0.6V ∆ITH = gm RVP ∆VOUT VOUT these resistors must equal RVP and their ratio determines nominal value of the ITH pin voltage when the error amplifier input is zero. To set the beginning of the load line at the regulation point, the ITH pin voltage must be set to correspond to zero output current. The relation between voltage and the output current is: 12V 1 ITH(NOM) = RSENSE IOUT – ∆IL + 0.75V 2 VRNG 12V 1 = 0.002Ω 0A – 5.8A + 0.75V 2 0.5V = 0.61V ( Solving for the required values of the resistors: Solving for this resistance value: RVP1 = RVP = = ) VOUT ∆ITH (0.6V)gm ∆VOUT 5V 5V 15.7k RVP = 5V – ITH(NOM) 5V – 0.61V = 18k 5V 5V 15.7k = 129k RVP2 = RVP = 0.61V ITH(NOM) (1.25V)(0.96V) = 15.7k (0.6V)(1.7mS)(75mV) The gain setting resistance RVP is implemented with two resistors, RVP1 connected from ITH to ground and RVP2 connected from ITH to INTVCC. The parallel combination of The active voltage positioned circuit is shown in Figure 8. Refer to Linear Technology Design Solutions 10 for additional information about output voltage positioning. CSS 0.1µF 1 RUN/SS LTC3778 2 RRNG1 RRNG2 4.99k 45.3k CC1 2.2nF RPG 100k VON TG PGOOD SW 3 4 RC 20k RVP2 129k RVP1 18k BOOST 19 18 VRNG SENSE + 17 ITH SENSE – 16 5 CC1 100pF 6 20 FCB PGND 7 SGND BG 9 11.7k RON 330k CFB 100pF ION DRVCC VFB INTVCC 12.7k 10 EXTVCC 5V VIN CB 0.33µF VIN CIN 7V TO 24V 22µF 50V ×3 VOUT 1.25V 20A M1 L1 IRF7811 0.68µH ×2 M2 IRF7811 ×3 D1 UPS840 COUT 270µF 2V ×3 RSENSE 0.002Ω 15 14 CION 0.01µF 8 DB CMDSH-3 13 CVCC 4.7µF 12 11 RF 1Ω CF 0.1µF CIN: UNITED CHEMICON THCR70EIH226ZT COUT: PANASONIC EEFUE0D271 L1: SUMIDA CEP125-4712-T007 3778 F08 Figure 8. CPU Core Voltage Regulator with Active Voltage Positioning 1.25V/20A at 300kHz 3778f 19 LTC3778 U W U U APPLICATIO S I FOR ATIO • Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3778. Use several bigger vias for power components. PC Board Layout Checklist When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. • Use compact plane for switch node (SW) to improve cooling of the MOSFETs and to keep EMI down. • Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. • The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). • Place CIN, COUT, MOSFETs, D1 and inductor all in one compact area. It may help to have some components on the bottom side of the board. When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 9. • Place LTC3778 chip with pins 11 to 20 facing the power components. Keep the components connected to pins 1 to 9 close to LTC3778 (noise sensitive components). CSS 2 3 4 CC1 CB LTC3778 1 RC CC2 5 6 7 RUN/SS BOOST VON TG PGOOD SW VRNG SENSE+ ITH SENSE– FCB SGND PGND BG L 20 19 DB 18 + M1 17 16 D1 15 CIN VIN 14 M2 CION 9 R1 10 ION DRVCC VFB INTVCC EXTVCC VIN 13 12 CVCC – + 8 CFB 11 – VOUT COUT CF + RF R2 RON BOLD LINES INDICATE HIGH CURRENT PATHS 3778 F10 Figure 9. LTC3778 Layout Diagram 3778f 20 LTC3778 U W U U APPLICATIO S I FOR ATIO • Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. • Keep the high dV/dT SW, BOOST and TG nodes away from sensitive small-signal nodes. • Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short. • Connect the top driver boost capacitor CB closely to the BOOST and SW pins. • Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. • Connect the VIN pin decoupling capacitor CF closely to the VIN and PGND pins. • Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and PGND pins. U TYPICAL APPLICATIO S Figure 10 shows a DDR memory termination application in which the output can sink and source up to 6A of current. The resistive divider of R1 and R2 are meant to introduce 1 2 RPG 100k 3 4 CC1 1500pF RC 20k CC2 100pF R1 12.7k 6 R2 11.7k 8 9 RON 227k TG 10 SW PGOOD VRNG SENSE + ITH SENSE – 5 7 CON, 0.01µF LTC3778 20 RUN/SS BOOST VON PGND FCB BG SGND ION DRVCC VFB INTVCC EXTVCC VIN 19 VIN 5V TO 25V DB CMDSH-3 CB 0.22µF 18 CIN 10µF 35V ×3 M1 IRF7811 17 15 + R1 1.2k 16 R2 68Ω M2 IRF7811 330µF 25V, SANYO ELECTROLYTIC VOUT 1.25V ±6A L1, 1.8µH D1 B340A COUT1-2 180µF 4V ×2 COUT3 22µF 6.3V X7R 14 13 + CSS 0.1µF an offset to the SENSE – pin so that the current limit is symmetrical during both sink and source. CVCC 4.7µF 12 11 RF 1Ω CF 0.1µF 3778 F11 CIN: UNITED CHEMICON THCR60EIHI06ZT COUT1-2: CORNELL DUBILIER ESRE181E04B L1: SUMIDA CEP125-1R8MC-H Figure 10. 1.25V/±6A Sink and Source at 550kHz 3778f 21 LTC3778 U TYPICAL APPLICATIO S Intel Compatible Tualatin Mobile CPU Power Supply with AVP 1 3.3V VRON 3 3 2 1 R2 100k Q2 2N7002 2 R1 100k Q1 2N7002 2 R3 OPT 1 VIN INTVCC C1, 0.01µF SGND C2, 0.01µF R4 2k R5 100Ω 1 R6 1k R8 1k 2 VOUT PGND LTC3778E RUN/SS BOOST VON TG PGOOD SW 20 R16 0 + 2 1 QT IRF7811A ×2 D1 CMDSH-3 C10 0.22µF 19 L1 0.68µH SUMIDA CEP125-4712F011 PWRGOOD 3 1 Q3 MMMT3906-7 3 2 1 Q6 MMBT3904-7 R14 2 10k 3 R10 3.2k C7 1µF 6.3V 0603 VIN 7.5V CIN TO 24V 10µF 35V ×4 18 1 4 R13 10k 5 VRNG SENSE + 17 ITH SENSE – 16 D2 UPS840 QB IRF7811A ×3 C8, 0.1µF 6 R15 20k C9, 220pF 7 FCB PGND SGND BG COUT 270µF 3 2V, SP ×4 2 15 VCORE 1.35V/1.15V/0.85V 23A + R21 0.003Ω 14 C11, 220pF 8 R17 24.9k, 1% 9 R18 221k, 1% 10 ION DRVCC VFB INTVCC EXTVCC VIN 13 R23 1Ω 12 11 VIN R41 0 5V R19 330k R9 221k 1% VIN C18, 1000pF R29 12.1k 1 DPSLP# 2 R33 100k 3 1 R37 100k R28 100k 1 2 R38 1M DPRSLPVR GMUXSEL 3 1 Q15 2N7002 2 Q12 2N7002 1 3 1 R39 1M R49* 178k 1% R31 10k VCORE 1% R34 33.2k 1% R30 11.8k 1% Q13 2N7002 2 3.3V 3 Q14 2N7002 C19 4.7µF 16V R7 1Ω C41, 1µF C42, 1µF 3.3V C21 1µF R11 9.76k Q17 2N7002 1% 3 2 1 3 Q19* 2N7002 2 1 3 Q20* 2N7002 2 *OPTIONAL 2 3778 F12 3778f 22 LTC3778 U PACKAGE DESCRIPTIO F Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1650) 6.40 – 6.60* (.252 – .260) 20 19 18 17 16 15 14 13 12 11 6.25 – 6.50 (.246 – .256) 1 2 3 4 5 6 7 8 9 10 1.10 (.0433) MAX 4.30 – 4.48** (.169 – .176) 0° – 8° .09 – .18 (.0035 – .0071) .50 – .70 (.020 – .028) .65 (.0256) BSC .18 – .30 (.0071 – .0118) .05 – .15 (.002 – .006) F20 TSSOP 0501 NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 3778f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC3778 U TYPICAL APPLICATIO 12V/5A at 300kHz 2 100k 3 4 5 RC CC1 20k 2.2nF 6 CC2 100pF 7 8 R1 10k R2 190k DB CMDSH-3 LTC3778 1 9 10 RON 1.6M RUN/SS BOOST VON TG PGOOD SW 20 19 VRNG ITH SENSE – PGND SGND BG ION DRVCC VFB INTVCC EXTVCC VIN VIN CIN 14V TO 28V 22µF 50V M1 18 17 SENSE + FCB CB 0.22µF L1 10µH VOUT 12V 5A 16 + M2 15 D1 COUT 220µF 16V 14 13 CVCC 4.7µF 12 + CSS 0.1µF 11 C2 2200pF CF 0.1µF RF 1Ω 3778 TA01 CIN: UNITED CHEMICON THCR70E1H226ZT COUT: SANYO 16SV220M D1: DIODES, INC B340A L1: SUMIDA CDRH127-100 M1, M2: FAIRCHILD FDS6680A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1622 550kHz Step-Down Controller 8-Pin MSOP; Synchronizable; Soft-Start; Current Mode LTC1625/LTC1775 No RSENSETM Current Mode Synchronous Step-Down Controller 97% Efficiency; No Sense Resistor; 16-Pin SSOP LTC1628-PG/ LTC1628-SYNC Dual, 2-Phase Synchronous Step-Down Controller Minimum Input/Output Capacitors; 3.5V ≤ VIN ≤ 36V; Power Good Output; Synchronizable 150kHz to 300kHz LTC1709-7 High Efficiency, 2-Phase Synchronous Step-Down Controller with 5-Bit VID Up to 42A Output; 0.925V ≤ VOUT ≤ 2V LTC1709-8 High Efficiency, 2-Phase Synchronous Step-Down Controller Up to 42A Output; VRM 8.4; 1.3V ≤ VOUT ≤ 3.5V LTC1735 High Efficiency, Synchronous Step-Down Controller Burst ModeTM Operation; 16-Pin Narrow SSOP; 3.5V ≤ VIN ≤ 36V LTC1736 High Efficiency, Synchronous Step-Down Controller with 5-Bit VID Mobile VID; 0.925V ≤ VOUT ≤ 2V; 3.5V ≤ VIN ≤ 36V TM LTC1772 ThinSOT Step-Down Controller Current Mode; 550kHz; Very Small Solution Size LTC1773 Synchronous Step-Down Controller Up to 95% Efficiency, 550kHz, 2.65V ≤ VIN ≤ 8.5V, 0.8V ≤ VOUT ≤ VIN, Synchronizable to 750kHz LTC1778 Wide Operating Range, No RSENSE Step-Down Controller GN16-Pin, 0.8V FB Reference LTC1876 2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator 3.5V ≤ VIN ≤ 36V, Power Good Output, 300kHz Operation LTC3701 Dual, 2-Phase Step-Down Controller Current Mode; 300kHz to 750kHz; Small 16-Pin SSOP, 2.5V ≤ VIN ≤ 9.8V LTC3711 5-Bit Adjustable, No RSENSE Step-Down Controller 0.925V ≤ VOUT ≤ 2V; Mobile VIC Code LTC3713 Very Low VIN, High Current Step-Down Synchronous Controller 1.5V ≤ VIN, IOUT ≤ 20A, Generates its own 5V Gate Drive, Uses Standard N-Channel MOSFETs LTC3714 Intel Compatible, Wide Operating Range, No RSENSE Step-Down Controller with Internal Op Amp G28 Package, VOUT = 0.6V to 1.75V 5-Bit Mobile VID, Active Voltage Positioning IMVP2, VIN to 36V LTC3716 High Efficiency, 2-Phase Synchronous Step-Down Controller with 5-Bit Mobile VID VOUT = 0.6V to 1.75V, Active Voltage Positioning IMVP2, VIN to 36V Burst Mode and ThinSOT are trademarks of Linear Technology Corporation. 24 Linear Technology Corporation 3778f LT/TP 0702 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001