PT4301 Low Power High Sensitivity 315/434MHz OOK/ASK Superheterodyne Receiver DESCRIPTION The PT4301 is a very low power and highly sensitive single chip OOK/ASK super-heterodyne receiver for the 315MHz and 434MHz frequency bands that offers a high level of integration and requires only a few external components. The PT4301 consists of a low-noise amplifier (LNA), an image-rejection mixer, an on-chip phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) and loop filter, a 10.7MHz intermediate frequency (IF) limiting amplifier stage with received-signal-strength indicator (RSSI), and analog baseband data recovery circuitry (data filter, peak detector, and data slicer). The PT4301 also implements a discrete one-step automatic gain control (AGC) that reduces the LNA gain by 20dB when the RF input signal is greater than -47dBm. The PT4301 is available in a 24-pin SSOP package. FEATURES • Low current consumption (5mA fully active mode at 315MHz) • 2.4V to 5.5V supply voltage operation range • Optimized for 315MHz or 434MHz ISM Band • On-chip image-rejection function • High dynamic range with on-chip AGC • Low power down mode current (<1µA) • High sensitivity of -114dBm (315MHz, 2Kb/s AM 99% square-wave modulation) • 24-pin SSOP package APPLICATIONS • Remote keyless entry (RKE) systems • Remote control systems including garage door and gate openers • Alarm and security systems • Wireless sensors BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT4301 APPLICATION CIRCUIT C15 X1 1 XOUT XIN 2 REGIF CE 3 LNAIN PDOUT 22 4 VSSLNA DATA 21 5 LNAOUT VDD5 20 6 REGRF DSP 19 7 MIXIN DFFB 18 8 VSSMIX OPP 17 C1 C4 L3 C2 L1 C14 U1 VDD5 24 23 C13 R4 C3 PWR R5 R1 PT4301 C6 L2 C7 PTC C5 9 MIXOUT DSN 16 10 VSSDIG DFO 15 11 REGDIG LIMINB 14 12 AGCDIS LIMIN 13 C12 C11 REGDIG R2 R7 CE C16 R3 C10 C9 C8 R6 F1 BILL OF MATERIALS Component R1, R4 R2 R3 R5 R6 R7 L1 L2 L3 C1Note1 ,C7, C12 C2 C3 C4 C5 C6 C8 C9 C10 C11 C13 C14, C15 C16 F1Note2 X1 U1 Value 315MHz 10 27K 8.2M 220K 100K 5.6K 68n 47n 39n 100n 10p 1.8p 100p 1.5n 470n 390p 1.2n 27p 100n 10.7 9.509 PT4301 IC Unit 434MHz 10 27K 8.2M 220K 100K 5.6K 39n 27n 27n 100n 10p 1.2p 100p 1.5n 470n 390p 1.2n 27p 100n 10.7 13.226 PT4301 IC Ω Ω Ω Ω Ω Ω H H H F F F F F F F F F F F F F MHz MHz - Description Power supply de-coupling resistors (option) Data filter to data slicer interface resistor Data slicer threshold adjustment (option) Data filter to data slicer interface resistor AGC disable REGDIS discharge resistor (option) LNA input matching, coil inductor LNA output matching Antenna ESD protection, coil inductor (option) Power supply de-coupling resistors LNA input matching LNA input matching (option) LNA input matching LNA output matching (option) LNA to mixer interface capacitor IF amplifier de-coupling capacitor Data slicer threshold charge capacitor Data filter capacitor Data filter capacitor Peak mode charge capacitor (option) Crystal oscillator frequency fine tune capacitors AGC high gain mode quick start capacitor IF filter Reference crystal oscillator Receiver chip Notes: 1. C1 could be separated into three de-coupling capacitors and connect them against the three VDD pins as close as possible. 2. F1 is the 10.7MHz ceramic filter. The recommended part number is Murata SFELA10M7HA00-B0. V1.4 2 October 2010 PT4301 ORDER INFORMATION Valid Part Number PT4301-X Package Type 24 Pins, SSOP, 150mil Top Code PT4301-X PIN CONFIGURATION PIN DESCRIPTION Pin Name XOUT REGIF LNAIN VSSLNA LNAOUT REGRF MIXIN VSSMIX MIXOUT VSSDIG REGDIG AGCDIS LIMIN LIMINB DFO DSN OPP DFFB DSP VDD5 DATA PDOUT CE XIN I/O O P I G O P I G O G P I I I O I I I/O I P O O I I Description Crystal oscillator output Supply voltage for IF portion LNA input Ground for LNA LNA output Supply voltage for RF portion Mixer input Ground for image-rejection mixer Mixer output Ground for LO and digital portions Supply voltage for LO and digital portions AGC control pin. Pull high (connect to VDD5) to disable AGC Limiting amplifier input Limiter amplifier de-coupling input Data filter output Negative data slicer input Non-inverting op-amp input for Sallen-Key data filter Data filter feedback node Positive data slicer input 5V supply voltage Data output Peak detector output Chip enable pin. Pull high (connect to VDD5) to power on the chip Crystal oscillator input Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Note: Pin 13 and Pin 14 are identical pins. Users can choose either pin as the limiting amplifier input and treat the other pin as the de-coupling input. V1.4 3 October 2010 PT4301 FUNCTION DESCRIPTION The PT4301 CMOS superheterodyne receiver achieves both low power consumption and high sensitivity and functions as a complete receive chain from antenna input to digital data output. Depending upon the component selection, data rates as high as 50Kb/s may be achieved at both 315 and 434MHz frequency bands. LOW NOISE AMPLIFIER (LNA) The LNA is an on-chip cascade amplifier with a power gain of 16dB and a noise figure of approximately 3dB. The gain is determined by external matching networks in front of the LNA and between the LNA output and the mixer input. Examples of the input matching network and the input impedance of the PT4301 for 315/434MHz bands are shown in Figure 1. The component values given in the table following the application circuit shown in page 2 are nominal values only. For a particular PCB layout, the user may be required to make component adjustments in order to achieve highest sensitivity. Frequency(MHz) 315 433.92 LNA Input Impedance (Pin 3) Normalized to 50Ω 2.45-j138.4 3.05-j194.85 Figure 1. LNA Input Matching Circuit and Input Impedance of PT4301 The LNA output of PT4301 externally connects to the mixer stage. For the interface between the LNA and mixer, the coupling capacitor should be as close to the PT4301 pins as possible, with the bias inductor being further away. The value of the inductor may be changed to compensate for trace inductance. For obtaining better LNA gain, it is recommended to add a capacitor in parallel with this inductor to implement a resonant tank at the desired frequency as shown in Figure 2. Note that the LNA might self-oscillate and degrade the receiver sensitivity if a large output inductor value is chosen. An alternative matching method is to replace the parallel capacitor with a 330Ω to 1KΩ resistor, which would reduce the resonant tank Q (quality factor) to avoid the self-oscillation. Figure 2. LNA Output Matching Circuit The LNA incorporates gain control circuitry. When the RSSI voltage exceeds a threshold reference value corresponding to an RF input level of approximately -47dBm, the AGC switches on the LNA gain reduction resistor. The loading resistor reduces the LNA gain by 20dB, thereby reducing the RSSI output by approximately 260mV. The threshold reference voltage which is compared with the RSSI voltage to determine the gain state of the LNA is also reduced. The LNA resumes high-gain mode when the RSSI voltage drops below this lower threshold voltage corresponding to approximately -63dBm RF input. The AGC incorporates an additional protection mechanism (delay timer of 220×TREF seconds) to prevent immediate resetting of the LNA back to the high-gain state during reception of a “space” for OOK/ASK modulation. V1.4 4 October 2010 PT4301 MIXER A special feature of the PT4301 is its integrated double-balanced image-rejection mixer, which eliminates the need for a costly front-end SAW filter for many applications. The advantages of not using a SAW filter include simplified antenna matching, less board space, and lower BOM cost. The mixer cell is a pair of double-balanced mixers that perform an IQ down-conversion of the RF input to the 10.7MHz IF with low-side injection (i.e. fLO=fRF – fIF). The image-rejection circuit then combines these signals to achieve a typical 35dB of image-rejection ratio. Low-side injection is required since high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower biased to create a driving impedance of 330Ω to interface with an off-chip 330Ω ceramic IF filter. The voltage-conversion gain of the image-rejection mixer is approximately 18dB at 315MHz and 15dB at 433.92MHz with a 330Ω load. PHASE-LOCKED LOOP (PLL) The PT4301 utilizes a fixed divided-by-32 PLL to generate the receiver LO. The PLL consists of the voltage-controlled oscillator (VCO), crystal oscillator, asynchronous÷32 divider, charge pump, loop filter and phase-frequency detector (PFD). All these components are integrated on-chip. The PFD compares two signals and produces an error signal which is proportional to the difference between the input phases. The error signal passes through a loop filter with an approximately 400KHz bandwidth, and is used to control the VCO which generates an LO frequency. The VCO frequency is also fed through a frequency divider back to one input of the PFD, producing a feedback loop. Thus, the output is locked to the reference frequency at the other input, which is derived from a crystal oscillator (i.e. fREF=(fRF–fIF)/32). The block diagram below shows the basic elements of the PLL. Figure 3. Phase-locked Loop in PT4301 To achieve an accurate frequency for the crystal oscillator, it is recommended to specify the suitable load capacitors, C14 and C15. Specifying the value of 27pF is acceptable. Choosing a lower value of crystal parallel equivalent capacitance, C0=1.5pF is also a suitable, but this may increase the price of the crystal itself. Typically the value of C0_max is 7.0pF. Figure 4. Crystal Oscillator Circuit The reference oscillator frequency is close to 10.7 MHz intermediate frequency. It is necessary to avoid signal trace coupling between the reference oscillator and intermediate frequency. Otherwise, it would degrade receiver performance. LIMITER/RSSI The limiter is an AC coupled multi-stage amplifier with a cumulative gain of approximately 72dB that possesses a band-pass characteristic. The -3dB bandwidth of the limiter is around 12MHz. The limiter circuit also produces an RSSI voltage that is directly proportional to the input signal level with a slope of approximately 13mV/dB. The RSSI signal is used to demodulate ASK-modulated receive signals in the subsequent baseband circuitry. The RSSI output level has the dynamic range of approximately 80dB. V1.4 5 October 2010 PT4301 AUTOMATIC GAIN CONTROL (AGC) The AGC circuitry monitors the RSSI voltage level. As described previously, when the RSSI voltage reaches a first value corresponding to an RF input level of approximately -47dBm, the AGC reduces the LNA gain by 20dB, thereby reducing the RSSI output by approximately 260mV. When the RSSI voltage drops below a level corresponding to an RF input of approximately -63dBm, the AGC sets the LNA back to high-gain mode. Figure 5 shows the change of RSSI voltage versus RF input power. When the RSSI level increases and then exceeds 1.77V (RF input power rising), the AGC switches the LNA from high-gain mode to low-gain mode. As RSSI level decreases back to 1.16V (RF input power falling), the AGC switches the LNA from low-gain mode back to high-gain mode. The AGC has an additional protection mechanism (delay timer of 220×TREF seconds) when the LNA is reset back to the high-gain state. RSSI vs. RF Input Power 1.9 1.8 1.7 RSSI Level (V) 1.6 1.5 1.4 1.3 1.2 AGC Disable AGC Enable; RF Pow er from L to H AGC Enable; RF Pow er from H to L 1.1 1 0.9 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 RF Input Power (dBm) Figure 5. RSSI vs. RF Input Power DATA FILTER The data filter is implemented as a 2nd-order low-pass Sallen-Key filter as shown in Figure 6. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to approximately 1.5 times the highest expected data rate from the transmitter. Figure 6. Ideal Sallen-Key Filter Utilizing the on-board voltage follower and the two 100KΩ on-chip resistors, a 2nd-order Sallen-Key low pass data filter may be constructed by adding 2 external capacitors between pins 15 (DFO) and 18 (DFFB) and to pin 17 (OPP) as depicted in the Page 2. The following table shows the recommended values of the capacitors for different data rates. V1.4 6 October 2010 PT4301 Data Rate <2Kb/s 2Kb/s - 10Kb/s 10Kb/s - 20Kb/s 20Kb/s - 40Kb/s >40Kb/sNote C11 (pF) 1000 470 150 56 15 C10 (pF) 270 100 56 15 4.7 Notes: 1. The maximum data rate of PT4301 is 50Kb/s 2. The component values may be different, which depend upon the data duty and codec pattern. PEAK DETECTOR The peak detector generates a DC voltage which is proportional to the peak value of the received data signal. An external R-C network is necessary. The peak detector input is connected to the data filter internally, and its output is connected to pin 16 (DSN) through the R-C network. This output may be used as an indicator of the received signal strength in wake-up circuits or used as a reference for data slicing. The time constant is calculated using the driving current of the op-amp in data filter, 100µA. Figure 7. Circuit for Using Peak Detector for Faster Start-Up DATA SLICER The data slicer consists chiefly of a fast comparator, which allows for a maximum receive data rate of up to 50Kb/s. The maximum achievable data rate also depends upon the IF filter bandwidth. Both data slicer inputs are accessible off-chip to allow for easy adjustment of the slicing threshold. The output delivers a digital data signal (CMOS level) for subsequent circuits. The self-adjusting threshold on pin 16 (DSN) is generated by an R-C network or peak detector, depending upon the baseband coding scheme. The suggested data slicer configuration is shown in Figure 8. The cut-off frequency of the R-C integrator must be set lower than the lowest frequency appearing in the data signal to minimize distortion in the output signal. Figure 8. Circuit for Generating Data Slicer Threshold V1.4 7 October 2010 PT4301 DEMODULATION With different circuit combinations, the PT4301 may utilize two demodulation modes, called “peak mode” and “average mode.” PEAK MODE In conjunction with an external RC filter (R3 and C13), the threshold voltage may be set at the peak detector output for comparison as shown in Figure 7. The demodulated data enters into a quasi-mute state as the RF input signal becomes very small (when there is no RF signal received or the RF signal is too small) and the DATA output remains mostly at a logic “HIGH” level. If the environment is very noisy, the R3 value may be enlarged to achieve better immunity against noise, but at the cost of less sensitivity. AVERAGE MODE When the “average mode” has been set as shown in Figure 8, the DATA output will exhibit a toggling behavior similar to random noise. In this mode, better sensitivity may be achieved, but noise immunity is worse than in “peak mode.” SENSITIVITY AND SELECTIVITY In digital radio systems, sensitivity is often defined as the lowest signal level at the receiver input that will achieve a specified bit error ratio (BER) at the output. The sensitivity of the PT4301 receiver, when used in the 434MHz application shown in Figure 9, is typically -106dBm (OOK modulated with 2Kb/s, 50% duty cycle square wave in average mode) to achieve a 0.1% BER. The input was matched for a 50Ω signal source. At 315MHz, -108dBm sensitivity is typically achievable. The selectivity is governed by the response of the receiver front-end circuitry, the channel filter (off-chip 10.7MHz IF filter), and the data filter. Note the IF filter provides not only channel selectivity but also the interference rejection. Within the pass band of the receiver, no rejection for interfering signals is provided. Sensitivity for 433.92 MHz F requency Band 0 S ens it iv it y (dBm) -2 0 -4 0 -6 0 -8 0 -1 0 0 -1 2 0 411 414 417 420 423 426 429 432 435 RF Input Frequenc y (MHz ) Figure 9. Sensitivity of PT4301 V1.4 8 October 2010 PT4301 POWER-DOWN CONTROL The chip enable (CE) pin controls the power on/off behavior of the PT4301. Connecting CE to “HIGH” sets the PT4301 to its normal operation mode; connecting CE to “LOW” sets the PT4301 to standby mode. The chip consumption current will be lower than 1µA in standby mode. Once enabled, the PT4301 requires <10ms to recover received data. Figure 10. Timing plot of PT4301 Chip Enable under 27°C & -80dBm Input Power Test Condition. ANTENNA DESIGN For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L (in cm), may be calculated by using the formula L= 7132 f For example, if the frequency is 315MHz, then the length of a λ/4 antenna is 22.6cm. If the calculated antenna length is too long for the application, then it may be reduced to λ/8, λ/16, etc. without degrading the input return loss. However, the RF input matching circuit may need to be re-optimized. Note that in general, the shorter the antenna, the worse the receiver sensitivity and the shorter the detection distance. Usually, when designing a λ/4 dipole antenna, it is better to use a single conductive wire (diameter about 0.8mm to 1.6mm) rather than a multiple core wire. If the antenna is printed on the PCB, ensure there is neither any component nor ground plane underneath the antenna on the backside of PCB. For an FR4 PCB (εr=4.7) and a strip-width of 30mil, the length of the antenna, L (in cm), is calculated by L= V1.4 c 4× f × εr where “c” is the speed of light (3 x1010cm/s) 9 October 2010 PT4301 ANTENNA PART ESD PROTECTION PT4301 IC provides the ESD level (Human Body Mode) better than 3KV at LNAIN pin. However, the higher ESD protection level would be required in system level for some applications. The extra ESD protection level could rely on the external components. Changing L1 from SMD type to coil type could enhance ESD protection level of around 1KV, and adding a shunt coil inductor L3 in the front of C4 to gain more ESD protection enhancements. C4 L3 RF Frequency fRF 315MHz 340MHz 390MHz 433.92MHz To LNAIN L1 Suggestion Value of L3 39nH 39nH 33nH 27nH Figure 11. Antenna ESD Protection Inductor of PT4301 PCB LAYOUT CONSIDERATION Proper PCB layout is extremely critical in achieving good RF performance. At the very least, using a two-layer PCB is strongly recommended, so that one layer may incorporate a continuous ground plane. A large number of via holes should connect the ground plane areas between the top and bottom layers. Note that if the PCB design incorporates a printed loop antenna, there should be no ground plane beneath the antenna. Within the PT4301, the power supply rails of the LNA and others blocks should be separated for improving the isolation and minimizing the noise coupling effects. Careful consideration must also be paid to the supply power and ground at the board level. The larger ground area plane should be placed as close as possible to all the VSS pins. To reduce supply bus noise coupling, the power supply trace should be incorporate series-R, shunt-C filtering as shown in Figure 12. Figure 12. Noise Rejection Filter for Power Bus V1.4 10 October 2010 PT4301 ABSOLUTE MAXIMUM RATINGS (VSS=0V) Parameter Supply voltage range Operating temperature range Storage temperature range Soldering temperature Soldering time Symbol VDD5 Topr Tstg TSLD tSLD Rating VSS-0.3 to VSS+6.0 -40 to +85 -55 to +125 255 10 Unit V ℃ ℃ ℃ s RECOMMENDED OPERATING CONDITIONS (VSS=0V) Parameter Symbol Supply voltage range Operating temperature V1.4 VDD5 TA 11 Min. 2.4 -40 Value Typ. 5.0 27 Max. 5.5 85 Unit V ℃ October 2010 PT4301 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, VDD5=5.0V, VSS=0V, CE=“HIGH”, Temp=27℃) Parameter General Characteristics Frequency range Maximum receiver input level SensitivityNote1 Note3 Symbol fRF PRF,MAX SIN Data rate Image rejection ratio LO leakage DRate IMR LLO System start-up time Tstart-up Condition ASKNote2, peak power level @315MHz OOK, peak power level @315MHz ASK, peak power level @434MHz OOK, peak power level @434MHz Min. Value Typ. 250 -25 -20 25 Max. Unit 500 MHz dBm -114 -112 dBm -108 -106 dBm -112 -110 dBm -106 -104 dBm 2 35 50 -80 Kb/s dB dBm 10 ms 5.0 5.5 V 5.0 5.3 5.5 5.9 1.0 mA mA µA 16 15 3 20 18 3.6 dB dB dB Measured at RF input RF input power=-60dBm Temp=27℃ Power Supply Supply voltage VDD5 Consumption DC current IDD5 Standby DC current LNA Istand-by 13 12 NFLNA IIP3LNA Matched to 50Ω -20 GLNA Noise figure Input third-order intermodulation intercept point Auto Gain Control (AGC)Note4 AGC hysteresis LNA voltage gain reduction AGC delay time Down-conversion Mixer Input third-order intermodulation intercept point Output impedance PLL Reference frequency VCO frequency range Limiter Amplifier and RSSI IF frequency Input impedance RSSI dynamic range RSSI gain 2.4 Matched to 50Ω@315MHz Matched to 50Ω@434MHz Matched to 50Ω Power gain Conversion voltage gain Connect the supply voltage to VDD5 pin only CE=”HIGH”@315MHz CE=”HIGH“@434MHz CE=”LOW” HAGC GRed DYAGC GMIX TREF=1/fREF @315MHz @434MHz 15 12 dBm 16 20 220×TREF 30 dB dB s 18 15 22 18 dB dB -18 IIP3MIX ZOUT,MIX dBm 330 fREF fVCO 6 220 fIF ZIN,LIM DRRSSI SLRSSI Ω 16 550 10.7 330 80 13 MHz MHz MHz Ω dB mV/dB Notes: e-3 1. BER=1 , data rate=2Kb/s. 2. AM 99% square-wave modulation. 3. The selection of data rate depends upon the component values use for the data filter, peak detector, and slicer. 4. AGC hysteresis and LNA gain reduction depend upon the gain setting and matching circuits of the LNA. The AGC delay time depends upon the PLL reference frequency. V1.4 12 October 2010 PT4301 TEST BOARD LAYOUT <Top Side> <Bottom Side> Figure 12. Example of Test Board Layout V1.4 13 October 2010 PT4301 PACKAGE INFORMATION 24 PINS, SSOP, 150MIL Symbol A A1 b c D E E1 e L θ Min. 0.10 0.20 0.10 Nom. 8.66 BSC 5.99 BSC 3.91 BSC 0.635 BSC - 0.41 0° Max. 1.75 0.25 0.30 0.25 1.27 8° Notes: 1. Refer to JEDEC MO-137AE. 2. All dimensions are in millimeter. V1.4 14 October 2010 PT4301 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.4 15 October 2010