KESRX04 260 to 470MHz. ASK Receiver with Power Down Preliminary Information DS4997 - 1.5 August 1998 FEATURES ■ In-band interference rejection (typ. 14dB) ■ -103dBm Sensitivity (IF BW = 470kHz) ■ AGC around LNA and Mixer ■ Low supply voltage (3 to 6V) ■ 2 stage power-down for low current applications ■ Interface for ceramic IF filters up to 15MHz P The KESRX04 is a single chip ASK (Amplitude Shift Key) Receiver IC. It is designed to operate in a variety of low power radio applications including keyless entry, general domestic and industrial remote control, RF tagging and local paging systems. The receiver offers an exceptionally high level of integration and performance to meet the local oscillator radiation requirements of regulatory authorities world-wide. Functionally the device works in the same way as the KESRX01 with the added features of low supply voltage, in-band interference rejection (anti-jamming detector), a 2 stage power down to enable receiver systems to be implemented with less than 1mA supply, and a wide IF bandwidth and drive stage to interface to an external ceramic IF band pass filter at intermediate frequencies from 0.2MHz to 15MHz. The KESRX04 is an ideal receiver for difficult reception areas where high level interferers would jam the wanted signal. The anti-jamming circuit allows operation to be possible with interfering signals which are more than 14dB stronger than the wanted signal, without the cost penalties of increased IF selectivity and frequency accuracy. IFFLT2 IFFLT1 RSSI PIN 1 REF. SPOT IFDC1 IFIN IFDC2 (9.80/10.01) VCC DETB PD XTAL1 XTAL2 IFOUT VCCRF DF0 MIXIP DF1 RFOP DF2 VEERF VCO1 RFIN VCO2 AGC VEE LF PEAK DSN DATOP QP28 Figure 1 Pin Connections (top view) APPLICATIONS ■ Remote Keyless Entry ■ Security, tagging ■ Remote Controlled equipment ORDERING INFORMATION KESRX04/IG/QP1S (anti-static tubes) KESRX04/IG/QP1T (tape and reel) ABSOLUTE MAXIMUM RATINGS Supply Voltage Vcc Storage temperature,Tstg Junction Temperature, Tj RF Input power -0.5V to +7V -55 to 150°C -55 to 150°C +20dBm from 50Ω agc RF Input Ceramic IF Filter mixer SAW Filter LNA RSSI detector Noise reduction Filter Local Oscillator Figure 2 Typical system application Anti-jam data filter Slicer Sliced data Ref KESRX04 PIN DESCRIPTION Pin Symbol 1 2 IFFLT1 IFDC1 Noise reducing IF filter Log amp dc stability capacitor Function 3 4 IFIN IFDC2 Log amp input Log amp dc stability capacitor 5 6 VCC IFOUT Positive supply IF output to external IF filter 7 8 VCCRF MIXIP Positive supply for RF circuits Mixer input 9 10 RFOP VEERF Output from LNA Negative supply for RF circuits 11 12 RFIN AGC Input to LNA RF AGC time constant 13 14 PEAK DATOP Data signal peak detect Sliced data output 15 16 DSN LF Data slice level PLL loop filter 17 18 VEE VCO2 Negative supply Voltage controlled oscillator 19 20 VCO1 DF2 Voltage controlled oscillator Data filter 21 22 DF1 DF0 Data filter Data filter 23 24 XTAL2 XTAL1 Crystal oscillator Crystal oscillator 25 26 PD DETB Power down Anti-jam detector input 27 RSSI RSSI output 28 IFFLT2 Noise reducing IF filter DESCRIPTION The single-conversion super-heterodyne receiver approach is now generally considered the way forward for ISM band type applications because of lower cost, superior selectivity, lower radiation, and flexibility over other techniques. For powerconscious, hand-held applications KESRX04 provides improved performance and flexibility on a lower 3.0V supply and a power-down feature allows faster switch-on times for use in a pulsed power saving mode. Although this is a relatively simple receiver, the flexibility of using an external IF filter allows the designer to choose both the selectivity and the IF in order to optimise the performance for a wide range of applications and locations world wide. 2 The KESRX04, with its Anti-jamming detector circuit, is an ideal ASK / OOK receiver for difficult reception areas caused by interference such as “Amateur Radio Repeater Stations” and Wireless Stereo Head-Phones”. Operation is possible with interfering signals which are more than 14dB stronger that the wanted signal (IF bandwidth = 470kHz.), without the cost penalities of increased IF selectivity and frequency accuracy. Figure 2 is the system block diagram for the device with an external ceramic IF filter, SAW fillter and noise reduction filter. KESRX04 ELECTRICAL CHARACTERISTICS Test conditions T amb = –40°C to + 85°C, VCC = 3.0V to 6.0V. These characteristics are guaranteed by either device characterisation, production test and or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated using test circuit Figure 12. Characteristic Symbol Value Supply voltage VCC Min 3.0 Ambient temperature Test Frequency Ta –40 Max 6.0 +85 470 local Oscillator ESD Protection: Typ Units 480.7 Conditions V °C MHz MHz local oscillator frequency configured for high side injection, except where otherwise specified All pins meet 2kV Human Body Model requirement. Except pins 9 and 11, which are limited to 700V and pins 18 and 19 which are limited to 1.00kV. ELECTRICAL CHARACTERISTICS D.C. T amb = –40°C to + 85°C, VCC = 3.0V to 6.0V. These characteristics are guaranteed by either device characterisation production test and or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Symbol Min Value Typ Max Units Condition Supply Current Receive mode (PD2) Icc 3.7 4.5 mA All. PD=High. RF input <-50dBm. Power down (PD1) Icc1 0.33 0.5 mA All. PD=Vcc/2 or high impedance source. Vcc = 3 to 6.0V (4) Power down (PD0) Icc2 33 50 µA All. PD=low ELECTRICAL CHARACTERISTICS A.C Parameter Symbol Value Min Typ Units Condition Max Input frequency range fs 260 470 MHz All Intermediate Frequency IF 0.2 15.0 MHz. All. (8) Sensitivity (test fixture) Vin(min) 8.0 23.0 µVrms 20kB/s data rate at 470MHz. (1) Sensitivity (application) Vin(min) 1.5 µVrms Circuit as Figure 11 with SAW filter removed1kB/s data rate at 433.92MHz. (3) Overload Performance Vin(max) PLL control line (pin 16) To achieve 90% of final ts2 0.5 2.23 2.0 Vrms 4.0 mS value PD0 to PD2 All. Circuit as Figure 11 (5) Local Oscillator low side Injection 423.33 MHz. PLL control line (pin 16) To achieve 90% of final value PD1 to PD2 ts3 Data output Voltage High Voh Data output Voltage Low Vol Conducted emissions 20kB/s data rate at 470MHz. (2) Antenna (LO) 1.0 3.0 mS All. Circuit as Figure 11 (5) Local Oscillator low side Injection 423.33 MHz. Volt Ioh=+10µA 0.7 Volt Iol=-10µA 100 µVrms Vcc-0.7V 5.6 All Figure 11 (6), local Osc. low side injection = 423.3MHz . 3 KESRX04 ELECTRICAL CHARACTERISTICS A.C.(continued) These characteristics are typical values measured for a limited sample size. They are not guaranteed by production test. They are only given as a design guide to assist during the design-in phase of KESRX04. Parameter Symbol Value Units Condition Min Anti-jam rejection Typ +14 Max dB Internal RF Amplifier Parallel input impedance Rfin 1.0 // 1.8 Parallel input impedance Rfin 1.6 // 1.9 Parallel output impedance Rfout 8.8 // 1.7 Parallel output impedance Rfout 18 // 1.8 Noise Figure NF 4.5 Noise matching Impedance Rfin 1.0 // 4.6 1dB compression point (input referred) Rfin -20 dBm Amplifier gain RFamp 13 dB MIXER Parallel input impedance MIXIP 1.6 // 1.8 Parallel input impedance MIXIP 1.6 // 1.8 Output impedance IF1 300 Noise Figure (Double side band measurement) NF 10 dB Amix 9 dB Mixer conversion gain Unmodulated interfering signal = -76dBm 433.82MHz. OOK modulated wanted signal = -90dBm 433.92MHz Figure 5 (7) KΩ // pF Fs=434MHz, Vcc= 5V, Tamb =25°C KΩ // pF Fs=315MHz, Vcc= 5V, Tamb =25°C KΩ // pF Fs=434MHz, Vcc= 5V, Tamb =25°C KΩ // pF Fs=315MHz, Vcc= 5V, Tamb =25°C dB Fs=434MHz; Vcc= 5V, Tamb =25°C matched 50ohm environment input and output KΩ // nH Fs=434MHz, Vcc= 5V, Tamb =25°C Fs=434MHz, Vcc= 5V, Tamb =25°C matched 50ohm environment input and output Fs=434MHz., Vcc= 5V, Tamb =25°C O/P matched to Mixer input impedance RF Amplifier is conditionally stable KΩ // pF Fs=434MHz, Vcc= 5V, Tamb =25°C KΩ // pF Fs=315MHz, Vcc= 5V, Tamb =25°C Ω Fs=10.7MHz, Vcc= 5V, Tamb =25°C Fs=434MHz; Vcc= 5V, Tamb =25°C matched 50ohm environment input and output Fs=434MHz., Vcc= 5V, Tamb =25°C Measured at input to ceramic filter. Includes 6dB matching loss IF Strip (RSSI) IF2 input impedance 4.0 KΩ IF=10.7MHz, Vcc= 5V, Tamb =25°C IF gain of log amp 4 Alog 80 dB All, Vcc= 5V, Tamb =25°C KESRX04 Notes: 1. The Sensitivity of the test fixture Figure 12 is degraded by loading the input to RF amplifier with 50 ohms, lack of image rejection and increasing the data filter bandwidth to 50kHz. Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0.01 where the input signal is a return to zero pulse at 470MHz.,with an average duty cycle of 50%, 20kB/s data rate with the receiver bandwidth set to 470kHz. 2. Peak RF input level, pin RFIN, to overload the demodulator with the AGC operating. Equivalent to +7dBm for 50 ohm input impedance. Where the input signal is a return to zero pulse at 470MHz. with an average duty cycle of 50%. 20kB/s data rate with the receiver bandwidth set to 470kHz. 3. Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0.01 where the input signal is a return to zero pulse with an average duty cycle of 50%, 1kB/s data rate. Equivalent to -103dBm for 50ohm input impedance. Does not include insertion loss of SAW filter at RF input but does include IF filter of 470kHz 3dB bandwidth and a data filter bandwidth of 5kHz. This equates closely to a measurement of tangential sensitivity. 4. The performance of the power down option PD1 to PD2 cannot be guaranteed below 3V for temperatures less than 0°C 5. Time taken for PLL lock voltage to achieve 90% transition point of the control signal and the VCO frequency to achieve within 470kHz of the final frequency. The time taken to acquire PLL acquisition is governed by the PLL loop filter (C12, C1 and R2) and the crystal oscillator components (XTAL1, C13 and C14). The dominant term for PLL aquistion is the startup time of the crystal oscillator circuit, provided the PLL loop filter settling time is much less than the crystal oscillator startup time. Figure 6 illustrates a suitable test setup for measuring the acquisition time of the PLL. The electrical characterisation parameters are based on the following set of conditions: Crystal Oscillator circuit C13 = C14 = 15pF XTAL 1 Freq. 6.6128 MHz. ESR 15.3 Ω L 85.36 mH C0 1.83 pF C1 6.8 fF PLL loop filter C12 = 1.5 nF, C1 = 180pF R1 = 10KΩ 6. Local oscillator power fed back into 50ohm source at antenna input (RF input). Measured with RF input matching network shown in Figure 11. 7. In-band interference rejection for an unmodulated interfering signal at 100kHz. low side from the wanted modulated signal at 433.92MHz. to achieve a Bit Error Rate =0.01. Figure 5 illustrates a suitable test set-up for measuring the interference rejection and selectivity of the receiver. Wanted signal = (1kB/s. 50% duty cycle) -90dBm at 433.92MHz. Interfering signal = (unmodulated) -76dBm at 433.82MHz. Interference rejection typically equals +14dBm. i.e. in-band interfering signal is 14dBm above the wanted signal level at –90dBm. 8. Actual intermediate frequency determined by choice of crystal and external ceramic filter. 5 KESRX04 Functional Operation Power Down The PD pin, a tristate input, provides a 2 stage power down for the receiver. The receiver is fully operational when the pin is held high and is fully powered down when the pin is taken to ground. Status PD0 PD1 PD2 PD Pin Low (0V) Vcc/2 High (Vcc) Status Receiver powered down Crystal oscillator running Receive mode PD0 = Low. None of the receiver circuits are functional. Current, Icc2, is reduced to its lowest level, <50µA (Vcc applied). A longer settling time (ts2) is required to restore full performance after switching to receive mode, PD0 to PD2 (Figure 6). PD1 = Vcc/2 or high impedance source (CMOS tristate). A non-receiving state with some critical circuits running including the crystal oscillator. Current consumption, Icc1, is reduced to about 330µA. When switching to the receive state, PD1 to PD2 (Figure 6), data can start to be recovered within 1ms (ts3) for signals close to maximum sensitivity. PD2 = High. The receiver is fully functional ready to receive data. RF down-converter An internal RF amplifier is designed to interface to an input SAW filter with a maximum insertion loss of 3dB. The RF amplifier gain is about 13dB at 460MHz when matched into the mixer, while the RF amplifer noise figure is about 4.5dB when fed from a 50 ohm source. The internal RF amplifier is conditionally stable and feeds a double balanced mixer through an external impedance matching circuit, RFOP to MIXIP. The AGC circuit monitors the mixer signal output level. Control is fed back, applying AGC to the RF amplifier to prevent overloading in the mixer and the generation of unwanted distortion products. This also has the effect of reducing the RSSI characteristic slope and extending its range of operation by more than 20dB at high signal levels, compare Figure 9B and Figure 9C. The AGC circuit also applies mixer booster current to improve the linearity of the mixer at high signal levels. This can be confirmed by monitoring the current consumption of the receiver with applied RF signal level Figure 9D. 6 The AGC circuit comes into operation at input signals greater than ~ -35dBm and reduces the RF amplifer gain by 6dB at an input signal level of ~ -25dBm. Since the AGC operates on the mixer output signal level then the exact point where the AGC comes into operation depends on the RF amplifer to mixer matching circuits and RF amplifer gain. IF interface Unlike KESRX01 there is no internal integrated IF filter. This is to provide a more flexible design and allows the system designer to use a low IF or high IF up to 15MHz. Typically, a 10.7MHz Ceramic IF filter connected between IFOUT and IFIN would be used together with an input RF SAW filter to give very good image channel rejection. The choice of bandwidth for the 10.7MHz ceramic filter depends on frequency tolerancing of the transmitter, receiver, data rate and component cost. The IF filter drive, IFOUT, is a voltage drive with a 300 ohm series resistance. This allows impedance matching to the ceramic IF filter to be set by an external series resistor. A 10.7MHz ceramic filter with, typically, a 300 ohm input impedance does not require an external matching resistor at IFOUT. The input to the log amp, IFIN, is high impedance with an internal 4Kohm shunt resistor. Impedance matching to the output of the ceramic filter is achieved by an external shunt resistor R9 between IFIN and IFDC1. Phase Lock Loop VCO The local oscillator (LO) is a VCO locked to a crystal reference by a phase lock loop (PLL). The VCO gain is nominally 40MHz/Volt depending on the external varactor used. The LO frequency is divided by 64 and fed into the phase-frequency detector, where the reference frequency is provided from the crystal oscillator. The phase detector output current into the PLL loop filter is nominally ±30µA. The max loop filter bandwidth is 50kHz. Conducted LO signals capable of being radiated from the antenna of the complete receiver are suppressed to a level of <-65dBm into 50ohms. KESRX04 Voltage Controlled Oscillator (VCO) Circuit Design / Layout The Local Oscillator (LO) frequency is controlled by a parallel resonant tuned circuit. The frequency of the local oscillator is controlled by a Phase Locked Loop (PLL), referenced to the crystal frequency. Designing for VCO Track Parasitics Cp = To remove the effect of track parasitics the following procedure should be adopted. 1 ( 2π * LO) 2 * L2 (( ) ) -Cv Cv: Varactor capacitance at Vcc/2 8. Using the following equation select the nearest value for L2 to centre the VCO at VCC/2. 1. Open circuit the control feed back from the PLL control loop by removing R1. 2. Connect an external Power Supply Unit (PSU = VCC/2) in place of R1, LF output Figure 3. 3. Using a spectrum analyser, monitor the LO level at the RFin port. Alternatively use a small pick-up coil to loosely couple to the signal generated across L2. 4. Note :- LO level is < -65 dBm, Range = 300 to 500MHz. 5. Vary the value of the PSU input to confirm that there is a corresponding change in LO frequency. Set the PSU at VCC/2. If the VCO does not oscillate at VCC/2, characterise the LO at an alternative voltage. 6. Using a plot of the varactor characteristic determine the varactor capacitance at VCC/2. e.g. for a 2 volt VCC design the Siemens BB833 capacitance at 1Volt = 10pF (approx.). 7. Using the following equation deduce the value of the total stray parasitic capacitance (Cp). L2 = 1 ( 2 π * LO) * (Cp + Cv ) 2 9. By varying the PSU voltage confirm that the LO is centred correctly at VCC/2, and that the oscillator operates over the range 0 to Vcc. 10. Disconnect the PSU and reconnect R1. Measure the value at LF output using a x10 probe and an oscilloscope. This should be a direct voltage with no ripple at VCC/2 (+/- 0.3 volt). If not repeat steps 1 to 8. To compensate for non standard inductor values vary the value of C18 and C11 to vary the capacitance of the varactor to centre the VCO at VCC/2. Note: It is important to minimise stray capacitance in the VCO circuit to ensure that the VCO starts oscillating. The use of a varactor with a low capacitance at zero bias is advisable. Similarly, reducing the values of C11 and C18 whilst increasing L2 will help to reduce the capacitance of the varactor at 0 volts, improving the reliability of the oscillator. A compact design methodology is recommended for the VCO circuit components L2, C11, C18 and D1. C11 VCO1 (pin 19) R4 L2 C18 VCO Buffer D1 VCO1 (pin 18) Connectfor characterisation DIV 64 RTest (=R1) PSU C12 LF (pin 16) Phase Detector R1 XTAL 1 XTAL1/2 (pins 23/24) C1 R2 KESRX04 Figure 3 Characterising the VCO/PLL operation 7 KESRX04 IF amp/RSSI detector This is a log amplifier with a gain > 80dB and an RSSI output used as the detector. The 3dB bandwidth of the IF log amplifier is typically 20MHz to allow for high IF’s to be used. However, normally, this wide IF bandwidth would limit the overall sensitivity of the receiver due to the amplified wide band noise generated in the first IF stage. The RSSI detector is not frequency selective so that any wide band noise introduced after the intermediate filter will be detected as signal. A simple LC noise reduction filter is therefore positioned part way down the log amplifier to reduce the noise power from the earlier stages. Typically this filter only needs to be a fixed component parallel LC filter (L5 // C7) between pins IFFLT1 and IFFLT2 with a 1MHz bandwidth (i.e. Q~10). There is an internal 20Kohm damping resistor across these pins which will determine the Q and the choice of L and C values. i.e. L= 20000 ; 2.π . f IF. Q C= Q 2. π. f IF. 20000 An external damping resistor should not be used as this will alter the gain of the log amplifier. A ceramic resonator or filter is not a suitable component here as a low impedance dc path must be maintained to remove dc voltage offsets in the high gain log amplifier. Further improvement in sensitivity can be gained by using a narrow band IF ceramic filter and a narrower noise reduction filter. For a low IF receiver, <1MHz, a low pass filter can be used for both the IF and noise reduction filters. Such a receiver however will have virtually no image rejection capability, and will thus have a 3dB penality in noise factor impairing the ultimate sensitivity of the receiver by a minimum of 3dB. The RSSI output transfer characteristic, at pin RSSI, has a slope of about 16mV/dB. A typical transfer characteristic from RF in input to RSSI output is plotted in Figure 9B, measured with a constant RF input signal. This shows the effect of the AGC in extending the range of the detector to +10dBm RF input signal and includes the effect of the AGC circuit adapting to this signal level. Because the RF amplifier AGC has a fast attack time - slow decay time characteristic the gain of the stage remains constant during the data burst. This means that the change in output for a given extinction ratio also remains constant at approximately 16mV/dB up to peak input signal levels >+10dBm. This requires the decay time constant to exceed the transmitted bit period and no long period of zero signal power has been transmitted. Increasing the decay time constant of the AGC circuit by increasing the value of C8 will impair the settling time (time to good data) of the receiver. When duty cycling the operation to the receiver between PD0 and PD2 to lower power consumption of the receiver. When Duty cycling the receiver between PD1 and PD2 the settling time of the receiver is independent of C8. In the application circuit Figure 11 the value of C8 is configured for minimum settling time. Anti-jamming Circuit The output of the RSSI is AC coupled into the Anti-jamming circuit where the signal is DC restored on the peak signal level Figure 7. The coupling capacitor charges to the appropriate DC level which is related to the final slice level for the data comparator. The anti-jamming circuit amplifies the peak of the signal to recover the data signal component even in the presence of CW jamming signals. The interferer causes modulation of the wanted signal at the beat frequency of the two signals and reduces the amplitude of the wanted data component making it more difficult to recover. By-passing the anti-jam circuit Figure 8 will result in data corruption for interfering RF signal levels 6dB below the wanted signal (Figure 5A) The DC restoration circuit has a fast attack time and slow decay time, both controlled by the value of coupling capacitor chosen between RSSI and DETB pins. Figure 5 illustrates a suitable test setup for characterising the interference rejection and selectivity of the receiver. Figure 5A illustrates the in-band interference rejection with the anti-jam circuit connected Figure 7 and by-passed(Figure 8) at 3V Tamb = 25°C. Note, the improvement in interference rejection between the two modes of operation over the wanted signal range of -94 to -20dBm. Figure 5B illustrates the difference in receiver selectivity with the ant-jam circuit connected (Figure 7) and by-passed (Figure 8). Note, the improvement in receiver selectivity between the two modes of operation. The selectivity curve with the antijam circuit by-passed is governed by the response of the front end SAW filter, IF ceramic filter and data filter. Providing no rejection for interfering signals within the pass band of the receiver. Whereas the receiver with the anti-jam circuit connected actively responds to the presence of the in-band interfering signal to recover the wanted OOK modulated signal. The action of the anti-jam circuit centres the bandwidth of the receiver around the wanted signal proportional to the data filter bandwidth to suppress the interfering beat frequency. Figures 5A and 5B were recorded with the following component specification. Component Specification (Figure 7) Anti-Jam removed (Figure 8) R6 C2 Data Filter BW IFBW SAW BW OOK modulation R6 C2 Data Filter BW IF BW SAW BW OOK modulation 130KΩ 270pF 5kHz 470kHz 750kHz 4kB/s (50% duty cycle) Component specification for Figure 5A and 5B 8 12KΩ removed 5kHz 470kHz 750kHz 4kB/S (50% duty cycle) KESRX04 Interference rejection (dB) = Interferer (dBm) - Wanted (dBm) i.e. Fc = 5 * The interference rejection of the receiver for different modulation schemes can be improved by: • Changing the value of C2. Increasing the value of C2 will result in pulse stretching of the recovered signal • Adjusting the comparator reference level (DSN) by offsetting the internal reference (Figure 4) by a high value resistor from the DSN pin to Vee and or the peak detector output. (Figure 11). • Reducing the bandwidth of the data fillter, intermediate frequency filter and or the noise reduction filter (L5 // C7). Thebandwidth of the receiver must accommodate tolerancing of the data, transmitter and receiver. • Increasing the value of AGC capacitor C8 to maintain the level of the AGC control during the “OFF” period of the wanted modulation signal. This will improve the interference rejection of the receiver but increase the time to good data from power-up PD0 to PD2. The application circuit Figure 11 has been optimised for time to good data. Baseband The RSSI output will contain wide band demodulated noise and signals which are within the RF and IF filter pass bands. An additional low pass data filter is therefore used to improve overall sensitivity. KESRX04 has an integrated second-order Sallen-Key data filter whose characteristic is set by R10, R11, C5 and C6. Figure 7 shows the connections and calculation for the -3dB cut-off frequency and filter type, The cut-off frequency is determined from the data rate and the level of pulse distortion which can be tolerated. The data filter cut off frequency is usually set at 3 to 5 times the minimum pulse width period. RFOP MIXIP IFOUT IFIN 1 ( DataPulsewidth) The output from this filter, DF2, is directly coupled into the inverting input of the data comparator with a fixed slice level applied to the non-inverting input, DSN. A peak detector recovers the signal amplitude on the capacitor. Normally, the comparator reference level used is the internal reference, a capacitor at Pin DSN serving to remove noise pick-up. In order to fine tune the slice level for sensitivity, squelch and optimum interference rejection the slice level can be offset from the internal reference by a high value resistor from the DSN pin to Vee and or the peak detector output (Figure 11). The data comparator (slicer) output, DATOP, is CMOS compatible but is only capable of driving small capacitive loads, <20pF, depending on data rate. Data output has the inverted sense of the input signal at DF2. The output drive current is nominally ±30µA so that a system using high data rates or higher capacitive loads, e.g. long track lengths, may need to incorporate a buffer transistor to provide the necessary edge speeds to the following logic circuits. The comparator has 20mV hysteresis built-in to reduce edge chatter. The sense of the squelch on the data output is LOW when no signal is present. This may be confusing, as a LOW output during the data burst also corresponds to the ‘ON’ period, i.e. the MARK, of the RF OOK signal. However, it is the very first pulse of the data signal which causes the DC restoration capacitor of the anti-jamming circuit to charge to the correct level appropriate to the final slice level. As a consequence of this the very first pulse of the data transmission may be lost as the receiver adapts to the incoming signal level. IFFLT1 IFDC2 IFDC1 RSSI DETB DF0 DF1 IFFLT2 DF2 PEAK DET PEAK VCCRF ANTI-JAM LIM AMP DATA FILTER DATA SLICER AGC AGC DATAOP DSN DIV 64 PFD 100K XTAL OSC RFIN LNA Vref VCO VEERF VCO2 VCO1 PD VCC LF XTAL2 XTAL1 VEE Figure 4 block schematic of KESRX04 9 KESRX04 Pulse Generator Variable Delay Line RX CLK 4KB/S (50% Duty Cycle) OOK Input Bit Error Rate KESRX04 PCB Wanted Signal 433.92 MHz. N/C N/C RFin RFGND GND Vcc DATA PD N/C Signal Generator 1 Trigger Buffer Amplifier RFin Interfering Signal 433.82 MHz. DATA O/P Hydbrid Combiner Signal Generator 2 Oscilloscope DC PSU (3 to 6V) Figure 5 Characterising the selectivityand interference rejection Note : (dB) Variable delay line used to equalise the propagation delay of the receiver. Buffer amplifier used to drive the low impedance input of the Bit Error Ratio analyser. High impedance (*10 probe) oscilloscope probe recommended. Interferer Rejection Ratio 1 2 3 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -100 Anti-jam circuit connected Anti-jam circuit By-passed -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 Wanted Signal level (dBm) at 433.92MHz (4kB/s 50% duty cycle) Figure 5a In-band interference rejection of the receiver Note: 10 Unmodulated interfering signal is 100kHz low side from wanted signal. Both signals are within the passband of the receiver (ceramic filter) KESRX04 90 Anti-jam connected 80 Selectivity Response (dB) 70 60 50 40 30 20 Anti-jam By-passed 10 0 -10 -20 431 431.5 432 432.5 433 433.5 434 434.5 435 435.5 436 Frequency Response (MHz.) Figure 5b KESRX04 selectivity response Note: The action of the anti-jam circuit to centre the bandwidth of the receiver around the wanted modulated signal at 433.92MHz KESRX04 PCB PLL PLL N/C N/C RFin RFGND GND Spectrum Analyser PLL Vcc DATA PD N/C Oscilloscope 1 Power Down Trigger GND +/- 470KHz. Power Down Switch DC PSU (3 to 6V) t Figure 6 Characterising the PLL aquisition time from power-up Note : 1 2 3 4 High impedance (*10 probe) oscilloscope probe recommended Loosely coupled antenna or high impedance FET probe recommended for the spectrum analyser measurement. Time taken for PLL to achieve 90% of final voltage and the VCO within +/- 470kHz. of final frequency (423.33MHz.) Power down switch operation. • • • PD0 = PD pin connected to GND, receiver fully powered down. PD1 = PD pin open circuit or connected to Vcc/2, crystal oscillator running. PD2 = PD pin connected to Vcc, receiver fully operational. 5. Spectrum analyser set to PLL lock frequency (423.33MHz), zero span 470kHz IF bandwidth, t sweep 20mS. 11 KESRX04 C5 R10 C10 RSSI C2 C6 DF0 DETB 100k RSSI Output Anti-Jam Circuit R11 AMP A DF1 DF2 PEAK Sallen Key Sallen-key Data filter Data Filter AMP B - DATOP AMP C + SLICER REF DSN 100k Internal Ref. voltage Figure 7 Anti - jamming circuit and data filter Sallen-Key Data filter components ωc = 2πfcY: fc: cut off frequency (Hz) C5 = 2.Q R.ωc Bessel Q=0.577 Y=1.732 C6 = 1 2.Q.R.ωc Butterworth Q=0.71 Y=1.0 Example To implement a Bessel response filter with a 10kHz 3dB cut-off frequency, R = 100kohm Bessel Filter Butterworth Filter 12 C5 = 106pF C5 = 150pF C6 = 80pF C6 = 150pF KESRX04 C5 R10 R11 C10 C6 RSSI DF0 DETB DF1 DF2 PEAK C22 100k RSSI Output Anti-Jam Circuit AMP B AMP A DATOP AMP C Sallen Key Sallen-key Datafilter Data Filter SLICER R6 REF 100k DSN REF Figure 8 By-passing the anti - jamming circuit Ω 10.7 Before Connecting Remove IF Filter 100nF MHz. Signal Generator 2 KESRX04 PCB IFIN RSSI Oscilloscope 1 FET Probe IFOUT AGC Spectrum Analyser N/C N/C RFin RFGND GND Vcc DATA PD N/C Volt meter 433.92 MHz. Unmodulated Signal A Signal Generator 1 DC PSU (3 to 6V) Figure 9 Characterising the receiver performance (Figure 9A to 9D) Note: 1. 250 Ohms added to signal generator 2 to modifiy its characteristic impedance to mimic the output impedance of the ceramic filter. 2. 100nF capacitor to prevent de-biasing of IFIN. 13 KESRX04 35 30 25 Conversion Gain (dB) 20 15 10 Conversion Gain @ 3V Conversion Gain @ 6V 5 0 -5 -10 -15 -20 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 RFIN Unmodulated Carrier at 433.92MHz (dBm) Figure 9a RFIN to IFOUT conversion gain 1.8 1.6 RSSI Voltage (V) 1.4 1.2 Pin 27 RSSI Voltage (V) @ 3V Pin 27 RSSI Voltage (V) @ 6V 1 0.8 0.6 0.4 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 RFIN Unmodulated Carrier at 433.92MHz (dBm) Figure 9b RFIN to RSSI output transfer characteristic See Notes on page 15 14 20 KESRX04 2 1.8 1.6 RSSI Voltage (V) 1.4 1.2 Pin 27 RSSI Voltage (V)@ 3V Pin 27 RSSI Voltage (V) @ 6V 1 0.8 0.6 0.4 0.2 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 IFIN Unmodulated Carrier at 10.7MHz (dBm) Figure 9c IFIN to RSSI output transfer characteristic 7.7 7.2 6.7 Current Consumption (mA) 6.2 5.7 Current 3V Current 6V 5.2 4.7 4.2 3.7 3.2 2.7 -100 -80 -60 -40 -20 0 20 RFin Unmodulated Carrier at 433.92MHz. (dBm) Figure 9d Receiver current consumption V s received signal strength RFIN Note: 1. Conversion gain of the receiver is limited by the insertion loss of the front end SAW filter. 2. Dynamic range of RSSI output transfer characteristic (Figure 9B) is governed by the noise figure of the receiver, which is limited by the insertion loss of the front end SAW filter, and the bandwidth of the 10.7MHz ceramic filter. 3. Reduction in conversion gain and increase in receiver current consumption coincides with lift-off of the AGC control line (Pin 12). Action of the AGC applies additional mixer booster current to improve the linearity of the mixer at high signal levels. 15 KESRX04 Figure 10 Applications KESRX04 PCB with 10.7MHz IF Ceramic filter (PCB size = 22mm x 40mm) 16 RF_IN C19 L4 VCC 2 1 I/P(GND) I/P C26 B3550 C25 8 GND 3 7 O/P O/P(GND) GND 4 GND GND GND RF_IN GND 1 2 3 5 6 VCC I/P GND O/P CF1 C28 VCC DATA PD J1 C22 C16 L3 C29 R9 L1 C4 R6 C8 C9 VCC C3 1 DATA R7 14 13 12 11 10 9 8 7 6 5 4 3 2 DATAOP PEAK AGC RFIN VEERF RFOUT MIXIP VCCRF IFOUT VCC IFDC2 IFIN IFDC1 IFLT1 DSN LF VEE VCCO2 VCO1 DF2 DF1 DF0 XTAL2 XTAL1 PD DETB RSSI IFLT2 KESRX04 L5 15 16 17 18 19 20 21 22 23 24 25 26 27 28 L2 C13 C18 C11 C5 C14 C10 C17 R3 D1 R10 C2 R11 VCC R1 R4 XTAL1 Figure 11 Applications circuits diagram for KESRX04 with 10.7MHz IF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C7 C6 C12 C1 C23 R2 C15 C20 R_ON VCC PD KESRX04 17 KESRX04 Component list for applications circuit for KESRX04 with 10.7MHz IF (Figure 11) (Not to be used for Test Fixture Circuit Figure 12) Test fixture component values can be supplied on request. Identity 433.92 MHz. + SAW Part No Tolerance C1 150pF GRM39C0G151J Murata 0603 C2 270pF GRM39C0G271J Murata 0603 C3 10nF GRM39X7R103K Murata 0603 C4 10nF GRM39X7R103K Murata 0603 C5 270pF GRM39SL271J Murata 0603 0603 Size C6 270pF GRM39SL271J Murata C7** 47pF GRM39COG470G Murata 0603 C8 10nF GRM39Y5V103K Murata 0603 C9 56pF GRM39COG560J Murata 0603 C10 470nF GRM40Y5V474Z Murata 0805 C11** 12pF GRM39COG120J Murata 0603 C12 1.5nF GRM39X7R152K Murata 0603 C13 18pF GRM39COG180J Murata 0603 C14 18pF GRM39COG180J Murata 0603 C15 82pF GRM39COG820J Murata 0603 C16* N/A N/A N/A N/A C17 N/A N/A N/A N/A C18** 12pF GRM39COG120J Murata 0603 C19* 6.8pF GRM39COG6R8C Murata 0603 C20 N/A N/A N/A N/A C22 1uF GRM40Y5V105Z Murata 0805 C23 82pF GRM39COG820J Murata 0603 C25 82pF GRM39COG820J Murata 0603 C26 1uF GRM40Y5V105Z Murata 0805 C28 1uF GRM40Y5V105Z Murata 0805 C29 82pF GRM39COG820J Murata 0603 R1 4.7K N/A Rohm 0603 R2 10K N/A Rohm 0603 R3 N/A N/A N/A N/A R4 4.7K N/A Rohm 0603 R6 100K N/A Rohm 0805 R7 100K N/A Rohm 0603 R9** 360 N/A Rohm 0603 R10 100K N/A Rohm 0603 0603 R11 100K N/A Rohm R_ON N/A N/A N/A D1 BB833 4 to 10pF Siemens N/A SOD323 CF1** SFE10.7MA26 3dB BW = 470KHz. Murata Radial B355* B3550 3dB BW = 750KHz. Siemens 5mm2 L1* 39nH LL2012-F39NJ TOKO 2012 L2* 27nH LL2012-F27NJ TOKO 2012 L3* 100nH LL1608-FHR10J TOKO 1608 L4* 33nH LL2012-F33NJ TOKO 2012 L5** 4.7uH FLU25204R7J TOKO 2520 XTAL1* 6.61281MHz. +/-100 PPM Kinseki / Quartz Tek KESRX04 KESRX04 KESRX04 *Adjust for alternative centre frequency. **Adjust for alternative IF frequency / ceramic filter. AGC time constant (C8) optimised for minimum settling time (time to good) data N/A. Not Applicable 18 Supplier Zarlink Semiconductor HC49/4H QP28 KESRX04 C7 L5 CF1 C4 KESRX04 C3 I/P GND O/P 1 2 IFDC1 IFLT2 RSSI 28 27 1 2 3 VCC R9 IFLT1 3 IFIN DETB 26 C10 Power Down Input 4 C25 C26 IFDC2 PD 25 C14 VCC 5 6 VCC XTAL1 IFOUT XTAL2 VCCRF DF0 MIXIP DF1 24 23 C23 C13 VCC 7 R11 22 R10 C28 C29 8 L1 C9 C6 Reference Input 21 C5 9 10 RF Input (50 Ohm source) C15 RFOUT DF2 VEERF VCO1 20 R4 19 C16 C11 11 RFIN VCCO2 AGC VEE 18 D1 L2 C18 12 R1 C12 17 C8 13 14 PEAK DATAOP LF DSN 16 15 C1 C22 R2 R7 R6 Data Output Figure 12 Production test circuit for KESRX04 with 10.7MHz IF 19 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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