AD ADV3226

750 MHz, 16 × 16
Analog Crosspoint Switch
ADV3226/ADV3227
FEATURES
SER/PAR D0 D1 D2 D3 D4
CLK
GENERAL DESCRIPTION
The ADV3226/ADV3227 are high speed 16 × 16 analog crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater
than 750 MHz and channel switch times of less than 20 ns with
1% settling.
The ADV3226/ADV3227 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs to prevent off channels from loading the
output bus. The ADV3226 has a gain of +1 and the ADV3227
has a gain of +2. They both operate on voltage supplies of ±5 V
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
DATAIN
UPDATE
PARALLEL LATCH
RESET
80
SET INDIVIDUAL
OR RESET ALL
OUTPUTS TO OFF
DECODE
16 × 5:16 DECODERS
ADV3226/
ADV3227
256
16
OUTPUT
BUFFER
G = +1,
G = +2
SWITCH
MATRIX
08653-001
16
INPUTS
DATAOUT
80
CE
APPLICATIONS
Routing of high speed signals including
Video (NTSC, PAL, S, SECAM, YUV, RGB)
Compressed video (MPEG, wavelet)
3-level digital video (HDB3)
Data communications
Telecommunications
A0
A1
A2
A3
16
OUTPUTS
16 × 16 high speed, nonblocking switch array
Pinout and functionally equivalent to the AD8114/AD8115
Complete solution
Buffered inputs
Programmable high impedance outputs
16 output amplifiers, G = +1 (ADV3226), G = +2 (ADV3227)
Drives 150 Ω loads
Operates on ±5 V supplies
Low power: 1.3 W
Excellent ac performance
−3 dB bandwidth
200 mV p-p: 820 MHz (ADV3226), 750 MHz (ADV3227)
2 V p-p: 600 MHz (ADV3226), 750 MHz (ADV3227)
Slew rate: 2150 V/μs (ADV3226), 2950 V/μs (ADV3227)
Serial or parallel programming of switch array
100-lead LFCSP (12 mm × 12 mm)
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
while consuming only 118 mA (ADV3226) and 133 mA
(ADV3227) of idle current. Channel switching is performed via
a serial digital control that can accommodate daisy chaining of
several devices or via a parallel control to allow updating of an
individual output without reprogramming the entire array.
The ADV3226/ADV3227 are available in the 100-lead LFCSP
package over the extended industrial temperature range of
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADV3226/ADV3227
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................7
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................8
General Description ......................................................................... 1
Truth Table and Logic Diagram ............................................... 10
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ............................................11
Revision History ............................................................................... 2
Circuit Diagrams ............................................................................ 20
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 21
Timing Characteristics (Serial) .................................................. 5
Applications Information .......................................................... 21
Logic Levels ................................................................................... 5
Power-On Reset .......................................................................... 22
Timing Characteristics (Parallel) ............................................... 6
Gain Selection ............................................................................. 22
Absolute Maximum Ratings............................................................ 7
Creating Larger Crosspoint Arrays .......................................... 23
Thermal Resistance ...................................................................... 7
Outline Dimensions ....................................................................... 24
Power Dissipation ......................................................................... 7
Ordering Guide .......................................................................... 24
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADV3226/ADV3227
SPECIFICATIONS
VS = ±5 V, TA = +25°C, RL = 150 Ω, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Flatness
Propagation Delay
Settling Time
Slew Rate
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
Off Isolation, Input to Output
IMD2
IMD3
Output 1 dB Compression Point
Input Voltage Noise
DC PERFORMANCE
Gain Error
Gain Matching
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Resistance
Output Disabled Capacitance
Output Leakage Current
Output Voltage Range
INPUT CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage Drift
Input Voltage Range
Input Capacitance
Input Resistance
Input Bias Current
Test Conditions/Comments
Min
ADV3226
Typ
Max
Min
ADV3227
Typ
Max
Unit
200 mV p-p
2 V p-p
0.1 dB, 2 V p-p
0.5 dB, 2 V p-p, CL = 2.2 pF
2 V p-p
1%, 2 V step
2 V step, peak
820
600
130
400
0.6
3
2150
750
750
60
200
0.6
3
2950
MHz
MHz
MHz
MHz
ns
ns
V/μs
NTSC or PAL
NTSC or PAL
f = 100 MHz
f = 5 MHz
f = 100 MHz, one channel
f = 100 MHz, RL = 100 Ω
f = 500 MHz, RL = 100 Ω
f = 100 MHz, RL = 100 Ω
f = 500 MHz, RL = 100 Ω
f = 100 MHz, RL = 100 Ω
f = 500 MHz, RL = 100 Ω
0.01 MHz to 50 MHz
0.04
0.01
−45
−75
−80
0.02
0.01
−35
−60
−75
47
22
42
14
18
9
16
%
Degrees
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dBm
nV/√Hz
16
0.1
0.8
16
%
%
ppm/°C
0.2
10
2.7
1
±3
±2.8
55
0.2
5
2.7
1
±3
±2.8
55
Ω
MΩ
pF
μA
V
V
mA
±5
8
±3
±3
2.1
2
1
±5
8
±1.5
±1.5
2.1
2
1
mV
μV/°C
V
V
pF
MΩ
μA
Channel-to-channel
DC, enabled
DC, disabled
Output disabled
No load
RL = 150 Ω
Short-circuit current
Worst case (all configurations)
No load
RL = 150 Ω
Any switch configuration
Any switch configuration
Rev. 0 | Page 3 of 24
1.0
1.0
0.4
1.5
1.5
ADV3226/ADV3227
Parameter
SWITCHING CHARACTERISTICS
Enable/Disable Time
Switching Time, 2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
Supply Current
Supply Voltage Range
PSRR
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Test Conditions/Comments
Min
ADV3226
Typ
Max
Min
ADV3227
Typ
Max
Unit
50% UPDATE to 1% settling
20
20
ns
50% UPDATE to 1% settling
20
20
ns
40
65
mV p-p
AVCC, outputs enabled, no load
AVCC, outputs disabled
AVEE, outputs enabled, no load
AVEE, outputs disabled
DVCC, outputs enabled, no load
±4.5
DC to 50 kHz, AVCC, AVEE
f = 100 kHz, AVCC, AVEE
f = 10 MHz, AVCC
f = 10 MHz, AVEE
f = 100 kHz, DVCC
Operating (still air)
Operating (still air)
110
25
110
25
8
±5
>60
55
45
35
90
−40
26
Rev. 0 | Page 4 of 24
130
35
130
35
10
±5.5
±4.5
+85
−40
125
25
125
25
8
±5
>60
60
40
55
80
26
140
35
140
35
10
±5.5
mA
mA
mA
mA
mA
V
dB
dB
dB
dB
dB
+85
°C
°C/W
ADV3226/ADV3227
TIMING CHARACTERISTICS (SERIAL)
Table 2.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
Symbol
t1
t2
t3
t4
t5
Min
10
10
10
10
10
UPDATE Pulse Width
t6
10
CLK to DATAOUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
t7
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
50
ns
ns
20
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
1.6
RESET Time
30
μs
ns
50
ns
Timing Diagram—Serial Mode
t2
t4
1
CLK
0
t1
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t3
1
DATAIN
OUT07 (D4)
OUT07 (D3)
OUT00 (D0)
0
t5
t6
1 = LATCHED
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t7
08653-002
UPDATE
0 = TRANSPARENT
DATAOUT
Figure 2. Timing Diagram, Serial Mode
LOGIC LEVELS
Table 3. Logic Levels
VIH
VIL
RESET, SER/PAR,
CLK, DATAIN,
CE, UPDATE
RESET,SER/PAR,
CLK, DATAIN,
CE, UPDATE
2.0 V min
0.8 V max
VOH
DATAOUT
VOL
DATAOUT
IIH
IIL
SER/PAR,
CLK, DATAIN,
CE, UPDATE
SER/PAR, CLK,
DATAIN, CE,
UPDATE
2.4 V min
0.4 V max
2 μA max
2 μA max
Rev. 0 | Page 5 of 24
IIH
RESET
IIL
RESET
IOH
DATAOUT
IOL
DATAOUT
2 μA max
300 μA max
3 mA min
1 mA min
ADV3226/ADV3227
TIMING CHARACTERISTICS (PARALLEL)
Table 4.
Parameter
Parallel Data Setup Time
Address Setup Time
CLK Pulse Width
Parallel Data Hold Time
Address Hold Time
CLK Pulse Separation
UPDATE Pulse Width
Symbol
t1d
t1a
t2
t3d
t3a
t4
t5
Min
10
10
10
10
10
20
10
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
50
CLK, UPDATE Rise and Fall Times
ns
30
RESET Time
ns
Timing Diagram—Parallel Mode
1
CLK
0
1
A0 TO A3
0
1
D0 TO D4
0
t2
t4
t1a
t3a
t1d
t3d
t5
08653-003
1 = LATCHED
UPDATE
0 = TRANSPARENT
Figure 3. Timing Diagram, Parallel Mode
Rev. 0 | Page 6 of 24
ADV3226/ADV3227
ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION
Table 5.
The ADV3226/ADV3227 operate with ±5 V supplies and can
drive loads down to 100 Ω, resulting in a wide range of possible
power dissipations. For this reason, extra care must be taken
when derating the operating conditions based on ambient
temperature.
Rating
11 V
6V
±0.5 V
±0.5 V
6V
AVEE < VIN < AVCC
DGND < DIN < DVCC
AVEE < VIN < AVCC
AVEE < VOUT < AVCC
Momentary
Internally limited to 55 mA
−65°C to +125°C
−40°C to +85°C
150°C
300°C
Packaged in the 100-lead LFCSP, the ADV3226/ADV3227
junction-to-ambient thermal impedance (θJA) is 26°C/W.
For long-term reliability, the maximum allowed junction
temperature of the die should not exceed 125°C; even
temporarily exceeding this limit can cause a shift in parametric
performance due to a change in stresses exerted on the die by
the package. Exceeding a junction temperature of 150°C for an
extended period can result in device failure. In Figure 4, the
curve shows the range of allowed internal die power dissipation
that meets these conditions over the −40°C to +85°C ambient
temperature range. When using Figure 4, do not include the
external load power in the maximum power calculation, but do
include the load current dropped on the die output transistors.
6
25
35
45
55
65
AMBIENT TEMPERATURE (°C)
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
θJB
9.5
ψJT
0.2
ψJB
8.9
75
85
Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature
ESD CAUTION
Table 6. Thermal Resistance
θJC
2.56
3
2
15
THERMAL RESISTANCE
θJA
26
4
08653-004
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Package Type
100-Lead LFCSP
TJ = 150°C
5
MAXIMUM POWER (W)
Parameter
Analog Supply Voltage (AVCC − AVEE)
Digital Supply Voltage (DVCC − DGND)
Supply Potential Difference
(AVCC − DVCC)
Ground Potential Difference
(AGND − DGND)
Maximum Potential Difference
(DVCC − AVEE)
Analog Input Voltage
Digital Input Voltage
Exposed Paddle Voltage
Output Voltage (Disabled Analog
Output)
Output Short-Circuit
Duration
Current
Temperature
Storage Temperature Range
Operating Temperature Range
Junction Temperature
Lead Temperature (Soldering,
10 sec)
Unit
°C/W
Rev. 0 | Page 7 of 24
ADV3226/ADV3227
CE
DATAOUT
CLK
DATAIN
UPDATE
SER/PAR
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
D0
D1
D2
D3
D4
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
DVCC
74
DGND
DVCC
1
DGND
2
AGND
3
73
AGND
IN08
4
72
IN07
AGND
PIN 1
AGND
5
71
IN09
6
70
IN06
AGND
7
69
AGND
IN05
IN10
8
68
AGND
9
67
AGND
IN11
10
66
IN04
AGND
11
IN12
12
AGND
ADV3226/ADV3227
TOP VIEW
(Not to Scale)
65
AGND
64
IN03
13
63
AGND
IN13
14
62
IN02
AGND
15
61
AGND
IN14
16
60
IN01
AGND
AGND
17
59
IN15
18
58
IN00
AGND
19
57
AGND
AVEE
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
OUT09
AVEE
OUT08
AVCC
OUT07
AVEE
OUT06
AVCC
OUT05
AVEE
OUT04
AVCC
OUT03
AVEE
OUT02
50
34
AVCC
AVCC
33
OUT01
OUT10
51
32
25
AVEE
AVEE
OUT14
31
OUT00
52
OUT11
53
24
30
23
AVEE
AVCC
OUT15
29
AVCC
OUT12
54
28
22
AVEE
AVCC
AVCC
27
55
26
56
21
AVCC
20
OUT13
AVEE
AVCC
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB
GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS.
08653-005
RESET
100
99
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
DVCC
DGND
AGND
IN08
AGND
IN09
AGND
IN10
AGND
IN11
AGND
IN12
AGND
IN13
AGND
IN14
Description
Digital Positive Power Supply.
Digital Ground.
Analog Ground.
Input Number 8.
Analog Ground.
Input Number 9.
Analog Ground.
Input Number 10.
Analog Ground.
Input Number 11.
Analog Ground.
Input Number 12.
Analog Ground.
Input Number 13.
Analog Ground.
Input Number 14.
Pin No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Rev. 0 | Page 8 of 24
Mnemonic
AGND
IN15
AGND
AVEE
AVCC
AVCC
OUT15
AVEE
OUT14
AVCC
OUT13
AVEE
OUT12
AVCC
OUT11
AVEE
Description
Analog Ground.
Input Number 15.
Analog Ground.
Analog Negative Supply.
Analog Positive Supply
Analog Positive Supply.
Output Number 15.
Analog Negative Supply.
Output Number 14.
Analog Positive Supply.
Output Number 13.
Analog Negative Supply.
Output Number 12.
Analog Positive Supply.
Output Number 11.
Analog Negative Supply.
ADV3226/ADV3227
Pin No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Mnemonic
OUT10
AVCC
OUT09
AVEE
OUT08
AVCC
OUT07
AVEE
OUT06
AVCC
OUT05
AVEE
OUT04
AVCC
OUT03
AVEE
OUT02
AVCC
OUT01
AVEE
OUT00
AVCC
AVCC
AVEE
AGND
IN00
AGND
IN01
AGND
IN02
AGND
IN03
AGND
IN04
AGND
Description
Output Number 10.
Analog Positive Supply.
Output Number 9.
Analog Negative Supply.
Output Number 8.
Analog Positive Supply.
Output Number 7.
Analog Negative Supply.
Output Number 6.
Analog Positive Supply.
Output Number 5.
Analog Negative Supply.
Output Number 4.
Analog Positive Supply.
Output Number 3.
Analog Negative Supply.
Output Number 2.
Analog Positive Supply.
Output Number 1.
Analog Negative Supply.
Output Number 0.
Analog Positive Supply.
Analog Positive Supply.
Analog Negative Supply.
Analog Ground.
Input Number 0.
Analog Ground.
Input Number 1.
Analog Ground.
Input Number 2.
Analog Ground.
Input Number 3.
Analog Ground.
Input Number 4.
Analog Ground.
Pin No.
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85 to 93
94
Mnemonic
IN05
AGND
IN06
AGND
IN07
AGND
DGND
DVCC
D4
D3
D2
D1
D0
A3
A2
A1
A0
NC
SER/PAR
Description
Input Number 5.
Analog Ground.
Input Number 6.
Analog Ground.
Input Number 7.
Analog Ground.
Digital Ground.
Digital Positive Power Supply.
Parallel Data Input, Output Enable.
Parallel Data Input.
Parallel Data Input.
Parallel Data Input.
Parallel Data Input.
Parallel Data Input.
Parallel Data Input.
Parallel Data Input.
Parallel Data Input.
No Connect.
Serial/Parallel Mode Select (Control Pin).
95
UPDATE
Second Rank Write Strobe (Control Pin).
96
97
DATAIN
CLK
98
99
DATAOUT
CE
Serial Data In (Control Pin).
Serial Data Clock. Parallel 1st rank latch
enable (control pin).
Serial Data Out.
Chip Enable (Control Pin).
100
RESET
Second Rank Reset (Control Pin).
N/A 1
EP
Exposed Paddle. The exposed metal
paddle on the bottom of the LFCSP
package must be soldered to the PCB
ground for proper heat dissipation and
for noise and mechanical strength
benefits.
1
N/A means not applicable.
Rev. 0 | Page 9 of 24
ADV3226/ADV3227
TRUTH TABLE AND LOGIC DIAGRAM
Table 8. Operation Truth Table 1
CE
UPDATE
1
0
X
X
0
CLK
X
DATAIN
X
DataI 2
DATAOUT
X
DataI-80
X
0
D0…D4
0
0
X
X
N/A 3 in
parallel
mode 4
X
X
X
X
X
X
RESET
SER/PAR
X
X
X
0
X
1
1
X
0
X
Description
No change in logic.
The data on the serial DATAIN line is loaded into the serial register.
The first bit clocked into the serial register appears at DATAOUT 80
clock cycles later.
The data on the parallel data lines, D0 to D4, are loaded into the
80-bit serial shift register location addressed at A0 to A3.
Data in the 80-bit shift register transfers into the parallel latches
that control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Second rank
latches are cleared. Remainder of logic is unchanged.
1
X is don’t care.
DataI: serial data.
3
N/A means not applicable.
4
DATAOUT remains active in parallel mode and always reflects the state of the MSB of the serial shift register.
2
PARALLEL
DATA
(OUTPUT
ENABLE)
D0
D1
D2
D3
D4
SER/PAR
S
D1
Q
D0
DATA IN
(SERIAL)
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
S
D1
S
D1
Q D Q
D0
CLK
D Q
CLK
S
D1
D Q
Q
D0
S
D1
Q D Q
D0 CLK
CLK
Q
D0
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
S
D1
D Q
Q
D0
CLK
D Q
DATA
OUT
CLK
CLK
CE
UPDATE
OUTPUT
ADDRESS
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
A1
OUT5 EN
A2
A3
4 TO 16 DECODER
A0
OUT6 EN
OUT7 EN
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
LE D
OUT0
B0
OUT0
B1
OUT0
B2
OUT0
B3
OUT0
EN
OUT1
B0
OUT14
EN
OUT15
B0
OUT15
B1
OUT15
B2
OUT15
B3
OUT15
EN
Q
Q
Q
Q
Q
CLR Q
CLR Q
Q
Q
Q
Q
CLR Q
RESET
(OUTPUT ENABLE)
SWITCH MATRIX
Figure 6. Logic Diagram
Rev. 0 | Page 10 of 24
16
OUTPUT ENABLE
08653-006
DECODE
256
ADV3226/ADV3227
TYPICAL PERFORMANCE CHARACTERISTICS
0
–1
–2
GAIN (dB)
–4
–5
–6
–7
–8
1
10
100
10k
1k
FREQUENCY (MHz)
0
–1
–2
GAIN (dB)
GAIN (dB)
–3
–4
–5
–6
–7
–8
10
100
1k
10k
FREQUENCY (MHz)
08653-015
RL = 150Ω
VOUT = 2V p-p
1
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
10k
RL = 150Ω
VOUT = 2V p-p
1
10
100
1k
10k
12
10.4pF
10.4pF
10
5.0pF
5.0pF
8
6
1
2.2pF
–1
–2
–3
2.2pF
4
GAIN (dB)
0
GAIN (dB)
1k
Figure 11. ADV3227 Large Signal Frequency Response
2
1.2pF
0pF
–4
–5
1.2pF
2
0pF
0
–2
–4
–6
–7
–8
–9
–6
RL = 150Ω
VOUT = 200mV p-p
1
10
RL = 150Ω
VOUT = 200mV p-p
–8
100
FREQUENCY (MHz)
1k
10k
08653-016
–10
100
FREQUENCY (MHz)
Figure 8. ADV3226 Large Signal Frequency Response
6
5
4
3
10
Figure 10. ADV3227 Small Signal Frequency Response
1
–10
1
FREQUENCY (MHz)
Figure 7. ADV3226 Small Signal Frequency Response
–9
RL = 150Ω
VOUT = 200mV p-p
08653-018
–10
08653-014
RL = 150Ω
VOUT = 200mV p-p
–9
Figure 9. ADV3226 Small Signal Frequency Response with Capacitive Loads
Rev. 0 | Page 11 of 24
–10
1
10
100
1k
10k
FREQUENCY (MHz)
Figure 12. ADV3227 Small Signal Frequency Response, RL = 150 Ω
08653-019
GAIN (dB)
–3
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
08653-017
1
ADV3226/ADV3227
4
14
3
12
10.4pF
2
5.0pF
10
2.2pF
8
1
0
GAIN (dB)
2.2pF
–3
0pF
–4
4
1.2pF
2
0pF
0
–2
–6
–4
–7
–6
RL = 150Ω
VOUT = 2V p-p
1
RL = 150Ω
VOUT = 2V p-p
–8
10
100
1k
10k
FREQUENCY (MHz)
–10
08653-020
–9
Figure 13. ADV3226 Large Signal Frequency Response with Capacitive Loads
0.10
0.10
0.05
0.05
VOUT (V)
INPUT SIGNAL
OUTPUT SIGNAL
INPUT SIGNAL
2
4
6
8
10
12
14
16
18
20
TIME (ns)
–0.15
08653-021
0
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
08653-024
RL = 150Ω
VOUT = 200mV p-p
RL = 150Ω
VOUT = 200mV p-p
Figure 17. ADV3227 Small Signal Pulse Response
Figure 14. ADV3226 Small Signal Pulse Response
1.5
1.5
OUTPUT SIGNAL
1.0
1.0
0.5
VOUT (V)
0.5
0
INPUT SIGNAL
–0.5
0
OUTPUT SIGNAL
INPUT SIGNAL
–0.5
–1.0
–1.0
RL = 150Ω
VOUT = 2V p-p
RL = 150Ω
VOUT = 2V p-p
0
2
4
6
8
10
12
14
16
18
TIME (ns)
20
08653-022
VOUT (V)
10k
–0.10
–0.10
–1.5
1k
0
–0.05
–0.05
–0.15
100
Figure 16. ADV3227 Large Signal Frequency Response with Capacitive Loads
0.15
OUTPUT SIGNAL
10
FREQUENCY (MHz)
0.15
0
1
08653-023
–8
Figure 15. ADV3226 Large Signal Pulse Response
–1.5
0
2
4
6
8
10
12
14
16
18
TIME (ns)
Figure 18. ADV3227 Large Signal Pulse Response
Rev. 0 | Page 12 of 24
20
08653-025
GAIN (dB)
1.2pF
–2
–5
VOUT (V)
5.0pF
6
–1
–10
10.4pF
ADV3226/ADV3227
1.0
2000
0.5
1500
0
1000
1500
0
1000
–0.5
500
0
–1.0
0
–500
–1.5
–500
–0.5
500
–1.0
–1.5
–2.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–1000
5.0
–2.0
08653-026
VOUT (V)
2000
2500
PULSE: RISING EDGE
TIME (ns)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
SLEW RATE (V/µs)
PULSE: RISING EDGE
0.5
1.5
VOUT (V)
1.0
SLEW RATE
2500
SLEW RATE (V/µs)
SLEW RATE
1.5
3000
2.0
3000
–1000
5.0
08653-122
2.0
TIME (ns)
Figure 19. ADV3226 Rising Edge Slew Rate
Figure 22. ADV3227 Rising Edge Slew Rate
500
2.0
500
1.5
0
1.5
0
1.0
–500
1.0
–500
0.5
–1000
0.5
–1000
0
–1500
2.0
–2500
–1.0
–1.5
–3000
–1.5
–3500
5.0
–2.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
TIME (ns)
–3000
0
0.5
1.5
30
1.0
OUTPUT SIGNAL
10
0
0
–0.5
1.5
2.0
2.5
3.0
TIME (ns)
3.5
4.0
4.5
–3500
5.0
–20
4.0
30
OUTPUT–INPUT
20
OUTPUT SIGNAL
10
0
0
–1.0
–10
INPUT SIGNAL
PROPAGATION DELAY NOT SHOWN
08653-027
1.0
3.5
40
PROPAGATION DELAY NOT SHOWN
0.5
3.0
–0.5
–10
INPUT SIGNAL
0
2.5
0.5
VOUT (V)
20
0.5
VOUT (V)
40
OUTPUT ERROR (%)
OUTPUT–INPUT
–1.5
–1.0 –0.5
2.0
Figure 23. ADV3227 Falling Edge Slew Rate
1.5
–1.0
1.5
TIME (ns)
Figure 20. ADV3226 Falling Edge Slew Rate
1.0
1.0
OUTPUT ERROR (%)
0.5
–2500
SLEW RATE
–1.5
–1.0 –0.5
Figure 21. ADV3226 Settling Time
0
0.5
1.0
1.5
2.0
2.5
3.0
TIME (ns)
Figure 24. ADV3227 Settling Time
Rev. 0 | Page 13 of 24
3.5
–20
4.0
08653-030
0
–2000
–0.5
–1.0
–2.0
–1500
PULSE: FALLING EDGE
SLEW RATE (V/µs)
VOUT (V)
0
08653-029
–2000
SLEW RATE (V/µs)
PULSE: FALLING EDGE
–0.5
08653-120
VOUT (V)
SLEW RATE
ADV3226/ADV3227
20
20
10
0
0
–10
VEE AGGRESSOR
PSR (dB)
PSR (dB)
–20
–30
–40
–50
–20
VCC AGGRESSOR
–40
VCC AGGRESSOR
VEE AGGRESSOR
–60
–60
–70
1
10
100
1k
FREQUENCY (MHz)
–80
0.1
08653-028
–90
0.1
100
1k
Figure 28. ADV3227 Power Supply Rejection
200
200
180
180
NOISE SPECTRAL DENSITY (nV/ Hz)
160
140
120
100
80
60
40
20
160
140
120
100
80
60
40
10k
100k
1M
10M
100M
FREQUENCY (Hz)
0
1k
08653-032
0
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 26. ADV3226 Output Noise, 100 Ω Load
08653-035
20
Figure 29. ADV3227 Output Noise, 100 Ω Load
0
0
–10
–10
–20
–20
ISOLATION (dB)
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–80
–80
–100
1
10
100
1k
FREQUENCY (MHz)
10k
08653-033
–90
Figure 27. ADV3226 Off Isolation
–90
1
10
100
1k
FREQUENCY (MHz)
Figure 30. ADV3227 Off Isolation
Rev. 0 | Page 14 of 24
10k
08653-036
NOISE SPECTRAL DENSITY (nV/ Hz)
10
FREQUENCY (MHz)
Figure 25. ADV3226 Power Supply Rejection
ISOLATION (dB)
1
08653-031
–80
ADV3226/ADV3227
–10
–20
–30
–30
CROSSTALK (dB)
–20
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
1
10
1k
100
FREQUENCY (MHz)
–90
1
10
100
1k
FREQUENCY (MHz)
Figure 31. ADV3226 Crosstalk, One Adjacent Channel, RTO
0
IN3–OUT3: ENABLED CHANNEL
IN2 ACTIVATED
–10
08653-034
CROSSTALK (dB)
0
IN3–OUT3: ENABLED CHANNEL
IN2 ACTIVATED
08653-037
0
Figure 34. ADV3227 Crosstalk, One Adjacent Channel, RTO
20
IN3–OUT3: ENABLED CHANNEL
IN3–OUT3: ENABLED CHANNEL
–10
0
–30
CROSSTALK (dB)
CROSSTALK (dB)
–20
–40
–50
–60
–20
–40
–60
–70
–80
1
10
1k
100
FREQUENCY (MHz)
–100
08653-038
–90
1
1k
Figure 35. ADV3227 Crosstalk, All Hostile, RTO
1M
100k
100k
10k
10k
IMPEDANCE (Ω)
1M
1k
100
1k
100
10
0.1
1
10
100
FREQUENCY (MHz)
1k
10k
Figure 33. ADV3226 Input Impedance
1
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 36. ADV3227 Input Impedance
Rev. 0 | Page 15 of 24
1k
10k
08653-042
10
08653-039
IMPEDANCE (Ω)
100
FREQUENCY (MHz)
Figure 32. ADV3226 Crosstalk, All Hostile, RTO
1
0.01
10
08653-041
–80
1M
1M
100k
100k
10k
10k
IMPEDANCE (Ω)
1k
100
1k
100
10
100
1k
10k
FREQUENCY (MHz)
1
0.1
10
10
IMPEDANCE (Ω)
IMPEDANCE (Ω)
100
1
100
1k
FREQUENCY (MHz)
0.1
0.1
1.5
1.5
100
1k
3.5
UPDATE
3.0
VOUT RISING EDGE
1.0
0.5
2.0
0.5
2.0
0
1.5
0
1.5
–0.5
1.0
VOUT FALLING EDGE
–1.0
–1.5
–2.0
–10
0
10
20
TIME (ns)
VOUT (V)
UPDATE (V)
2.5
–0.5
0.5
–1.0
0
–1.5
–0.5
30
08653-045
VOUT (V)
1.0
10
2.0
3.0
VOUT RISING EDGE
1
Figure 41. ADV3227 Output Impedance, Enabled
3.5
UPDATE
10k
FREQUENCY (MHz)
Figure 38. ADV3226 Output Impedance, Enabled
2.0
1k
1
08653-044
10
100
Figure 40. ADV3227 Output Impedance, Disabled
100
1
10
FREQUENCY (MHz)
Figure 37. ADV3226 Output Impedance, Disabled
0.1
0.1
1
08653-047
10
–2.0
–10
Figure 39. ADV3226 Switching Time
1.0
VOUT FALLING EDGE
0.5
0
0
10
20
TIME (ns)
Figure 42. ADV3227 Switching Time
Rev. 0 | Page 16 of 24
2.5
UPDATE (V)
1
08653-040
1
0.1
08653-043
10
–0.5
30
08653-142
IMPEDANCE (Ω)
ADV3226/ADV3227
ADV3226/ADV3227
20
50
10
40
30
0
VOUT (mV)
–20
–30
10
0
–10
–40
–20
10
15
20
25
30
35
40
45
50
TIME (ns)
–30
0
5
10
40
45
50
0.5
2.0
0
1.5
1.0
–2
20
3.0
VOUT RISING EDGE
2.0
1.5
VOUT FALLING EDGE
3.5
UPDATE
1.0
VOUT (V)
0
10
35
2.5
UPDATE (V)
VOUT RISING EDGE
–0.5
0.5
–1.0
0
–1.5
–0.5
–2.0
–10
08653-050
VOUT (V)
1.5
3.0
2
0
30
2.0
3.5
UPDATE
–3
–10
25
Figure 46. ADV3227 Switching Glitch
3
–1
20
TIME (ns)
Figure 43. ADV3226 Switching Glitch
1
15
08653-049
5
30
TIME (ns)
2.5
1.0
VOUT FALLING EDGE
UPDATE (V)
0
08653-046
–50
0.5
0
0
10
–0.5
30
20
08653-048
VOUT (mV)
20
–10
TIME (ns)
Figure 47. ADV3227 Enable Time
Figure 44. ADV3226 Enable Time
0.025
0.040
DIFFERENTIAL GAIN ERROR (%)
0.030
0.025
0.020
0.015
0.010
0.005
0.020
0.015
0.010
0.005
0
–0.005
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
INPUT DC OFFSET (V)
0.6
0.8
–0.005
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
INPUT DC OFFSET (V)
Figure 48. ADV3227 Differential Gain Error
Figure 45. ADV3226 Differential Gain Error
Rev. 0 | Page 17 of 24
0.6
0.8
08653-054
0
08653-051
DIFFERENTIAL GAIN ERROR (%)
0.035
ADV3226/ADV3227
0.0015
0.0010
0.0005
0
–0.0005
–0.0010
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
INPUT DC OFFSET (V)
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.8
6
2
0.2
0.4
0.6
0.8
VIN = ±4.65V p-p
2
VOLTAGE (V)
1
0
–1
0
–2
–2
VOUT @ VIN = ±4.65V p-p
–3
–5
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
–6
08653-056
–4
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
08653-059
–4
VOUT @ VIN = ±4.55V p-p
Figure 53. ADV3227 Overdrive Recovery
Figure 50. ADV3226 Overdrive Recovery
60
THIRD-ORDER INTERCEPT (dBm)
25
20
15
10
5
100
INPUT FREQUENCY (MHz)
1k
40
30
20
10
0
10
08653-057
0
10
50
100
INPUT FREQUENCY (MHz)
Figure 54. ADV3227 Third-Order Intercept, 100 Ω Load
Figure 51. ADV3227 1 dB Gain Compression, 100 Ω Load
Rev. 0 | Page 18 of 24
1k
08653-060
VOLTAGE (V)
0
4
3
1dB GAIN COMPRESSION (dBm)
–0.2
Figure 52. ADV3227 Differential Phase Error
VIN = ±4.55V p-p
4
–0.4
INPUT DC OFFSET (V)
Figure 49. ADV3226 Differential Phase Error
5
–0.6
08653-055
DIFFERENTIAL PHASE ERROR (Degrees)
0.008
08653-052
DIFFERENTIAL PHASE ERROR (Degrees)
0.0020
90
–20
80
–30
HARMONIC DISTORTION (dBc)
70
60
50
40
30
20
10
100
1k
INPUT FREQUENCY (MHz)
HD2, 10dBm
–40
HD2, 0dBm
–50
HD3, 0dBm
–60
–70
–80
HD3, 10dBm
–90
–100
–110
10
100
1k
INPUT FREQUENCY (MHz)
Figure 57. ADV3227 Harmonic Distortion (Input Referred),100 Ω Load
Figure 55. ADV3227 Second-Order Intercept, 100 Ω Load
140
120
80
60
40
20
0
–30 –25 –20 –15 –10 –5
0
5
10
15
20
25
30
COUNT
08653-156
NUMBER OF HITS
100
Figure 56. ADV3226 and ADV3227, Input VOS Distribution
Rev. 0 | Page 19 of 24
08653-061
0
10
08653-058
SECOND-ORDER INTERCEPT (dBm)
ADV3226/ADV3227
ADV3226/ADV3227
CIRCUIT DIAGRAMS
INx
A[3:0], CE, CLK,
D[4:0], DATAIN,
SER/PAR, UPDATE
1kΩ
08653-008
08653-007
2.1pF
DGND
Figure 58. Analog Input
Figure 61. Logic Input
OUTx
OUTx
Figure 59. Analog Output Enabled
Figure 62. Analog Output Disabled
DVCC
CLK, RESET,
SER/PAR, CE,
UPDATE,
DATAIN,
DATAOUT,
A[3:0]. D[4:0]
DVCC
20kΩ
AGND
AGND
DGND
08653-013
RESET
1kΩ
DGND
Figure 63. Reset Input
Figure 60. ESD Map
DVCC
DATAOUT
DGND
Figure 64. Logic Output
Rev. 0 | Page 20 of 24
08653-009
INx, OUTx
08653-012
AVCC
08653-011
08653-010
2.7pF
ADV3226/ADV3227
THEORY OF OPERATION
The ADV3226 (G = 1) and ADV3227 (G = 2) are crosspoint
arrays with 16 outputs, each of which can be connected to any
one of 16 inputs. Organized by output row, 16 switchable input
transconductance stages are connected to each output buffer to
form 16-to-1 multiplexers. There are 16 of these multiplexers,
each with its inputs wired in parallel, for a total array of 256 transconductance stages forming a multicast-capable crosspoint
switch. Each input is buffered and is not loaded by the outputs,
simplifying the construction of larger arrays using the ADV3226
or ADV3227 as a building block.
Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier. A mask programmable feedback
network sets the closed-loop signal gain. For theADV3226, this
gain is 1, and for the ADV3226, this gain is 2.
The output stage of the ADV3226 or ADV3227 is designed for
low differential gain and phase error when driving composite
video signals. It also provides slew current for a fast pulse response
when driving component video signals. Unlike many multiplexer
designs, these requirements are balanced such that large signal
bandwidth is very similar to small signal bandwidth. The design
load is150 Ω, but provisions are made to drive loads as low as
100 Ω when on-chip power dissipation limits are not exceeded.
The outputs of the ADV3226/ADV3227 can be disabled to minimize on-chip power dissipation. When disabled, there is no
feedback network loading the output. This high disabled output
impedance allows multiple ICs to be bussed together without
additional buffering. Care must be taken to reduce output capacitance, which results in more overshoot and frequency domain
peaking.
A series of internal amplifiers drives internal nodes such that a
wideband high impedance is presented at the disabled output,
even while the output bus is under large signal swings. To keep
these internal amplifiers in their linear range of operation when
the outputs are disabled and driven externally, do not allow the
voltage applied to them to exceed the valid output swing range
for the ADV3226/ADV3227. If the disabled outputs are left
floating, they may exhibit high enable glitches. If necessary,
the disabled output can be kept from drifting out of range by
applying an output load resistor to ground.
The connection of the ADV3226/ADV3227 is controlled by a
flexible TTL-compatible logic interface. Either parallel or serial
loading into a first rank of latches preprograms each output. A
global update signal moves the programming data into the second
rank of latches, simultaneously updating all outputs. In serial
mode, a serial out pin allows devices to be daisy-chained together
for single pin programming of multiple ICs. A power-on reset
pin is available to avoid bus conflicts by disabling all outputs.
This power-on reset clears the second rank of latches but does
not clear the first rank of latches. In serial mode, preprogramming
individual inputs is not possible and the entire shift register needs
to be flushed.
To easily interface to ground referenced video signals, the
ADV3226/ADV3227 operate on split ±5 V supplies. The logic
inputs and output run on a single +5 V supply, but the logic
inputs switch at approximately 1.6 V for compatibility with a
variety of logic families. The serial output buffer is a rail-to-rail
output stage with 5 mA of drive capability.
APPLICATIONS INFORMATION
The ADV3226/ADV3227 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 80 bits can be provided, which updates the entire
matrix each time the 80-bit word is shifted into the part. The
second option allows for changing the programming of a single
output via a parallel interface. The serial option requires fewer
signals but more time (clock cycles) for changing the programming, whereas the parallel programming technique requires
more signals but can change a single output at a time and requires
fewer clock cycles to complete the programming.
Serial Programming
The serial programming mode uses the CE, CLK, DATAIN,
UPDATE, and SER/PAR pins. The first step is to assert a low
on SER/PAR to enable the serial programming mode. CE for
the chip must be low to allow data to be clocked into the device.
The CE signal can be used to address an individual device when
devices are connected in parallel.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix, which causes
the matrix to try to update to every intermediate state as defined by
the shifting data.
The data at DATAIN is clocked in at every falling edge of CLK.
A total of 80 bits must be shifted in to complete the programming.
For each of the 16 outputs, there are four bits (D0 to D3) that determine the source of its input. The MSB is shifted in first. A fifth bit
(D4) precedes the four input select bits and determines the enabled
state of the output. If D4 is low (output disabled), the four associated bits (D0 to D3) do not matter because no input switches
to that output.
The most significant output address data is shifted in first, and
the remaining addresses follow in sequence until the least significant output address data is shifted in. At this point, UPDATE
can be taken low, which programs the device according to the
Rev. 0 | Page 21 of 24
ADV3226/ADV3227
data that was just shifted in. The update registers are asynchronous,
and when UPDATE is low (and CE is low), they are transparent.
If more than one ADV3226/ADV3227 device is to be serially
programmed in a system, the DATAOUT signal from one
device can be connected to the DATAIN of the next device to
form a serial chain. Connect all of the CLK, CE, UPDATE, and
SER/PAR pins in parallel and operate them as described previously
in this section. The serial data is input to the DATAIN pin of
the first device of the chain, and it ripples through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence (80 bits) is multiplied by the number
of devices in the chain.
Parallel Programming
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
Parallel programming allows the modification of a single output
at a time. Because this takes only one CLK/UPDATE cycle, significant time savings can be realized by using parallel programming.
An important consideration in using parallel programming is
that the RESET signal does not reset all registers in the ADV3226/
ADV3227. When taken low, the RESET signal sets each output
to the disabled state. This is helpful during power-up to ensure
that two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device
generally contain random data, even though the RESET signal
was asserted. If parallel programming is used to program one
output, that output is properly programmed, but the rest of the
device has a random program state depending on the internal
register content at power-up. Therefore, when using parallel
programming, it is essential that all outputs be programmed to
a desired state after power-up to ensure that the programming
matrix is always in a known state. From this point, parallel programming can be used to modify either a single output or multiple
outputs at one time.
Similarly, if both CE and UPDATE are taken low after initial
power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent programming
the crosspoint into an unknown state, do not apply low logic
levels to both CE and UPDATE after power is initially applied.
To eliminate the possibility of programming the matrix to an
unknown state, after initial power-up, program the full shift
register one time to a desired state using either serial or parallel
programming.
To change the programming of an output via parallel programming, take the SER/PAR and UPDATE pins high, and take the
CE pin low. The CLK signal should be in the high state. Place
the 4-bit address of the output to be programmed on A0 to A3.
The first four data bits (D0 to D3) contain the information that
identifies the input that is programmed to the addressed output.
The fifth data bit (D4) determines the enabled state of the output. If D4 is low (output disabled), the data on D0 to D3 does
not matter.
After the address and data signals are established, they can be
latched into the shift register by pulling the CLK signal low;
however, the matrix is not programmed until the UPDATE
signal is taken low. In this way, it is possible to latch in new data
for several or all of the outputs first via successive negative transitions of CLK while UPDATE is held high and then have all the
new data take effect when UPDATE goes low. Use this technique
when programming the device for the first time after power-up
when using parallel programming. In parallel mode, the CLK
pin is level sensitive, whereas in serial mode, it is edge triggered.
POWER-ON RESET
When powering up the ADV3226/ADV3227, it is usually desirable
to have the outputs come up in the disabled state. When taken
low, the RESET pin causes all outputs to be in the disabled state.
However, the RESET signal does not reset all registers in the
ADV3226/ADV3227. This is important when operating in the
parallel programming mode. Refer to the Parallel Programming
section for information about programming internal registers
after power-up. Serial programming programs the entire matrix
each time; therefore, no special considerations apply.
Because the data in the shift register is random after power-up,
it should not be used to program the matrix, or the matrix can
enter unknown states. To prevent the matrix from entering
unknown states, do not apply logic low signals to both CE and
UPDATE initially after power-up. Instead, first load the shift
register with the data and then take UPDATE low to program
the device.
The RESET pin has a 20 kΩ pull-up resistor to DVCC that can be
used to create a simple power-up reset circuit. A capacitor from
RESET to ground holds the RESET pin low for a period during
which the rest of the device stabilizes. The low condition causes
all of the outputs to be disabled. The capacitor then charges
through the pull-up resistor to the high state, thereby allowing full
programming capability of the device.
GAIN SELECTION
The 16 × 16 crosspoints come in two versions, depending on
the gain of the analog circuit path. The ADV3226 device is unity
gain and can be used for analog logic switching and other
applications where unity gain is desired. The ADV3226 outputs
have very high impedance when their outputs are disabled.
The ADV3227 can be used for devices that drive a terminated
cable with its outputs. This device has a built-in gain-of-2 that
eliminates the need for a gain-of-2 buffer to drive a video line. Its
Rev. 0 | Page 22 of 24
ADV3226/ADV3227
CREATING LARGER CROSSPOINT ARRAYS
The ADV3226/ADV3227 are high density building blocks for
creating crosspoint arrays of dimensions larger than 16 × 16.
Various features, such as output disable, chip enable, and gainof-1 and gain-of-2 options, are useful for creating larger arrays.
When required for customizing a crosspoint array size, they can
be used with the AD8108 and AD8109, which are a pair of
(unity-gain and gain-of-2) 8 × 8 video crosspoint switches, or
with the AD8110 and AD8111, a pair of (unity-gain and gainof-2) 16 × 8 video crosspoint switches.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of required devices that are
required. The 16 × 16 architecture of the ADV3226/ADV3227
contains 256 points, which is a factor of 64 greater than a 4 × 1
crosspoint (or multiplexer). The benefits realized in PCB area
used, power consumption, and design effort are readily apparent
when compared to using multiples of these smaller 4 × 1 devices.
To obtain the minimum number of required points for a nonblocking crosspoint, multiply the number of inputs by the number
of outputs. Nonblocking requires that the programming of a given
input to one or more outputs does not restrict the availability of
that input to be a source for any other outputs. Some nonblocking
crosspoint architectures require more than this minimum. In
addition, there are blocking architectures that can be constructed
with fewer devices than this minimum. These systems have
connectivity available on a statistical basis that is determined
when designing the overall system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-OR
the outputs together in the vertical direction. The meaning of
horizontal and vertical can best be understood by referring to
Figure 65, which illustrates this concept for a 32 × 32 crosspoint
array that uses four ADV3226 or ADV3227 devices.
IN 00–15
16
ADV3226
OR
ADV3227
16
16
RTERM
16
IN 16–31
16
ADV3226
OR
ADV3227
16
ADV3226
OR
ADV3227
16
16
16
RTERM
ADV3226
OR
ADV3227
16
08653-062
high output disabled impedance minimizes signal degradation
when paralleling additional outputs.
Figure 65. A 32 × 32 Nonblocking Crosspoint Switch Array
Each input is uniquely assigned to each of the 32 inputs of the two
devices and terminated appropriately. The outputs are wired-OR’ed
together in pairs. Enable the output from only one wire-OR’ed
pair at any given time. The device programming software must
be properly written to prevent multiple connected outputs from
being enabled at the same time.
For a complete 32 × 32 array in a single device, refer to the AD8117
and AD8118 for high bandwidth or the ADV3200 and
ADV3201 for lower bandwidth. Also available are 32 × 16 arrays in
a single package: AD8104, AD8105, ADV3202, and ADV3203.
Rev. 0 | Page 23 of 24
ADV3226/ADV3227
OUTLINE DIMENSIONS
0.25
0.20
0.15
0.60 MAX
0.60 MAX
75 76
PIN 1
INDICATOR
11.75
BSC SQ
100 1
0.40
BSC
(BOTTOM VIEW)
0.90
0.85
0.80
12° MAX
0.50
0.40
0.30
0.70
0.65
0.60
26
25
0.20 MIN
9.60 REF
0.05 MAX
0.01 NOM
SEATING
PLANE
7.00
6.90 SQ
6.80
EXPOSED PAD
51 50
TOP VIEW
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VRRE.
06-11-2008-B
12.00
BSC SQ
Figure 66. 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12 mm × 12 mm Body, Very Thin Quad
(CP-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADV3226ACPZ
ADV3227ACPZ
ADV3226-EVALZ
ADV3227-EVALZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
100-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
100-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08653-0-4/10(0)
Rev. 0 | Page 24 of 24
Package Option
CP-100-1
CP-100-1