325 MHz, 8 × 8 Buffered Video Crosspoint Switches AD8108/AD8109 FUNCTIONAL BLOCK DIAGRAM EATURES APPLICATIONS Routing of high speed signals including Composite video (NTSC, PAL, S, SECAM) Component video (YUV, RGB) Compressed video (MPEG, Wavelet) 3-level digital video (HDB3) GENERAL DESCRIPTION The AD8108/AD8109 are high speed 8 × 8 video crosspoint switch matrices. They offer a −3 dB signal bandwidth greater than 250 MHz and channel switch times of less than 25 ns with 1% settling. With −83 dB of crosstalk and −98 dB isolation (@5 MHz), the AD8108/AD8109 are useful in many high speed applications. The differential gain and differential phase of better than 0.02% SER/PAR D0 D1 D2 D3 A0 A1 CLK DATA IN A2 32-BIT SHIFT REGISTER WITH 4-BIT PARALLEL LOADING UPDATE CE 32 PARALLEL LATCH RESET 32 DECODE 8 4:8 DECODERS AD8108/AD8109 64 SWITCH MATRIX SET INDIVIDUAL OR RESET ALL OUTPUTS TO "OFF" 8 OUTPUT BUFFER G = +1 G = +2 8 OUTPUTS 01068-001 8 INPUTS DATA OUT ENABLE/DISABLE 8 × 8 high speed nonblocking switch arrays AD8108: G = 1 AD8109: G = 2 Serial or parallel programming of switch array Serial data out allows daisy-chaining of multiple 8 × 8 arrays to create larger switch arrays Output disable allows connection of multiple devices Pin-compatible with AD8110/AD8111 16 × 8 switch arrays For 16 × 16 arrays see AD8116 Complete solution Buffered inputs Eight output amplifiers AD8108 (G = 1) AD8109 (G = 2) Drives 150 Ω loads Excellent video performance 60 MHz 0.1 dB gain flatness 0.02%/0.02° differential gain/differential phase error (RL = 150 Ω) Excellent ac performance −3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109) Slew rate: 400 V/μs (AD8108), 480 V/μs (AD8109) Low power of 45 mA Low all hostile crosstalk of −83 dB @ 5 MHz Reset pin allows disabling of all outputs (connected through a capacitor to ground provides power-on reset capability) Excellent ESD rating: exceeds 4000 V human body model 80-lead LQFP (12 mm × 12 mm) Figure 1. Functional Block Diagram and 0.02°, respectively, along with 0.1 dB flatness out to 60 MHz, make the AD8108/AD8109 ideal for video signal switching. The AD8108 and AD8109 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off channels do not load the output bus. The AD8108 has a gain of 1, while the AD8109 offers a gain of 2. They operate on voltage supplies of ±5 V while consuming only 45 mA of idle current. The channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control allowing updating of an individual output without re-programming the entire array. The AD8108/AD8109 is packaged in an 80-lead LQFP package and is available over the extended industrial temperature range of −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the AD8108_8109* Last content update 08/23/2013 02:21 pm PARAMETRIC SELECTION TABLES DESIGN COLLABORATION COMMUNITY Find Similar Products By Operating Parameters High Speed Switches Collaborate Online with the ADI support team and other designers about select ADI products. DOCUMENTATION AN-282: Fundamentals of Sampled Data Systems Data-acquisition system uses fault protection CMOS Switches Offer High Performance in Low Power, Wideband Applications Enhanced Multiplexing for MEMS Optical Cross Connects FOR THE AD8108 AN-214: Ground Rules for High Speed Circuits Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for the AD8108 View the Evaluation Boards and Kits page for the AD8109 Symbols and Footprints for the AD8108 Symbols and Footprints for the AD8109 Americas: Europe: China: India: Russia: 1-800-262-5643 00800-266-822-82 4006-100-006 1800-419-0108 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY AD8108 AD8109 View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. 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AD8108/AD8109 TABLE OF CONTENTS AD8108/AD8109—Specifications ................................................. 3 Power-On RESET....................................................................... 19 Timing Characteristics (Serial) .................................................. 5 Gain Selection............................................................................. 19 Timing Characteristics (Parallel) ............................................... 6 Creating Larger Crosspoint Arrays.......................................... 20 Absolute Maximum Ratings............................................................ 8 Multichannel Video ................................................................... 21 Maximum Power Dissipation ..................................................... 8 Crosstalk ...................................................................................... 22 ESD Caution.................................................................................. 8 PCB Layout...................................................................................... 24 Pin Configuration and Function Descriptions............................. 9 Evaluation Board ............................................................................ 28 Typical Performance Characteristics ........................................... 11 Control the Evaluation Board from a PC................................ 28 I/O Schematics ................................................................................ 17 Overshoot of PC Printer Ports’ Data Lines............................. 28 Theory of Operation ...................................................................... 18 Outline Dimensions ....................................................................... 30 Applications................................................................................. 18 Ordering Guide .......................................................................... 30 REVISION HISTORY 9/05—Rev. A to Rev. B Updated Format.................................................................. Universal Change to Absolute Maximum Ratings..........................................8 Changes to Maximum Power Dissipation Section........................8 Change to Figure 4 ............................................................................8 Updated Outline Dimensions ........................................................30 Changes to Ordering Guide ...........................................................30 1/02—Rev. 0 to Rev. A Universal change in nomenclature from MQFP to LQFP ............. Comment added to OUTLINE DIMENSIONS ..........................27 Revision 0: Initial Version Rev. B | Page 2 of 32 AD8108/AD8109 AD8108/AD8109—SPECIFICATIONS VS = ±5 V, TA = +25°C, RL = 1 kΩ, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Unit Reference 325/250 MHz 2 V p-p, RL = 150 Ω 140/160 MHz Figure 1, Figure 13 Figure 1, Figure 13 Propagation Delay Slew Rate Settling Time 2 V p-p, RL = 150 Ω 2 V Step, RL = 150 Ω 0.1%, 2 V Step, RL = 150 Ω 5 400/480 40 ns V/µs ns Gain Flatness 0.05 dB, 200 mV p-p, RL = 150 Ω 60/50 MHz 0.05 dB, 2 V p-p, RL = 150 Ω 60/50 MHz 0.1 dB, 200 mV p-p, RL = 150 Ω 70/65 MHz 0.1 dB, 2 V p-p, RL = 150 Ω 80/50 MHz NTSC or PAL, RL = 1 kΩ NTSC or PAL, RL = 150 Ω NTSC or PAL, RL = 1 kΩ NTSC or PAL, RL = 150 Ω f = 5 MHz 0.01 0.02 0.01 0.02 83/85 % % Degrees Degrees dB f = 10 MHz 76/83 dB f = 10 MHz, RL =150 Ω, one channel 0.01 MHz to 50 MHz 93/98 dB 15 nV/√Hz RL = 1 kΩ RL = 150 Ω No load, channel-channel RL = 1 kΩ, channel-channel 0.04/0.1 0.15/0.25 NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile Off Isolation, Input-Output Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching Gain Temperature Coefficient OUTPUT CHARACTERISTICS Output Impedance Output Disable Capacitance Output Leakage Current Output Voltage Range Output Current Short-Circuit Current Conditions Min Typ 200 mV p-p, RL = 150 Ω 240/150 Max 0.07/0.5 0.5/8 % % % % ppm/°C DC, enabled 0.2 Ω Disabled 10/0.001 MΩ Disabled Disabled, AD8108 only No load 2 1/NA ±3 40 65 pF µA V mA mA 0.02/1.0 0.09/1.0 ±2.5 20 Rev. B | Page 3 of 32 Figure 15, Figure 18 Figure 1, Figure 13 Figure 1, Figure 13 Figure 1, Figure 13 Figure 1, Figure 13 Figure 8, Figure 14 Figure 8, Figure 14 Figure 23, Figure 29 Figure 20, Figure 26 Figure 24, Figure 30 Figure 21, Figure 27 AD8108/AD8109 Parameter INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA Conditions Min Typ Max Unit Reference Worst case (all configurations) 5 20 mV Temperature coefficient 12 µV/°C Figure 35, Figure 41 Figure 36, Figure 42 Per output selected ±3/±1.5 2.5 10 2 V pF MΩ µA 50% UPDATE to 1% settling Measured at output 60 25 20/30 ns ns mV p-p f = 100 kHz 33 10 33 10 10 ±4.5 to ±5.5 73/78 mA mA mA mA mA V dB f = 1 MHz 55/58 dB Operating (still air) Operating (still air) −40 to +85 48 °C °C/W ±2.5/±1.25 Any switch configuration 1 AVCC, outputs enabled, no load AVCC, outputs disabled AVEE, outputs enabled, no load AVEE, outputs disabled DVCC Rev. B | Page 4 of 32 5 Figure 22, Figure 28 Figure 19, Figure 25 AD8108/AD8109 TIMING CHARACTERISTICS (SERIAL) Table 2. Timing Characteristics Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation, Serial Mode CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid, Serial Mode Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 t7 – – – – Min 20 100 20 100 0 50 Typ Max 180 8 6.4 100 200 Unit ns ns ns ns ns ns ns ns µs ns ns Table 3. Logic Levels VIH RESET, SER/PAR CLK, DATA IN, CE, UPDATE VIL RESET, SER/PAR CLK, DATA IN, CE, UPDATE VOH DATA OUT VOL DATA OUT IIH RESET, SER/PAR CLK, DATA IN, CE, UPDATE IIL RESET, SER/PAR CLK, DATA IN, CE, UPDATE IOH DATA OUT IOL DATA OUT 2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min t2 t4 1 CLK 0 t1 LOAD DATA INTO SERIAL REGISTER ON FALLING EDGE t3 1 DATA IN OUT7 (D3) OUT00 (D0) OUT7 (D2) 0 t5 t6 1 = LATCHED TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL t7 01068-002 UPDATE 0 = TRANSPARENT DATA OUT Figure 2. Timing Diagram, Serial Mode Rev. B | Page 5 of 32 AD8108/AD8109 TIMING CHARACTERISTICS (PARALLEL) Table 4. Timing Characteristics Parameter Data Setup Time CLK Pulse Width Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off CLK, UPDATE Rise and Fall Times RESET Time Symbol t1 t2 t3 t4 t5 t6 – – – Min 20 100 20 100 0 50 Typ Max 8 100 200 Unit ns ns ns ns ns ns ns ns ns Table 5. Logic Levels VIH RESET, SER/PAR CLK, D0, D1, D2, D3, A0, A1, A2 CE, UPDATE VIL RESET, SER/PAR CLK, D0, D1, D2, D3, A0, A1, A2 CE, UPDATE VOH DATA OUT VOL DATA OUT IIH RESET, SER/PAR CLK, D0, D1, D2, D3, A0, A1, A2 CE, UPDATE IIL RESET SER/PAR CLK, D0, D1, D2, D3, A0, A1, A2 CE, UPDATE IOH DATA OUT IOL DATA OUT 2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min t2 t4 1 CLK 0 t1 D0–D3 A0–A2 t3 1 0 t5 01068-003 1 = LATCHED t6 UPDATE 0 = TRANSPARENT Figure 3. Timing Diagram, Parallel Mode Rev. B | Page 6 of 32 AD8108/AD8109 Table 6. Operation Truth Table UPDATE X 1 SER/ PAR X 0 NA in parallel mode X 1 1 1 X X 0 X X 1 CLK X f DATA IN X Datai DATA OUT X Datai-32 0 1 f 0 0 X D0 … D3, A0 … A2 X… X X X X RESET Operation/Comment No change in logic. The data on the serial DATA IN line is loaded into serial register. The first bit clocked into the serial register appears at DATA OUT 32 clocks later. The data on the parallel data lines, D0 to D3, are loaded into the 32-bit serial shift register location addressed by A0 to A2. Data in the 32-bit shift register transfers into the parallel latches that control the switch array. Latches are transparent. Asynchronous operation. All outputs are disabled. Remainder of logic is unchanged. D0 D1 D2 (OUTPUT ENABLE) D3 PARALLEL DATA SER/PAR DATA IN (SERIAL) S D1 Q D Q S D1 Q DQ S D1 Q DQ S D1 Q DQ S D1 Q DQ S D1 D0 CLK D0 CLK D0 CLK D0 CLK D0 CLK S D1 Q DQ D0 CLK Q D0 S D1 DQ Q D0 CLK DQ S D1 Q DQ S D1 Q D Q CLK D0 CLK D0 CLK DATA OUT CLK CE RESET OUT0 EN OUT1 EN A1 A2 OUT2 EN OUT3 EN OUT4 EN OUT5 EN OUT6 EN OUT7 EN LE D LE D LE D LE D LE D LE D LE D LE D LE D LE D OUT0 B0 OUT0 B1 OUT0 B2 OUT0 EN OUT1 B0 OUT6 EN OUT7 B0 OUT7 B1 OUT7 B2 OUT7 EN Q Q Q Q CLR Q Q Q Q CLR Q CLR Q DECODE 64 SWITCH MATRIX Figure 4. Logic Diagram Rev. B | Page 7 of 32 8 OUTPUT ENABLE 01068-011 A0 3 TO 8 DECODER CE 1 0 AD8108/AD8109 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Supply Voltage Internal Power Dissipation1 AD8108/AD8109 80-Lead Plastic LQFP (ST) Input Voltage Output Short-Circuit Duration Storage Temperature Range2 2 2.6 W ±VS Observe power derating curves −65°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Specification is for device in free air (TA = 25°C): 80-lead plastic LQFP (ST): θJA = 48°C/W. Maximum reflow temperatures are to JEDEC industry standard J-STD-020. 5.0 MAXIMUM POWER DISSIPATION While the AD8108/AD8109 are internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (125°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 5. MAXIMUM POWER DISSIPATION (Ω) TJ = 125°C The maximum power that can be safely dissipated by the AD8108/AD8109 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 125°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 125°C for an extended period can result in device failure. 4.0 3.0 2.0 1.0 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE (°C) 80 90 Figure 5. Maximum Power Dissipation vs. Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 8 of 32 01068-004 1 Rating 12.0 V AD8108/AD8109 RESET DGND DVCC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DVCC DGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 IN00 1 60 CE 59 DATA OUT IN01 3 58 CLK AGND 4 57 DATA IN IN02 5 56 UPDATE AGND 6 55 SER/PAR IN03 7 54 A0 53 A1 52 A2 AGND 10 51 D0 IN05 11 50 D1 AGND 12 49 D2 IN06 13 48 D3 AGND 14 47 NC IN07 15 46 AGND AGND 16 45 AVEE AVEE 17 44 AVCC AVCC 18 43 AVCC00 AVCC07 19 42 AGND00 OUT07 20 41 OUT00 PIN 1 AGND 2 AD8108/AD8109 AGND 8 TOP VIEW (Not to Scale) IN04 9 Figure 6. Pin Configuration Rev. B | Page 9 of 32 01068-005 AVEE00/01 AGND01 OUT01 AVCC01/02 AGND02 OUT02 AVEE02/03 AGND03 OUT03 AVCC03/04 AGND04 OUT04 AVEE04/05 AGND06 OUT05 AVCC05/06 AGND06 OUT06 AGND07 NC = NO CONNECT AVEE06/07 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AD8108/AD8109 Table 8. Pin Function Descriptions Pin No. 1, 3, 5, 7, 9, 11, 13, 15 57 58 59 56 Mnemonic INxx DATA IN CLK DATA OUT UPDATE 61 60 55 41, 38, 35, 32, 29, 26, 23, 20 2, 4, 6, 8, 10, 12, 14, 16, 46 63, 79 62, 80 17, 45 18, 44 42, 39, 36, 33, 30, 27, 24, 21 43, 37, 31, 25, 19 40, 34, 28, 22 54 53 52 51 50 49 48 47, 64 to 78 RESET CE SER/PAR OUTyy AGND DVCC DGND AVEE AVCC AGNDxx AVCCxx/yy AVEExx/yy A0 A1 A2 D0 D1 D2 D3 NC Description Analog Inputs. xx = Channels 00 through 07. Serial Data Input, TTL Compatible. Clock, TTL Compatible. Falling edge triggered. Serial Data Output, TTL Compatible. Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data latched when high. Disable Outputs, Active Low. Chip Enable, Enable Low. Must be low to clock in and latch data. Selects Serial Data Mode, Low or Parallel, High. Must be connected. Analog Outputs. yy = Channels 00 through 07. Analog Ground for Inputs and Switch Matrix. 5 V for Digital Circuitry Ground for Digital Circuitry −5 V for Inputs and Switch Matrix. +5 V for Inputs and Switch Matrix. Ground for Output Amp. xx = Output Channels 00 through 07. Must be connected. +5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected. −5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected. Parallel Data Input, TTL Compatible (output select LSB). Parallel Data Input, TTL Compatible (output select). Parallel Data Input, TTL Compatible (output select MSB). Parallel Data Input, TTL Compatible (input select LSB). Parallel Data Input, TTL Compatible (input select). Parallel Data Input, TTL Compatible (input select MSB). Parallel Data Input, TTL Compatible (output enable). No Connect. Rev. B | Page 10 of 32 AD8108/AD8109 TYPICAL PERFORMANCE CHARACTERISTICS 5 0.4 RL = 150Ω 0.3 0.2 2 0.1 +50mV FLATNESS 0 1 200mV p-p 0 –0.1 GAIN 25mV/DIV 3 FLATNESS (dB) GAIN (dB) 4 +25mV 0 –25mV –50mV –0.2 –1 –3 100k 1M 10M FREQUENCY (Hz) 100M 01068-012 –0.3 –2 01068-015 2V p-p –0.4 1G 10ns/DIV Figure 10. AD8108 Step Response, 100 mV Step Figure 7. AD8108 Frequency Response –10 RL = 1kΩ –20 –30 +1.0V 500mV/DIV CROSSTALK (dB) –40 –50 ALL HOSTILE –60 –70 +0.5V 0 –0.5V –1.0V –80 ADJACENT 01068-013 01068-016 –90 –100 –110 0.2 1 10 FREQUENCY (MHz) 100 10ns/DIV 200 Figure 11. AD8108 Step Response, 2 V Step Figure 8. AD8108 Crosstalk vs. Frequency –30 –40 RL = 150Ω VOUT = 2V p-p 2V STEP RL=150Ω 0.2 0.1%/DIV 2ND HARMONIC –60 –70 0 –0.1 –0.2 –80 01068-017 3RD HARMONIC –90 –100 100k 0.1 01068-014 DISTORTION (dB) –50 1M 10M FREQUENCY (Hz) 0 100M Figure 9. AD8108 Distortion vs. Frequency 10 20 30 40 50 10ns/DIV 60 Figure 12. AD8108 Settling Time Rev. B | Page 11 of 32 70 80 AD8108/AD8109 5 0.4 4 0.3 3 0.2 +50mV 200mV p-p 1 0 –0.1 0 GAIN +25mV 0 –25mV –50mV –0.3 2V p-p –2 –3 100k 1M 10M FREQUENCY (Hz) –0.4 1G 100M 01068-021 –0.2 –1 01068-018 GAIN (dB) FLATNESS 25mV/DIV 0.1 2 FLATNESS (dB) 2V p-p 10ns/DIV Figure 16. AD8109 Step Response, 100 mV Step Figure 13. AD8109 Frequency Response –20 RL = 1kΩ –30 –40 0.5V/DIV CROSSTALK (dB) +1.0V –50 –60 ADJACENT –70 +0.5V 0 –0.5V –80 –1.0V ALL HOSTILE 01068-019 –100 –110 300k 01068-022 –90 1M 10M FREQUENCY (Hz) 10ns/DIV 100M 200M Figure 17. AD8109 Step Response, 2 V Step Figure 14. AD8109 Crosstalk vs. Frequency –30 –40 2V STEP RL = 150Ω RL = 150Ω VOUT = 2V p-p 0.2 0.1%/DIV 2ND HARMONIC –60 –70 0 –0.1 –0.2 –80 01068-023 3RD HARMONIC –90 –100 100k 0.1 01068-020 DISTORTION (dB) –50 1M 10M FREQUENCY (Hz) 0 100M Figure 15. AD8109 Distortion vs. Frequency 10 20 30 40 50 10ns/DIV 60 Figure 18. AD8109 Settling Time Rev. B | Page 12 of 32 70 80 AD8108/AD8109 –30 5 SWITCHING BETWEEN TWO INPUTS 1V/DIV 4 –50 3 UPDATE INPUT 2 1 –60 0 –70 10mV/DIV 10 –90 10k 100k 1M FREQUENCY (Hz) 0 TYPICAL VIDEO OUT (RTO) –10 01068-027 –80 01068-024 POWER SUPPLY REJECTION (dB) RL = 150Ω –40 50ns/DIV 10M Figure 19. AD8108 PSRR vs. Frequency Figure 22. AD8108 Switching Transient (Glitch) 100 –40 –50 56.3 VIN = 2V p-p RL = 150Ω OFF ISOLATION (dB) –60 17.8 10 –80 –90 –100 –110 01068-025 100 1k 100k 10k FREQUENCY (Hz) 1M –130 –140 100k 10M 100k 100 OUTPUT IMPEDANCE (Ω) 1k 10k 1k 01068-026 OUTPUT IMPEDANCE (Ω) 1M 0.1 1 10 FREQUENCY (MHz) 100 1M 10M FREQUENCY (Hz) 100M 500M Figure 23. AD8108 Off Isolation, Input-Output Figure 20. AD8108 Voltage Noise vs. Frequency 100 01068-028 –120 5.63 3.16 10 –70 10 1 0.1 100k 500 Figure 21. AD8108 Output Impedance, Disabled 01068-029 nV/√Hz 31.6 1M 10M FREQUENCY (Hz) 100M Figure 24. AD8108 Output Impedance, Enabled Rev. B | Page 13 of 32 500M AD8108/AD8109 –30 5 1V/DIV –50 3 0 –70 –80 100k 1M FREQUENCY (Hz) 0 TYPICAL VIDEO OUT (RTO) –10 01068-033 10mV/DIV 10 50ns/DIV 10M Figure 25. AD8109 PSRR vs. Frequency Figure 28. AD8109 Switching Transient (Glitch) 100.0 –40 –50 56.3 VOUT = 2V p-p RL = 150Ω OFF ISOLATION (dB) –60 31.6 17.8 10.0 –70 –80 –90 –100 –110 01068-031 3.16 10 100 1k 100k 10k FREQUENCY (Hz) 1M –130 –140 100k 10M Figure 26. AD8109 Voltage Noise vs. Frequency 10k 100 OUTPUT IMPEDANCE (Ω) 1k 1k 01068-032 100 1M 10M FREQUENCY (Hz) 100M 1M 10M FREQUENCY (Hz) 100M 500M Figure 29. AD8109 Off Isolation, Input-Output 100k 1 100k 01068-034 –120 5.63 10 1 0.1 100k 500M 01068-035 nV/√Hz UPDATE INPUT 2 1 –60 –90 10k OUTPUT IMPEDANCE (Ω) SWITCHING BETWEEN TWO INPUTS 4 01068-030 POWER SUPPLY REJECTION (dB RTI) RL = 150Ω –40 1M 10M FREQUENCY (Hz) 100M Figure 30. AD8109 Output Impedance, Enabled Figure 27. AD8109 Output Impedance, Disabled Rev. B | Page 14 of 32 500M AD8108/AD8109 1M 1V/DIV VOUT INPUT IMPEDANCE (Ω) 100k 1 INPUT 1 AT +1V 0 –1 INPUT 0 AT –1V 10k 2V/DIV 5 1k UPDATE 01068-036 100 30k 01068-039 0 100k 1M 10M FREQUENCY (Hz) 100M 50ns/DIV 500M Figure 34. AD8108 Switching Time Figure 31. AD8108 Input Impedance vs. Frequency 900 VIN = 200mV RL = 150Ω CL = 18pF 800 6 700 FREQUENCY 2 CL = 12pF 0 –2 600 500 400 –4 300 –6 200 01068-037 GAIN (dB) 4 –8 30k 100k 1M 10M 100M FREQUENCY (Hz) 1G 100 0 –0.020 3G –0.010 0.000 OFFSET VOLTAGE (V) 0.010 0.020 Figure 35. AD8108 Offset Voltage Distribution Figure 32. AD8108 Frequency Response vs. Capacitive Load 2.0 0.5 0.4 01068-040 8 VIN = 200mV RL = 150Ω 1.5 CL = 18pF 0.3 1.0 0.5 VOS (mV) 0.1 0 CL = 12pF –0.1 0.0 –0.5 –0.2 –1.0 –0.3 01068-038 –0.4 –0.5 30k 100k 1M 10M 100M FREQUENCY (Hz) Figure 33. AD8108 Flatness vs. Capacitive Load 1G –1.5 –2.0 –60 3G 01068-041 FLATNESS (dB) 0.2 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 Figure 36. AD8108 Offset Voltage Drift vs. Temperature (Normalized at 25°C) Rev. B | Page 15 of 32 AD8108/AD8109 1M 1V/DIV VOUT INPUT IMPEDANCE (Ω) 100k 1 INPUT 1 AT +1V 0 –1 INPUT 0 AT –1V 10k 2V/DIV 5 1k UPDATE 01068-042 100 30k 01068-045 0 100k 1M 10M FREQUENCY (Hz) 100M 50ns/DIV 500M Figure 40. AD8109 Switching Time Figure 37. AD8109 Input Impedance vs. Frequency 320 VIN = 100mV RL = 150Ω 8 300 280 6 260 CL = 18pF 240 FREQUENCY GAIN (dB) 4 2 0 –2 CL = 12pF 220 200 180 160 140 120 –4 100 –6 80 30k 100k 1M 10M 100M FREQUENCY (Hz) 1G 01068-046 60 01068-043 –8 40 0 –0.020 3G Figure 38. AD8109 Frequency Response vs. Capacitive Load –0.010 0.000 0.010 OFFSET VOLTAGE (V) 0.020 Figure 41. AD8109 Offset Voltage Distribution (RTI) 2.0 0.4 VIN = 100mV RL = 150Ω 1.5 0.3 0.5 VOS (mV) 0.1 0 CL = 12pF –0.1 0.0 –0.5 –0.2 –1.0 –0.3 100k 1M 10M 100M FREQUENCY (Hz) Figure 39. AD8109 Flatness vs. Capacitive Load 1G –2.0 –60 3G 01068-047 –0.4 30k –1.5 01068-044 GAIN (dB) 1.0 CL = 18pF 0.2 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 Figure 42. AD8109 Offset Voltage Drift vs. Temperature (Normalized at 25°C) Rev. B | Page 16 of 32 AD8108/AD8109 I/O SCHEMATICS VCC VCC ESD ESD INPUT INPUT ESD AVEE 01068-009 01068-006 ESD DGND Figure 43. Analog Input Figure 46. Logic Input VCC VCC ESD 2kΩ ESD OUTPUT OUTPUT DGND Figure 44. Analog Output Figure 47. Logic Output VCC ESD 20kΩ DGND 01068-008 ESD Figure 45. Reset Input Rev. B | Page 17 of 32 01068-010 AVEE ESD 01068-007 ESD 1kΩ (AD8109 ONLY) AD8108/AD8109 THEORY OF OPERATION The AD8108 (G = 1) and AD8109 (G = 2) share a common core architecture consisting of an array of 64 transconductance (gm) input stages organized as eight 8:1 multiplexers with a common 8-line analog input bus. Each multiplexer is basically a foldedcascode, high impedance voltage feedback amplifier with eight input stages. The input stages are NPN differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, compensation and a complementary emitter follower output buffer. In the AD8108, the output of each multiplexer is fed back directly to the inverting inputs of its eight gm stages. In the AD8109, the feedback network is a voltage divider consisting of two equal resistors. This switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back terminated video load (150 Ω) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02°, respectively). This design also achieves high input resistance and low input capacitance without the signal degradation and power dissipation of additional input buffers. However, the small input bias current at any input will increase almost linearly with the number of outputs programmed to that input. The output disable feature of these crosspoints allows larger switch matrices to be built by simply busing together the outputs of multiple 8 × 8 ICs. However, while the disabled output impedance of the AD8108 is very high (10 MΩ), that of the AD8109 is limited by the resistive feedback network (which has a nominal total resistance of 1 kΩ) that appears in parallel with the disabled output. If the outputs of multiple AD8109s are connected through separate back termination resistors, the loading due to these finite output impedances will lower the effective back termination impedance of the overall matrix. This problem is eliminated if the outputs of multiple AD8109s are connected directly and share a single back termination resistor for each output of the overall matrix. This configuration increases the capacitive loading of the disabled AD8109s on the output of the enabled AD8109. APPLICATIONS The AD8108/AD8109 have two options for changing the programming of the crosspoint matrix. In the first, a serial word of 32 bits can be provided that will update the entire matrix each time. The second option allows for changing a single output’s programming via a parallel interface. The serial option requires fewer signals, but requires more time (clock cycles) for changing the programming, while the parallel programming technique requires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming. Serial Programming The serial programming mode uses the device pins CE, CLK, DATA IN, UPDATE, and SER/PAR. The first step is to assert a low on SER/PAR to enable the serial programming mode. CE for the chip must be low to allow data to be clocked into the device. The CE signal can be used to address an individual device when devices are connected in parallel. The UPDATE signal should be high during the time that data is shifted into the device’s serial port. Although the data will still shift in when UPDATE is low, the transparent, asynchronous latches will allow the shifting data to reach the matrix. This will cause the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every down edge of CLK. A total of 32 data bits must be shifted in to complete the programming. For each of the eight outputs, there are three bits (D0 to D2) that determine the source of its input followed by one bit (D3) that determines the enabled state of the output. If D3 is low (output disabled), the three associated bits (D0 to D2) do not matter because no input will be switched to that output. The most significant output address data is shifted in first and is followed in sequence until the least significant output address data is shifted in. At this point, UPDATE can be taken low, which will cause the programming of the device according to the data that was just shifted in. The UPDATE registers are asynchronous, and when UPDATE is low, they are transparent. If more than one AD8108/AD8109 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, CE, UPDATE, and SER/PAR pins should be connected in parallel and operated as described above. The serial data is input to the DATA IN pin of the first device of the chain, and it will ripple on through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence will be 32 times the number of devices in the chain. Parallel Programming While using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output at a time. Since this takes only one CLK/UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RESET signal does not reset all registers in the Rev. B | Page 18 of 32 AD8108/AD8109 AD8108/AD8109. When taken low, the RESET signal will only set each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device will generally have random data, even though the RESET signal was asserted. If parallel programming is used to program one output, that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up. This will ensure that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single, or more, output at a time. In a similar fashion, if both CE and UPDATE are taken low after initial power-up, the random power-up data in the shift register will be programmed into the matrix. Therefore, to prevent the crosspoint from being programmed into an unknown state, do not apply low logic levels to both CE and UPDATE after power is initially applied. Programming the full shift register one time to a desired state by either serial or parallel programming after initial power-up will eliminate the possibility of programming the matrix to an unknown state. To change an output’s programming via parallel programming, SER/PAR and UPDATE should be taken high and CE should be taken low. The CLK signal should be in the high state. The address of the output that is to be programmed should be put on A0 to A2. The first three data bits (D0 to D2) should contain the information that identifies the input that is programmed to the output that is addressed. The fourth data bit (D3) will determine the enabled state of the output. If D3 is low (output disabled), the data on D0 to D2 does not matter. After the desired address and data signals have been established, they can be latched into the shift register by a high to low transition of the CLK signal. The matrix will not be programmed, however, until the UPDATE signal is taken low. Thus, it is possible to latch in new data for several or all of the outputs first via successive negative transitions of CLK while UPDATE is held high, and then have all the new data take effect when UPDATE goes low. This technique should be used when programming the device for the first time after power-up when using parallel programming. POWER-ON RESET When powering up the AD8108/AD8109, it is usually desirable to have the outputs come up in the disabled state. When taken low, the RESET pin will cause all outputs to be in the disabled state. However, the RESET signal does not reset all registers in the AD8108/AD8109. This is important when operating in the parallel programming mode. Please refer to that section for information about programming internal registers after powerup. Serial programming will program the entire matrix each time, so no special considerations apply. Since the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix can enter unknown states. To prevent this, do not apply logic low signals to both CE and UPDATE initially after power-up. The shift register should first be loaded with the desired data, and then UPDATE can be taken low to program the device. The RESET pin has a 20 kΩ pull-up resistor to DVDD that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground will hold RESET low for some time while the rest of the device stabilizes. The low condition will cause all the outputs to be disabled. The capacitor will then charge through the pull-up resistor to the high state, thus allowing full programming capability of the device. GAIN SELECTION The 8 × 8 crosspoints come in two versions, depending on the desired gain of the analog circuit paths. The AD8108 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. The AD8108 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. The AD8108 outputs have very high impedance when their outputs are disabled. The AD8109 can be used for devices that will be used to drive a terminated cable with its outputs. This device has a built-in gain of 2 that eliminates the need for a gain-of-2 buffer to drive a video line. Because of the presence of the feedback network in these devices, the disabled output impedance is about 1 kΩ. If external amplifiers will be used to provide a G = 2, Analog Devices’ AD8079 is a fixed gain-of-2 buffer. Rev. B | Page 19 of 32 AD8108/AD8109 8 The first consideration in constructing a larger crosspoint is to determine the minimum number of devices required. The 8 × 8 architecture of the AD8108/AD8109 contains 64 points, which is a factor of 16 greater than a 4 × 1 crosspoint. The PC board area and power consumption savings are readily apparent when compared to using these smaller devices. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs. Some nonblocking crosspoint architectures will require more than this minimum as calculated above. Also, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system. The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to wireOR the outputs together in the vertical direction. The meaning of horizontal and vertical can best be understood by looking at a diagram. An 8 input by 16 output crosspoint array can be constructed as shown in Figure 48. This configuration parallels two inputs per channel and does not require paralleling of any outputs. Inputs are easier to parallel than outputs because there are lower parasitics involved. For a 16 × 8 crosspoint, the AD8110 (gain of 1) or AD8111 (gain of 2) device can be used. These devices are already configured into a 16 × 8 crosspoint in a single device. 8 8 8 ONE TERMINATION PER INPUT AD8108 OR AD8109 8 RTERM 8 IN 08–15 8 8 08–15 8×8 8×8 8 RTERM 8 OUT 00–07 8 OUT 08–15 Figure 49. 16 × 16 Crosspoint Array Using Four AD8108s or AD8109s IN 00–07 8 8 IN 08–15 8 IN 16–23 8×8 8×8 8 8 8×8 8×8 8 8 8×8 8×8 8 RTERM 8 RTERM 8×8 8 8×8 8 8×8 8 8 8 OUT 00–07 OUT 08–15 RTERM 8 OUT 16–23 Figure 50. 24 × 24 Crosspoint Array Using Nine AD8108s or AD8109s At some point, the number of outputs that are wire-OR’ed becomes too great to maintain system performance. This will vary according to which system specifications are most important. For example, a 64 × 8 crosspoint can be created with eight AD8108/AD8109s. This design will have 64 separate inputs and have the corresponding outputs of each device wireOR’ed together in groups of eight. 8 16 OUTPUTS OUT 00–15 8×8 8 01068-048 8 INPUTS IN 00–07 AD8108 OR AD8109 00–07 8×8 IN 00–07 01068-049 The AD8108/AD8109 are high density building blocks for creating crosspoint arrays of dimensions larger than 8 × 8. Various features, such as output disable, chip enable, and gain-of-1 and-2 options, are useful for creating larger arrays. For very large arrays, they can be used along with the AD8116, a 16 × 16 video cross-point device. In addition, systems that require more inputs than outputs can use the AD8110 and/or the AD8111, which are (gain-of-1 and gain-of-2) 16 × 8 crosspoint switches. Figure 49 illustrates a 16 × 16 crosspoint array, while a 24 × 24 crosspoint is illustrated in Figure 50. The 16 × 16 crosspoint requires that each input driver drive two inputs in parallel and each output be wire-OR’ed with one other output. The 24 × 24 crosspoint requires driving three inputs in parallel and having the outputs wire-OR’ed in groups of three. It is required of the system programming that only one output of a wired-OR node be active at a time. 01068-050 CREATING LARGER CROSSPOINT ARRAYS Figure 48. 8 × 16 Crosspoint Array Using Two AD8108s (Unity Gain) or Two AD8109s (Gain of 2) Rev. B | Page 20 of 32 AD8108/AD8109 Using additional crosspoint devices in the design can lower the number of outputs that must be wire-OR’ed together. Figure 51 shows a block diagram of a system using eight AD8108s and two AD8109s to create a nonblocking, gain-of-2, 64 × 8 crosspoint that restricts the wire-OR’ing at the output to only four outputs. The rank 1 wire-OR’ed devices are AD8108s, which have higher disabled output impedance than the AD8109. RANK 1 (64:16) IN 08–15 IN 16–23 IN 24–31 8 8 8 8 8 IN 32–39 IN 40–47 8 8 IN 48–55 8 IN 56–63 In such systems, the video signals are differential; there is a positive and negative (or inverted) version of the signals. These complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first-order zero commonmode signal. At the receive end, the signals are differentially received and converted back into a single-ended signal. 4 AD8108 4 4 RANK 2 16 × 8 NONBLOCKING 16 × 16 BLOCKING AD8108 4 4 AD8108 4 4 4 1kΩ 4 AD8109 4 4 1kΩ OUT 00–07 NONBLOCKING AD8108 4 4 4 AD8108 4 AD8109 4 4 4 1kΩ 4 ADDITIONAL 8 OUTPUTS (SUBJECT TO BLOCKING) 1kΩ AD8108 4 4 AD8108 4 4 AD8108 4 When switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video channel. Thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. For a single AD8108/AD8109, four differential video channels can be assigned to the eight inputs and eight outputs. This will effectively form a 4 × 4 differential crosspoint switch. Programming such a device will require that inputs and outputs be programmed in pairs. This information can be deduced by inspection of the programming format of the AD8108/AD8109 and the requirements of the system. 01068-051 IN 00–07 that operates in noisy environments or where common-mode voltages are present between transmitting and receiving equipment. Figure 51. Nonblocking 64 × 8 Array with Gain of 2 (64 × 16 Blocking) Additionally, by using the lower four outputs from each of the two rank 2 AD8109s, a blocking 64 × 16 crosspoint array can be realized. There are, however, some drawbacks to this technique. The offset voltages of the various cascaded devices will accumulate, and the bandwidth limitations of the devices will compound. In addition, the extra devices will consume more current and take up more board space. Once again, the overall system design specifications will determine how to make the various tradeoffs. MULTICHANNEL VIDEO The excellent video specifications of the AD8108/AD8109 make them ideal candidates for creating composite video crosspoint switches. These can be made quite dense by taking advantage of the AD8108/AD8109’s high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. There are, however, other video formats that can be routed with the AD8108/AD8109 requiring more than one crosspoint channel per video channel. Some systems use twisted-pair wiring to carry video signals. These systems utilize differential signals and can lower costs because they use lower cost cables, connectors, and termination methods. They also have the ability to lower crosstalk and reject common-mode signals, which can be important for equipment There are other analog video formats requiring more than one analog circuit per video channel. One 2-circuit format that is commonly being used in systems such as satellite TV, digital cable boxes, and higher quality VCRs is called S-video or Y/C video. This format carries the brightness (luminance or Y) portion of the video signal on one channel and the color (chrominance, chroma, or C) on a second channel. Since S-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video channel to two crosspoint channels, as in the case of a differential video system. Aside from the nature of the video format, other aspects of these two systems will be the same. There are yet other video formats using three channels to carry the video information. Video cameras produce RGB (red, green, blue) directly from the image sensors. RGB is also the usual format used by computers internally for graphics. RGB can be converted to Y, R-Y, B-Y format, sometimes called YUV format. These 3-circuit video standards are referred to as component analog video. The component video standards require three crosspoint channels per video channel to handle the switching function. In a fashion similar to the 2-circuit video formats, the inputs and outputs are assigned in groups of three, and the appropriate logic programming is performed to route the video signals. Rev. B | Page 21 of 32 AD8108/AD8109 CROSSTALK Many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in proximity in a system, as will undoubtedly be the case in a system that uses the AD8108/ AD8109, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required to specify a system that uses one or more AD8108/AD8109s. Types of Crosstalk Crosstalk can be propagated by means of any of three methods. These fall into the categories of electric field, magnetic field, and sharing of common impedances. This section will explain these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields will then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. Areas of Crosstalk For a practical AD8108/AD8109 circuit, it is required that it be mounted to some sort of circuit board to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that a system’s crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. It is important to try to separate these two areas of crosstalk when attempting to minimize its effect. In addition, crosstalk can occur among the inputs to a crosspoint and among the outputs. It can also occur from input to output. Techniques will be discussed for diagnosing which part of a system is contributing to crosstalk. Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by: XT = 20 log 10 (Asel( s ) Atest ( s )) where s = jω is the Laplace transform variable, Asel(s) is the amplitude of the crosstalk-induced signal in the selected channel, and Atest(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal will have a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 8 × 8 matrix of the AD8108/AD8109, we can examine the number of crosstalk terms that can be considered for a single channel, say IN00 input. IN00 is programmed to connect to one of the AD8108/AD8109 outputs where the measurement can be made. We can first measure the crosstalk terms associated with driving a test signal into each of the other seven inputs one at a time. We can then measure the crosstalk terms associated with driving a parallel test signal into all seven other inputs taken two at a time in all possible combinations, and then three at a time, etc., until there is only one way to drive a test signal into all seven other inputs. Each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then to specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other (not used for measurement) outputs are taken into consideration, the numbers rather Rev. B | Page 22 of 32 AD8108/AD8109 quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8108/AD8109s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all hostile crosstalk. This term means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this will yield the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst-case measure for any other 1-channel or 2-channel crosstalk measurements. Input and Output Crosstalk The flexible programming capability of the AD8108/AD8109 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input channel (IN03 in the middle for this example) can be programmed to drive OUT03. The input to IN03 is just terminated to ground (via 50 Ω or 75 Ω) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically this is provided by a distribution amplifier), with all other outputs except OUT03 disabled. Since grounded IN03 is programmed to drive OUT03, there should be no signal present. Any signal that is present can be attributed to the other seven hostile input signals because no other outputs are driven. (They are all disabled.) Thus, this method measures the allhostile input contribution to crosstalk into IN03. Of course, the method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN03 in the middle) are programmed to connect to IN00. OUT03 is programmed to connect to IN07 (far away from IN00), which is terminated to ground. Thus OUT03 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUT03 can be attributed to the output crosstalk of the other seven hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies, the magnitude of the crosstalk will be given by [( ) ] XT = 20 log10 R C ×s S M where RS is the source resistance, CM is the mutual capacitance between the test signal circuit and the selected circuit, and s is the Laplace transform variable. From the equation, it can be observed that this crosstalk mechanism has a high-pass nature; it can be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8108/AD8109 is specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8108/AD8109. From a circuit standpoint, this output crosstalk mechanism looks like a transformer, with a mutual inductance between the windings, that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by XT = 20 log 10 (Mxy × s R L ) where Mxy is the mutual inductance of Output x to Output y, and RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. Rev. B | Page 23 of 32 AD8108/AD8109 PCB LAYOUT The packaging of the AD8108/AD8109 is designed to help keep the crosstalk to a minimum. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board. These ground pins provide shielding, low impedance return paths, and physical separation for the inputs. All of these help to reduce crosstalk. Each output is separated from its two neighboring outputs by an analog ground pin in addition to an analog supply pin of one polarity or the other. Each of these analog supply pins provides power to the output stages of only the two nearest outputs. These supply pins and analog grounds provide shielding, physical separation, and a low impedance supply for the outputs. Individual bypassing of each of these supply pins with a 0.01 µF chip capacitor directly to the ground plane minimizes high frequency output crosstalk via the mechanism of sharing common impedances. Each output also has an on-chip compensation capacitor that is individually tied to the nearby analog ground pins AGND00 through AGND07. This technique reduces crosstalk by preventing the currents that flow in these paths from sharing a common impedance on the IC and in the package pins. These AGNDxx signals should all be directly connected to the ground plane. The input and output signals will have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The only place the input and output signals surface is at the input termination resistors and the output series back-termination resistors. These signals should also be separated, to the extent possible, as soon as they emerge from the IC package. Optimized for video applications, all signal inputs and outputs are terminated with 75 Ω resistors. Stripline techniques are used to achieve a characteristic impedance of 75 Ω on the signal input and output lines. Figure 52 shows a cross section of one of the input or output tracks along with the arrangement of the PCB layers. It should be noted that unused regions of the four layers are filled up with ground planes. As a result, the input and output traces, in addition to having controlled impedances, are well shielded. w = 0.008" (0.2mm) TOP LAYER b = 0.024" (0.6mm) a = 0.008" (0.2mm) t = 0.00135" (0.0343mm) SIGNAL LAYER h = 0.011325" (0.288mm) POWER LAYER BOTTOM LAYER 01068-058 Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. Figure 52. Cross Section of Input and Output Traces The board has 16 BNC type connectors: eight inputs and eight outputs. The connectors are arranged in two crescents around the device. As can be seen from Figure 53, this results in all eight input signal traces and all eight signal output traces having the same length. This is useful in tests such as all-hostile crosstalk where the phase relationship and delay between signals needs to be maintained from input to output. The three power supply pins AVCC, DVCC, and AVEE should be connected to good quality, low noise, ±5 V supplies. Where the same ±5 V power supplies are used for analog and digital, separate cables should be run for the power supply to the evaluation board’s analog and digital power supply pins. As a general rule, each power supply pin (or group of adjacent power supply pins) should be locally decoupled with a 0.01 µF capacitor. If there is a space constraint, it is more important to decouple analog power supply pins before digital power supply pins. A 0.1 µF capacitor, located reasonably close to the pins, can be used to decouple a number of power supply pins. Finally a 10 µF capacitor should be used to decouple power supplies as they come onto the board. Rev. B | Page 24 of 32 01068-053 AD8108/AD8109 01068-054 Figure 53. Component Side Silkscreen Figure 54. Board Layout (Component Side) Rev. B | Page 25 of 32 01068-055 AD8108/AD8109 01068-056 Figure 55. Board Layout (Signal Layer) Figure 56. Board Layout (Power Plane) Rev. B | Page 26 of 32 01068-057 AD8108/AD8109 Figure 57. Board Layout (Bottom Layer) Rev. B | Page 27 of 32 AD8108/AD8109 EVALUATION BOARD A 4-layer evaluation board for the AD8108/AD8109 is available. The exact same board and external components are used for each device. The only difference is the device itself, which offers a selection of a gain of unity or gain of 2 through the analog channels. This board has been carefully laid out and tested to demonstrate the specified high speed performance of the device. Figure 60 shows the schematic of the evaluation board. Figure 53 shows the component side silk-screen. The layouts of the board’s four layers are given in Figure 54, Figure 55, Figure 56, and Figure 57. The evaluation board package includes the following: • Fully populated board with BNC-type connectors. • Windows®-based software for controlling the board from a PC via the printer port. • Custom cable to connect evaluation board to PC. • Disk containing Gerber files of board layout. CONTROL THE EVALUATION BOARD FROM A PC The evaluation board includes Windows-based control software and a custom cable that connects the board’s digital interface to the printer port of the PC. The wiring of this cable is shown in Figure 58. The software requires Windows 3.1 or later to operate. To install the software, insert the disk labeled Disk 1 of 2 into the PC and run the file called SETUP.EXE. Additional installation instructions will be given on-screen. Before beginning installation, it is important to terminate any other Windows applications that are running. MOLEX 0.100" CENTER CRIMP TERMINAL HOUSING D-SUB 25 PIN (MALE) 14 1 RESET 1 CLK When you launch the crosspoint control software, you will be asked to select the printer port. Most modern PCs have only one printer port, usually called LPT1. However, some laptop computers use the PRN port. Figure 59 shows the main screen of the control software in its initial reset state (all outputs off). Using the mouse, any input can be connected with one or more outputs by simply clicking on the appropriate radio buttons in the 8 × 8 on-screen array. Each time a button is clicked on, the software automatically sends and latches the required 32-bit data stream to the evaluation board. An output can be turned off by clicking the appropriate button in the off column. To turn off all outputs, click on RESET. The software offers volatile and nonvolatile storage of configurations. For volatile storage, up to two configurations can be stored and recalled using the Memory 1 and Memory 2 buffers. These function in an identical fashion to the memory on a pocket calculator. For nonvolatile storage of a configuration, the save setup and load setup functions can be used. This stores the configuration as a data file on disk. OVERSHOOT OF PC PRINTER PORTS’ DATA LINES The data lines on some printer ports have excessive overshoot. Overshoot on the pin that is used as the serial clock (Pin 6 on the D-Sub-25 connector) can cause communication problems. This overshoot can be eliminated by connecting a capacitor from the CLK line on the evaluation board to ground. A pad has been provided on the solder side of the evaluation board to allow this capacitor to be soldered into place. Depending on the overshoot from the printer port, this capacitor may need to be as large as 0.01µF CE UPDATE DATA IN 6 DGND SIGNAL CE RESET UPDATE DATA IN CLK DGND EVALUATION BOARD 25 13 PC 01068-059 MOLEX D-SUB-25 TERMINAL HOUSING 2 3 3 1 4 4 5 5 6 2 25 6 01068-060 Figure 58. Evaluation Board-PC Connection Cable Figure 59. Evaluation Board Control Panel Rev. B | Page 28 of 32 AD8108/AD8109 AVEE AGND AVCC P1-4 P1-5 NC P1-7 P1-6 + DVCC + 0.1µF 10µF AVCC DVCC 0.01µF 0.01µF AVCC 0.01µF AVEE 0.01µF 0.01µF 0.1µF 10µF 0.1µF 10µF INPUT 00 75Ω 80 79 63 43 44 45 46 DGND DVCC DVCC AVCC AVCC AVEE AGND AGND 1 INPUT 00 2 AGND OUTPUT 00 AVEE AGND INPUT 01 75Ω 3 INPUT 01 4 AGND OUTPUT 01 AVCC AGND INPUT 02 75Ω 5 INPUT 02 6 AGND OUTPUT 02 AVEE AGND INPUT 03 75Ω 7 INPUT 03 8 AGND OUTPUT 03 AD8108/AD8109 AVCC AGND INPUT 04 75Ω OUTPUT 04 9 INPUT 04 10 AGND AVEE AGND OUTPUT 05 INPUT 05 75Ω 11 INPUT 05 12 AGND AVCC AGND OUTPUT 06 INPUT 06 75Ω 13 INPUT 06 14 AGND AVEE AGND OUTPUT 07 15 INPUT 07 16 AGND P2-2 AVEE 40 39 38 AVEE 0.01µF 75Ω 37 36 35 AVCC 0.01µF 75Ω 34 33 32 AVEE 0.01µF 75Ω 31 30 29 AVCC 0.01µF 75Ω 28 27 26 AVEE 0.01µF 75Ω 25 24 23 AVCC 0.01µF 75Ω 22 21 20 AVEE 0.01µF 75Ω 19 AVCC 18 AVCC 17 AVEE D3 D2 D1 D0 A2 A1 0.01µF A0 SER/PAR DATA IN 62 61 60 58 56 55 54 53 52 51 50 49 48 R25 20kΩ P2-3 DVCC P2-1 Rev. B | Page 29 of 32 P3-13 P3-12 P3-11 P3-10 P3-9 P3-8 P3-7 P3-6 P3-5 P3-4 Figure 60. Evaluation Board Schematic P3-14 NC P2-6 NC = NO CONNECT 75Ω 0.01µF P2-5 P2-4 AVCC DATA OUT UPDATE 57 41 0.01µF CLK 59 AVCC CE 75Ω RESET INPUT 07 42 SERIAL MODE JUMP 01068-052 CR1 CR2 1N4148 P3-3 + NC P1-3 DGND P1-2 P3-2 P1-1 P3-1 DVCC DGND AD8108/AD8109 OUTLINE DIMENSIONS 0.75 0.60 0.45 14.00 BSC SQ 1.60 MAX 80 61 60 1 PIN 1 12.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 20 41 21 VIEW A VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 40 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BDD Figure 61. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-1) Dimensions shown in millimeters ORDERING GUIDE1 Model AD8108AST AD8108ASTZ2 AD8109AST AD8109ASTZ2 AD8108-EB AD8109-EB 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Evaluation Board Package Option ST-80-1 ST-80-1 ST-80-1 ST-80-1 Details of the lead finish composition can be found on the ADI website at www.analog.com by reviewing the Material Description of each relevant package. Z = Pb-free part. Rev. B | Page 30 of 32 AD8108/AD8109 NOTES Rev. B | Page 31 of 32 AD8108/AD8109 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01068–0–9/05(B) Rev. B | Page 32 of 32