DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 ® DLP DLPA200 DMD Micromirror Driver Check for Samples: DLPA200 FEATURES 1 • • • • VBIAS_RAIL OUT15 VOFFSET_RAIL OUT14 VRESET_RAIL VRESET_RAIL OUT13 VOFFSET_RAIL OUT12 VBIAS_RAIL VBIAS_RAIL OUT11 VOFFSET_RAIL OUT10 VRESET_RAIL VRESET_RAIL OUT09 VOFFSET_RAIL OUT08 VBIAS_RAIL GND MODE1 MODE0 SEL1 SEL0 OEZ GND VBIAS_SWL VBIAS VBIAS_LHI P12V VRESET_SWL VRESET GND STROBE A3 A2 A1 A0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 GND RESETZ SCPENZ SCPDI SCPCK GND NC G NC NC P12V VOFFSET P12V V5REG GND DEV_ID1 DEV_ID0 IRQZ SCPDO GND VBIAS_RAIL OUT00 VOFFSET_RAIL OUT01 VRESET_RAIL VRESET_RAIL OUT02 VOFFSET_RAIL OUT03 VBIAS_RAIL VBIAS_RAIL OUT04 VOFFSET_RAIL OUT05 VRESET_RAIL VRESET_RAIL OUT06 VOFFSET_RAIL OUT07 VBIAS_RAIL • ETQFP PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 • Designed for use as a part of a DLP Chipset Generates the Micromirror Clocking Pulses required by the DLP Digital Micromirror Device (DMD) Generates specialized voltage levels required for micromirror clocking pulse generation Operates from a single 12-V power supply Provides a VBIAS voltage level, used by the DMD to control the array border mirrors Provides a VOFFSET voltage level, used by the DMD as DMDVCC2 All logic inputs are LVTTL and CMOS compatible Packaged in an Pb-free Thermally Enhanced Surface-Mount Package: 80-pin, 0.5 mm-pitch, enlarged terminal pitch, thin profile quad flat pack (eTQFP) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 • • 2 DESCRIPTION The DLPA200 is designed to be used as a part of a complete DLP chipset. A DLP chipset typically consists of a DMD, a DMD Controller, DMD Controller Firmware, and the DMD Micromirror Driver. Within a chipset, the DLPR200 is responsible for generating micromirror clocking pulses. These clocking pulses (also referred to as micromirror reset pulses) are what cause the DMD micromirrors to switch from one binary landed state to another (as dictated by the binary contents of the DMD CMOS memory array). A DMD Controller is responsible for writing data to the DMD CMOS memory array, and then commanding the DLPR200 to generate the required micromirror clocking pulses. The DLPA200 consists of three functional blocks: A High-Voltage Power Supply function, a DMD Micromirror Clock Generation function, and a Serial Communication function. The High-Voltage Power Supply function generates three specialized voltage levels: VBIAS (19 to 28 V), VRESET (–19 to –28 V), and VOFFSET (4.5 to 10 V). The Micromirror Clock Generation function uses the three voltages generated by the High-Voltage Power Supply function to create the sixteen micromirror clock pluses (output the OUTx pins of the DLPA200). The Serial Communication function allows the chipset Controller to: control the generation of VBIAS, VRESET, and VOFFSET; control the generation of the micromirror clock pulses; status the general operation of the DLPA200. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a registered trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Functional Block Diagram MODE[1:0] 2 SEL[1:0] 2 A[3:0] 4 STROBE Select, Latch, Output Logic and High-Voltage Output FET Switches 16 OUT(00–15) OEZ P12V Internal 5 V and Ref. Supplies V5REG VBIAS_RAIL VBIAS_LHI VBIAS Boost Converter VBIAS_SWL VBIAS VRESET_RAIL (SUBSTRATE) VRESET Buck-Boost Converter VRESET_SWL VRESET VOFFSET_RAIL VOFFSET Regulator VOFFSET SCPENZ SCPCK Serial Bus Interface SCPDI Power-Up Initialization Fault Logic IRQZ SCPDO DEV_ID[1:0] 2 GND RESETZ 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 Device Marking The device marking consists of the fields shown in Figure 1. Figure 1. Device Marking (Device Top View) TERMINAL FUNCTIONS TERMINAL NAME NO. I/O (INPUT DEFAULT) OUT00 22 Output OUT01 24 Output OUT02 27 Output OUT03 29 Output OUT04 32 Output OUT05 34 Output OUT06 37 Output OUT07 39 Output OUT08 62 Output OUT09 64 Output OUT10 67 Output OUT11 69 Output OUT12 72 Output OUT13 74 Output OUT14 77 Output OUT15 79 Output A0 19 Input (pull down) A1 18 Input (pull down) A2 17 Input (pull down) A3 16 Input (pull down) MODE0 3 Input (pull down) MODE1 2 Input (pull down) SEL0 5 Input (pull down) SEL1 4 Input (pull down) STROBE 15 Input (pull down) OE 6 Input (pull up) Asynchronous input controls whether the 16 OUTxx pins are active or are in a in high-impedance state. OE = 0 : Enabled. OE = 1 : High Z. RESET 59 Input (pull up) Resets the DLPA200 internal logic. Active low. Asynchronous. SCPEN 58 Input (pull up) Enables serial bus data transfers. Active low. DESCRIPTION 16 micromirror clocking waveform outputs (enabled by OE = 0). Output Address. Used to select which OUTxx pin is active at a given time. Mode Select. Used to determine the operating mode of the DLPA200. Output Voltage Select. Used to switch the voltage applied to the addressed OUTxx pin. A rising edge on STROBE latches in the control signals after a tri-state delay. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 3 DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O (INPUT DEFAULT) SCPDI 57 Input (pull down) Serial bus data input. Clocked in on the falling edge of SCPCK. SCPCK 56 Input (pull down) Serial bus clock. Provided by chipset Controller. SCPDO 42 Output Serial bus data output (open drain). Clocked out on the rising edge of SCPCK. A 1kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended. IRQ 43 Output Interrupt request output to the chipset Controller. Active low. A 1 kΩ pull up resistor to the Chip-Set Controller VDD supply is recommended. DEV_ID1 45 Input (pull up) DEV_ID0 44 Input (pull up) DESCRIPTION Serial bus device address: 00 = all; 01 = device 1; 10 = device 2; 11 = device 3. VBIAS 9 Power One of three specialized voltages which are generated by the DLPA200. VBIAS_LHI 10 Power Current limiter output for VBIAS supply. (also the VBIAS switching inductor input) VBIAS_SWL 8 Power Connection point for VBIAS supply switching inductor. VBIAS_RAIL 21, 30, 31, 40, 61, 70, 71, 80 Power (substrate) VRESET 13 Power One of three specialized voltages which are generated by the DLPA200. The package thermal pad is tied to this voltage level. VRESET_SWL 12 Power Connection point for VRESET supply switching inductor.. VRESET_RAIL (1) 25, 26, 35,36, 65, 66, 75, 76 Power VOFFSET 49 Power VOFFSET_RAIL 23, 28, 33, 38, 63, 68, 73, 78 Power GND 1, 7, 14, 20, 41, 46, 53, 55, 60 Power V5REG 47 Power The 5-volt logic supply output. P12V 11, 48, 50 Power The main power input to the DLPA200. NC 51, 52, 54 No Connect (1) 4 The internally-used VBIAS supply rail. Internally isolated from VBIAS. The internally-used VRESET supply rail. Internally isolated from VRESET. (1) One of three specialized voltages which are generated by the DLPA200. The internally-used VOFFSET supply rail. Internally isolated from VOFFSET. Common ground No connect Exposed thermal pad is internally connected to VRESET_RAIL. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under " Absolute Maximum Ratings” may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional performance of the device at these or any other conditions beyond those indicated under “ Recommended Operating Conditions” is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability. CONDITIONS P12V Load supply voltage VRESET_S VRESET_SWL Measured with respect to VRESET_RAIL VBIAS_R VBIAS_RAIL VOFFSET_R VOFFSET_RAIL VIN Logic inputs VOUT Open drain logic outputs TJ Maximum junction temperature TA Operating temperature range TSTORE Storage temperature range Rc-j Thermal resistance ESD MIN TYP MAX UNIT 14 V –1 V Measured with respect to VRESET_RAIL 60 V Measured with respect to VRESET_RAIL 40.5 V 7 V 7 V 125 °C 0 75 °C –55 150 °C –0.3 VBIAS = 26 V, VRESET = -26 V, VOFFSET = 10 V, Output load = 390 pF and 39R on each output, Phase by one with global mode, Channel repetition frequency = 50 kHz, Additional external loads: IBIAS = 5 mA, IOFFSET = 30 mA, I5REG = 30 mA Human Body Model Charge Device Model 3 °C/W 2 kV 800 V Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 5 DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS at TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Control Logic VIL Low-level logic input voltage VIH High-level logic input voltage 0.8 IIH High-level logic input current VIN = 5 V, input with pulldown. See terminal functions table. IIL Low-level logic input current VIN = 0 V, input with pullup. See terminal functions table. IIH High-level logic input leakage current VIN = 0 V, input with pulldown –1 1 IIL Low-level logic input leakage current VIN = 5 V, input with pullup –1 1 VOL Open drain logic outputs I = 4 mA IOL Logic output leakage current V = 3.3 V P12V supply current (1) Global shadow at 50 kHz, OUT load = 39 Ω and 390 pF, V5REG = 30 mA, VBIAS = 26 V at 5 mA, VOFFSET = 10V at 30 mA, VRESET = –26 V 1.97 V 40 –50 V 50 –40 µA µA µA µA 0.4 V 1 µA Power IP12V1 IP12V2 TJTSDR Thermal shutdown temperature With device temperature rising Delta between thermal shutdown and thermal warning Thermal warning temperature With device temperature rising Hysteresis (1) mA Outputs disabled and no external loads, VBIAS = 19 V, VOFFSET = 4.5 V, VRESET = –19 V Hysteresis TJTWR 200 22 mA 145 160 175 °C 5 10 15 °C 5 10 15 125 140 155 °C 5 10 15 °C MIN TYP MAX 4.75 5 5.25 °C During power up the inrush power supply current can be as high as 1 A for a momentary period of time. ELECTRICAL CHARACTERISTICS 5-V Linear Regulator TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) TEST CONDITIONS V5REG Output voltage IIL Output current: internal logic 4 20 IIE Output current: external circuitry 0 30 ICL5 Current limit VUV5 Undervoltage threshold VRIP Output ripple voltage (1) VOS5 Voltage overshoot at start up tss Power up (1) 6 Average voltage, I_out = 4 mA to 50 mA 80 I_out = 50 mA V mA mA mA V5REG voltage increasing, P12V = 5.4 V 4.1 V5REG voltage falling, P12V = 5.2 V 3.9 Measured between 10 to 90% of V5REG UNIT V 200 mVpk-pk 2 %V5REG 1 ms Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 ELECTRICAL CHARACTERISTICS Bias Voltage Boost Converter TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN IRL Output current: reset outputs Load = 400pF, 39 Ω, repetition frequency = 50 kHz IQL Output current: quiescent / drivers Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IDL Output current: DMD load ICLFB Current limit flag Corresponding current on output at P12V = 10.8 V ICLB Current limit Measured on input 330 VUVB VBIAS undervoltage threshold Bias voltage falling 50 VUVLHI VBIAS_LHI undervoltage threshold VBIAS_LHI voltage increasing 0 0 Boost switch Rdson VRIP Output ripple voltage (1) FSW Switching frequency VOSB Voltage overshoot at start up tss Power up tdis Discharge current sink (1) MAX UNIT 18 mA 3 mA 5 mA 30 VBIAS_LHI voltage falling RDS TYP TJ = 25°C mA 376 460 mA 92 %VBIAS 8 V 6.5 V Ω 2 1.35 1.5 Cout = 3.3 µF, Measured between 10 to 90% of target VBIAS 200 mVpk-pk 1.65 MHz 2 %VBIAS 1 ms 400 mA Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. ELECTRICAL CHARACTERISTICS Reset Voltage Buck-Boost Converter TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAMETER TEST CONDITIONS IRL Output current: reset outputs Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IQL Output current: quiescent / drivers Load = 400 pF, 39 Ω , repetition frequency = 50 kHz ICLFR Current limit flag Corresponding current on output at P12V = 10.8 V ICLR Current limit Measured on input VUVR Undervoltage threshold Reset voltage falling RDS Buck-boost switch Rdson TJ = 25°C VRIP Output ripple voltage (1) FSW Switching frequency VOSR Voltage overshoot at start up tss Power up tdis Discharge current sink (1) MIN TYP 0 MAX UNIT 18 mA 3 mA 25 mA 400 800 50 mA 92 %VRESET Ω 8 1.35 1.5 200 mVpk-pk 1.65 MHz 2 %VRESET Cout = 3.3 µF, Measured between 10 to 90% of target VRESET 1 400 ms mA Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 7 DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS VOFFSET/DMDVCC2 Regulator TA = 25°C, P12V = 10.8 V to 13.2 V (unless otherwise noted) PARAAMETER TEST CONDITIONS IRL Output current: reset outputs Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IQL Output current: quiescent / drivers Load = 400 pF, 39 Ω, repetition frequency = 50 kHz IDL Output current: DMDVCC2 ICLO Current limit VUVO Undervoltage threshold VRIP tdis Discharge time constant (1) 8 TYP MAX UNIT 12.2 mA 3 30 100 VOFFSET voltage falling 50 mA mA mA 92 %VOFFSET 100 VOSO Voltage overshoot at start-up Power up 0 0 Output ripple voltage (1) tss MIN mVpk-pk 2 %VOFFSET Cout = 4.7 µF, Measured between 10 to 90% of target VOFFSET 1 100 ms ms Output ripple voltage relies on suitable external components being selected and good printed circuit board layout practice. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Serial Communication Port Interface A (1) Setup SCPEN Low To SCPCK Reference to rising edge of SCPCK 360 ns B (1) Byte To Byte Delay Nominally 1 SCPCK cycle, rising edge to rising edge 1.9 µs Setup SCPDI To SCPEN High Last byte to slave disable 360 C (1) D (1) SCPCK Frequency (2) SCPCK Period E (1) ns 0 1.9 2 kHz µs 300 ns F (1) SCPDI Set-Up Time Reference to falling edge of SCPCK 300 ns G (1) SCPDI Hold Time Reference from falling edge of SCPCK 300 ns SCPDO Propagation Delay Reference from rising edge of SCPCK H SCPCK High Or Low Time 526 (1) 300 SCPEN, SCPCK, SCPDI, RESET Filter (Pulse Reject) 150 ns ns Output Micromirror Clocking Pulses FPREP Phased reset repetition frequency each output pin (non-overlapping) 50 kHz FGREP Global reset repetition frequency all output pins 50 kHz IRLK VRESET output leakage current OE = 1, VRESET_RAIL = -28.5V -1 -10 µA IBLK VBIAS output leakage current OE = 1, VBIAS_RAIL = 28.5V 1 10 µA IOLK VOFFSET output leakage current OE = 1, VOFFSET_RAIL = 10.25V 1 10 µA Output Micromirror Clocking Pulse Controls tSPW STROBE Pulsewidth 10 ns tSP STROBE Period 20 ns tOHZ Output Time To High Z OE Pin = High 100 ns tOEN Output Enable Time From High Z OE Pin = Low 100 ns tSUS Set-Up Time From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge 8 ns tHOS Hold time From A[3:0], MODE[1:0], and SEL[1:0] to STROBE edge 8 ns tPBR tPRO Propagation time tPOB From STROBE to VBIAS/VRESET edge 50% point. 80 200 ns From STROBE to VRESET/VOFFSET edge 50% point. 80 200 ns From STROBE to VOFFSET/VBIAS edge 50% point. 80 200 ns tDEL Edge-to-edge propagation delta Maximum difference between the slowest and fastest propagation times for any given reset output. 40 ns tCHCH Output channel-to-channel propagation delta Maximum difference between the slowest and fastest propagation times for any two outputs for any given edge. 20 ns (1) (2) See Figure 2 There is no minimum speed for the serial port. It can be written to statically for diagnostic purposes. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 9 DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com SCPENZ D A C E E B Clock 1 Byte 1 SCPCK F SCPDI X Clock 2 Byte 1 G F X H Clock 3 Byte 1 Clock 8 Byte 1 Clock 1 Byte 2 G F X X X H Clock 8 Last byte G X H SCPDO X = Don’t care Figure 2. Serial Interface Timing 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 PRINCIPLES OF OPERATION 5-V Linear Regulator The 5-V linear regulator supplies the 5 V requirement of the DLPA200 internal logic. Figure 3 shows the block diagram of this module. The input de-coupling capacitors are shared with other internal DLPA200 modules. See Component Selection Guidelines for recommended component values. 5 V Linear Regulator P12V V5REG GND Figure 3. 5-Volt Linear Regulator Block Diagram Bias Voltage Boost Converter The bias voltage converter is a switching supply that operates at 1.5 MHz. The bias switching device switches 180° out-of-phase with the reset switching device. The converter supplies the internal bias voltage for the high voltage FET switches and the external VBIAS for the DMD border mirrors. The VBIAS voltage level can be different for different generations of DMDs. The VBIAS voltage level is configured by the DLP Controller chip over a serial communication interface. Four control bits select the voltage level while a fifth bit is the on/off control. The module provides two status bits to indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions. Figure 4 shows the block diagram of this module. The input de-coupling capacitors are shared with other internal DLPA200 modules. See Component Selection Guidelines for recommended component values. Inductor VBIAS_LHI VBIAS_SWL P12V VBIAS V5REG BGAP REF OSC BIAS STATUS Serial Interface and Control BIAS CONTROL Bias Boost Converter and Current Limit 2 4 ENABLE GND Figure 4. Bias Voltage Boost Converter Block Diagram Reset Voltage Buck-Boost Converter The reset voltage buck-boost converter is a switching supply that operates at 1.5 MHz. The reset switching device switches 180° out-of-phase with the bias switching device. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 11 DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com The converter supplies the internal reset voltage levels for the high voltage FET switches. The VRESET voltage level can be different for different generations of DMDs. The VRESET voltage level is configured by the DLP Controller chip over a serial communication interface. Four control bits select the voltage level while a fifth bit is the on/off control. The module provides two status bits to indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions. Figure 5 shows the block diagram of this module. The input de-coupling capacitors are shared with other internal DLPA200 modules. See Component Selection Guidelines for recommended component values. P12V SWL VRESET V5REG BGAP REF OSC Serial Interface and Control RESET STATUS Reset Buck-Boost Converter and Current Limit VRESET_SWL 2 RESET CONTROL 4 Inductor ENABLE GND Figure 5. Reset Voltage Buck-Boost Converter Block Diagram VOFFSET/DMDVCC2 Regulator The VOFFSET/DMDVCC2 regulator supplies the internal VOFFSET voltage for the high voltage FET switches and the external DMDVCC2 for the DMD. The VOFFSET voltage level can be different for different generations of DMDs. The VOFFSET voltage level is configured by the DLP Controller chip over a serial communication interface.Four control bits select the voltage level while a fifth bit is the on/off control. The module provides 2 status bits to indicate latched and unlatched status bits for under-voltage (VUV) and current-limit (CL) conditions. Figure 6 shows the block diagram of this module. The input de-coupling capacitors are shared with other DLPA200 modules. See Component Selection Guidelines for recommended component values. P12V VOFFSET DMDVCC2 V5REG BGAP REF VOFFSET Linear Serial Interface and Control OFFSET STATUS 2 Regulator and Current Limit OFFSET CONTROL 4 ENABLE GND Figure 6. Offset Voltage Boost Convertor Block Diagram Driver Output Logic Block The clocking waveform present on each OUTxx pin is managed by the DLP Controller chip, as shown in Figure 7. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 OEZ UU[1:0] D Q SEL[1:0] D Q VRESET VOFFSET VBIAS A[3:0] D Q Shadow Enable MODE[1:0] GLOBAL SHADOW D D Q OUTPUT CONTROL DECODE LOGIC VOLTAGE SELECT Enable Q OUTPUT CONTROL LATCHES X16 BBM & DRIVERS X16 Reset Output Global or Adjacent ADJACENT SHADOW D Q STROBE RESETZ Figure 7. Driver Output Logic Block PWB LAYOUT AND ROUTING GUIDELINES WARNING Board layout and routing guidelines must be followed explicitly and all external components used must be in the range of values and of the quality recommended for proper operation of the DLPA200. Important: Thermal pad(s) must be tied to VRESET_RAIL, do not connect to ground. WARNING Thermal pad(s) must be tied to VRESET_RAIL, do not connect to ground. General Guidelines Suitable Kelvin connections should be provided for the switching regulator feedback pins: VBIAS (pin 9) and VRESET (pin 13). The etch traces that connect the switching devices: VBIAS_SWL (pin 8) and VRESET_SWL (pin 12) should be as short and wide as possible to minimize leakage inductances. The etch traces that connect the switching converter components (inductors, flywheel diodes and filtering capacitors) should also be as short and wide as possible. The electrical loops that these components form should be as small and compact as possible, with the ground referenced components forming a star connection. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 13 DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Due to the fast switching transitions appearing on the sixteen reset OUTx pins, it is recommended to keep these traces as short as possible. Also, to minimize potential cross-talk between outputs, it is advisable to maintain as much clearance between each of the output traces. Grounding Guidelines The PWB should have an internal ground plane that extends under the DLPA200. All 9 ground pins (1, 7, 14, 20, 41, 46, 53, 55, and 60) must be connected to the ground plane using the shortest possible runs and vias. All filter and bypass capacitors must be placed near the pin being filtered or bypassed for the shortest possible runs to the part and to the ground plane. Thermal Guidelines The DLPA200 package should be thermally bonded or soldered to an external thermal pad on the PWB surface. The recommended dimensions of the thermal pad are 10 x 10 mm centered under the part. The metal bottom of the package is tied internally to the substrate at the VRESET_RAIL voltage level. Therefore, the thermal pad on the board must be isolated from any other extraneous circuit or ground and no circuit vias are allowed inside the pad area. Thermal pads are required on both sides of the PWB and should be connected together through an array of 5 x 5 thermal vias, 0.5 mm in diameter. Thermal pads and the thermal vias are connected to VRESET_RAIL and isolated from ground, or any other circuit. An internal P12V or VBB plane should be located directly underneath the top layer and have an isolated area under the DLPA200. This isolated area must be a minimum of 20 cm2 and connect to the thermal pad of the DLPA200 through the thermal vias. The potential of the isolated area will also be at VRESET_RAIL. The internal ground plane should extend under the DLPA200 to help carry the heat away. Careful consideration should be taken with respect to DLPA200 placement in the vicinity of local PWB hotspots. Heat generated from adjacent components may impact the DLPA200 thermal characteristics. Power Supply Rail Guidelines Table 1 through Table 5 provides discrete component selection guidelines. The P12V filter and bypass capacitors should be distributed and connected to pin 11 and pins 48 & 50. These capacitors should be placed as near to their respective pins as possible and if necessary, should be placed on the bottom layer. The V5REG filter and bypass capacitors must be placed near and connected to pin 47. The VBIAS_RAIL etch runs should be routed in the following order: pin 40, pin 31, pin 30, pin 21, pin 80, pin 71, pin 70, and pin 61. The etch runs should be short and direct as they must carry 35 ns current spikes of up to 0.64 amps peak. Bypass capacitors should be located near and connected to pins 30 and 71 to provide bypassing on both sides. The VBIAS_LHI filter and bypass capacitors must be placed near and connected to pin 10. The VBIAS filter and bypass capacitors must be placed near and connected to pin 9. VBIAS pin 9 must also be connected (optionally with a 0-ohm resistor) to VBIAS_RAIL at or between pins 21 and 80. The VRESET_RAIL etch runs should be routed in the following order: pin 36, pin 35, pin 26, pin 25, pin 76, pin 75, pin 66, and pin 65. The etch runs should be short and direct as they must carry 35 ns current spikes of up to 0.64 amps peak. Bypass capacitors should be placed near and connected to pins 35 and 66 to provide bypassing on both sides. The VRESET filter and bypass capacitors must be located near and connected to pin 13. VRESET pin 13 must also be connected (optionally with a 0-ohm resistor) to VRESET_RAIL at or between pins 25 and 76. The VOFFSET_RAIL etch runs should be routed in the following order: pin 23, pin 28, pin 33, pin 38, pin 63, pin 68, pin 73, and pin 78. The etch runs should be short and direct as they must carry 35 ns current spikes of up to 0.64 amps peak. Bypass capacitors should be placed near and connected to pins 28 and 73 to provide bypassing on both sides. The VOFFSET filter and bypass capacitors must be placed near and connected to pin 49. VOFFSET pin 49 must also be connected (optionally with a 0-ohm resistor) to VOFFSET_RAIL at or between pins 38 and 63. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 WARNING Aluminum electrolytic capacitors may not be suitable for the DLPA200 application. At the switching frequencies used in the DLPA200 (up to 1.5MHz), aluminum electrolytic capacitors drop significantly in capacitance and increase in ESR resulting in voltage spikes on the power supply rails, which could cause the device to shut down or perform in an unreliable manner. COMPONENT SELECTION GUIDELINES Table 1. 5-V Regulator COMPONENT VALUE TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 P12V filter capacitor 10 to 33 µF, 20 VDC, 1Ω max ESR Tantalum or ceramic Pos: P12V, pin 11 (locate near pin 11) Neg: Ground P12V bypass capacitor 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic P12V, pin 11 (locate near pin 11) Ground V5REG filter capacitor 0.1 (1) to 1.0 µF, 10 VDC, 2.5Ω max ESR Tantalum or ceramic Pos: V5REG, pin 47 (locate near pin 47) Neg: Ground V5REG bypass capacitor 0.1 µF (1), 16 VDC, 0.1Ω max ESR Ceramic V5REG, pin 47 (locate near pin 47) Ground (1) To ensure stability of the linear regulator, the capacitance should not be less than 0.1 µF. Table 2. Bias Voltage Boost Converter CONNECTION 1 CONNECTION 2 Tantalum or ceramic Pos: VBIAS_LHI, pin 10 (locate near pin 10) Neg: Ground 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VBIAS_LHI, pin 10 (locate near pin 10) Ground VBIAS filter capacitor 1 to 10 µF, 35 VDC, 1Ω max ESR; (3.3 µF nominal value) Tantalum or ceramic Pos: VBIAS, pin 9 (locate near pin 9) Neg: Ground VBIAS bypass capacitor 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VBIAS, pin 9 (locate near pin 9) Ground VBIAS_RAIL bypass capacitors (2 required) 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VBIAS_RAIL, pins 30 and 71 (locate near pins 30 and 71) Ground Resistor jumper (optional) 0-ohm normally (1Ω for testing (1)) VBIAS, pin 9 VBIAS_RAIL, pins 21 or 80 Inductor 22 µH, 0.5 amp, 160 mΩ ESR Coil Craft DT1608C-223 (or equivalent) VBIAS_LHI, pin 10 VBIAS_SWL, pin 8 Schottky diode 0.5A, 40V (minimum) Motorola MBR0540T1 or STMicroelectronics STPS0540Z, STPS0560Z (or equivalent) Anode: VBIAS_SWL, pin 8 Cathode: VBIAS, pin 9 (1) COMPONENT VALUE LHI filter capacitor 10 µF, 20 VDC, 1Ω max ESR LHI bypass capacitor TYPE OR PART NUMBER Allows for VBIAS current measurement. Table 3. Reset Voltage Boost Converter COMPONENT VALUE VRESET filter capacitor 1 to 10 µF, 35 VDC, 1Ω max ESR; (3.3 µF nominal value) VRESET bypass capacitor 0.1 µF, 50 VDC, 0.1Ω max ESR TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 Tantalum or ceramic Neg: VRESET, pin 13 (locate near pin 13) Pos: Ground Ceramic VRESET, pin 13 (locate near pin 13) Ground Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 15 DLPA200 DLPS015A – APRIL 2010 – REVISED JUNE 2010 www.ti.com Table 3. Reset Voltage Boost Converter (continued) COMPONENT VALUE VRESET_RAIL bypass capacitors (2 required) 0.1 µF, 50 VDC, 0.1Ω max ESR Resistor jumper (optional) 0-ohm normally (1Ω for testing (1)) Inductor 22 µH, 0.5A, 160 mΩ Schottky diode 0.5 A (minimum), 60 V (1) TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 VRESET_RAIL, pins 35 and 66 (locate near pins 35 and 66) Ground VRESET, pin 13 VRESET_RAIL, pins 25 or 76 Coil Craft DT1608C-223 (or equivalent) VRESET_SWL, pin 12 Ground STMicroelectronics STPS0560Z or International Rectifier 10MQ060N (or equivalent) Cathode: VRESET_SWL, pin 12 Anode: VRESET, pin 13 Ceramic Allows for VRESET current measurement. Table 4. Offset Voltage Regulator (1) (2) (3) (4) COMPONENT VALUE VOFFSET/VCC2 filter capacitors (2 required) 1.0 (1) to 4.7 (2) µF, 35 VDC, 1Ω max ESR VOFFSET/VCC2 bypass capacitors (5 required) TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 Tantalum or ceramic Pos: VOFFSET, pin 49 (1st near pin 49) Pos: DMDVCC2 pins (locate 2nd at DMD) Neg: Ground at DLPA200 Neg: Ground at DMD 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VOFFSET, pin 49 (locate 1 near pin 49) DMD DMDVCC2 pins (locate 4 near DMD pins) Ground at DLPA200 Ground at DMD VOFFSET_RAIL bypass capacitor (2 required) 0.1 µF, 50 VDC, 0.1Ω max ESR Ceramic VOFFSET_RAIL, pins 28 and 73 (locate near pins 28 and 73) Ground Resistor jumper (optional) 0-ohm normal (1Ω for testing (3)) VOFFSET, pin 49 VOFFSET_RAIL, pins 38 or 63 Resistor jumper (optional) 0-ohm normal (1Ω for testing (4)) VOFFSET, pin 49 DMDVCC2 pins To ensure stability of the linear regulator, the absolute minimum output capacitance should not be less than 1.0 µF. Recommended value is 3.3 µF each. Different values are acceptable, provided that the sum of the two is 6.8 µF maximum. Allows for VOFFSET current measurement Allows for DMDVCC2 current measurement Table 5. Pullup Resistors COMPONENT 16 VALUE TYPE OR PART NUMBER CONNECTION 1 CONNECTION 2 Resistor 1 kΩ SCPDO, pin 42 Chipset controller 3.3-V VDD Resistor 1 kΩ IRQ, pin 43 Chipset Controller 3.3-V VDD Resistor (optional) 1 kΩ OE, pin 6 Chipset Controller 3.3-V VDD Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 DLPA200 www.ti.com DLPS015A – APRIL 2010 – REVISED JUNE 2010 Revision History REVISION DATE SECTION(S) COMMENT * March 2010 All Initial release A June 2010 Device Marking Modified Device marking to show TI internal part number Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): DLPA200 17 PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DLPA200PFC ACTIVE TQFP PFC 80 1 Pb-Free (RoHS) Call TI Level-2-260C-1 YEAR Purchase Samples DLPA200PFCT ACTIVE TQFP PFC 80 10 Pb-Free (RoHS) Call TI Level-2-260C-1 YEAR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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