INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4024 7-stage binary ripple counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 7-stage binary ripple counter 74HC/HCT4024 The counter advances on the HIGH-to-LOW transition of CP. FEATURES • Output capability: standard A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. • ICC category: MSI Each counter stage is a static toggle flip-flop. GENERAL DESCRIPTION Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. The 74HC/HCT4024 are high-speed Si-gate CMOS devices and are pin compatible with the “4024” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. APPLICATIONS • Frequency dividing circuits The 74HC/HCT4024 are 7-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). • Time delay circuits QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT tPHL/ tPLH propagation delay CP to Q0 14 14 ns fmax maximum clock frequency 90 70 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package 25 27 pF CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification 7-stage binary ripple counter 74HC/HCT4024 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 CP clock input (HIGH-to-LOW, edge-triggered) 2 MR master reset input (active HIGH) 12, 11, 9, 6, 5, 4, 3 Q0 to Q6 parallel outputs 7 GND ground (0 V) 8, 10, 13 n.c. not connected 14 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 7-stage binary ripple counter 74HC/HCT4024 FUNCTION TABLE INPUTS OUTPUTS CP MR Qn ↑ ↓ X L L H no change count L Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition ↓ = HIGH-to-LOW clock transition Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification 7-stage binary ripple counter 74HC/HCT4024 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +125 −40 to +125 min. typ. max. min. max. min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to Q0 47 17 14 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.6 tPHL propagation delay MR to Q0 63 23 18 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay Qn to Qn+1 25 9 7 80 16 14 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 tW clock pulse width HIGH or LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tW master reset pulse width HIGH 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 trem removal time MR to CP 50 10 9 6 2 2 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.6 fmax maximum clock pulse frequency 6.0 30 35 27 82 98 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification 7-stage binary ripple counter 74HC/HCT4024 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT CP MR 0.75 0.85 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +125 −40 to +125 min. typ. max. min. max. min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to Q0 17 35 44 53 ns 4.5 Fig.6 tPHL propagation delay MR to Q0 21 40 50 60 ns 4.5 Fig.6 tPHL/ tPLH propagation delay Qn to Qn+1 9 16 20 24 ns 4.5 Fig.6 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 16 9 20 24 ns 4.5 Fig.6 tW master reset pulse width HIGH 16 6 20 24 ns 4.5 Fig.6 trem removal time MR to CP 10 0 13 15 ns 4.5 Fig.6 fmax maximum clock pulse frequency 30 64 24 20 MHz 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification 7-stage binary ripple counter 74HC/HCT4024 AC WAVEFORMS Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7